KR100797732B1 - Wdm-pon ethernet adapat apparatus for adaption speed of ehternet line - Google Patents

Abstract

A WDM-PON(Wavelength Division Multiplexing Passive Optical Network) Ethernet adapter apparatus adaptable to speed of an Ethernet line is provided to maximize transmission efficiency by accepting Ethernet frames. A WDM-PON(Wavelength Division Multiplexing Passive Optical Network) Ethernet adapter apparatus adaptable to speed of an Ethernet line comprises a flow controller(210) and a physical module(220). The flow controller(210) controls quantity of traffics of Ethernet frames and controls receipt or transmission of signals according to an access protocol which is the same as the access protocol of the Ethernet interface. The physical module(220) adjusts an internal clock such that a speed demanded by the Ethernet interface gets accorded with a speed provided by one wavelength of the WDM-PON if the speed demanded by the Ethernet interface is different from the speed provided by one wavelength of the WDM-PON, and accepts the Ethernet frames outputted by the Ethernet interface.

Description

TECHNICAL FIELD [0001] The present invention relates to a WDM-PON Ethernet adapter device capable of adapting an Ethernet line speed.

1 is a configuration diagram of a WDM-PON Ethernet adapter apparatus according to an embodiment of the present invention;

2 is a detailed configuration diagram of the WDM-PON Ethernet adapter device of FIG.

3 illustrates in detail each functional block and input signal source of a variable clock generator for Ethernet line rate adaptation;

Description of the Related Art

100: Ethernet interface (GMII / MII) 200: Ethernet adapter device

300: band matching unit 210: flow control unit

220: PHY module unit 211: frame reception buffer

212: flow control signal generator 260: transmitter

213, 231: a cyclic redundancy check (CRC)

214: frame transmission buffer 230:

240: Variable clock generator 250: Receive clock generator

232: Coding unit 233: FIFO (First In First Out)

234: PTS (Parallel to Serial) 235: Transmission buffer

261: Transmission buffer 262: STP (Serial to Parallel)

263:

The present invention relates to a WDM-PON Ethernet adapter capable of adapting to an Ethernet line speed, and more particularly, to a WDM-PON Ethernet adapter capable of adapting an Ethernet frame when an incompatibility between the required speed of the Ethernet interface and the speed provided by one wavelength of the WDM- Thereby maximizing the transmission efficiency.

Recently, a transition from a conventional copper-based network to a fiber-based network has been rapidly made, and wavelength-division multiplexing (WDM) technology has been applied to cope with the demand of an increasing bandwidth of a network .

WDM technology is a transmission method that simultaneously transmits optical signals having several different wavelengths to one optical fiber, and can stably increase the transmission capacity while minimizing the optical fiber.

Accordingly, a wavelength division multiplexing passive optical network system (hereinafter, referred to as WDM-PON) in which WDM technology is applied in a recently-defined optical fiber infrastructure is under active development.

The WDM-PON is a subscriber network technology that transmits data from an OLT in a home office to a remote node through a single optical fiber cable, and transmits data from a remote site to an optical network unit (ONU) through individual wavelengths.

Ethernet, on the other hand, has evolved to 100Mbps and 1Gbps, which uses 4B / 5B and 8B / 10B code over 10Mbps, which used Manchester code, and is getting even faster. Therefore, the Ethernet transmission rate is relatively large.

In contrast, the rate at which a WDM-PON can transmit through one wavelength has various values ranging from 100 Mbps to 500 Mbps, 1 Gbps, etc. depending on the distance of the optical cable and the wavelength of the wavelength used.

Of course, in the WDM-PON, the transmission rate in the range of 100 ~ 500Mbps including the case of transmitting per unit wavelength is variable according to the distance and wavelength used in the same technology base, so it is preferable to utilize the maximum transmission rate Since it can accommodate many subscribers, it will be advantageous in terms of bandwidth utilization.

If one wavelength is regarded as a simple transmission channel in this WDM-PON, it is required to provide a transmission rate of 125 Mbps or 1.25 Gbps per wavelength in order to accommodate Ethernet of 100 Mbps or 1 Gbps to satisfy IEEE802.3 standard .

However, the conventional WDM-PON has an inefficient problem that it can only accept 100 Mbps Ethernet even if one wavelength has a transmission capacity of 210 Mbps, 220 Mbps or 500 Mbps.

Therefore, in order to solve the above-mentioned problem, when the Ethernet interface required speed and the speed provided by one wavelength of the WDM-PON do not coincide with each other, the Ethernet frame is accepted by matching the speed mismatch using the variable clock generator , And to maximize transmission efficiency.

In order to achieve the above object, the WDM-PON Ethernet adapter device capable of adapting the Ethernet line speed according to the embodiment of the present invention controls traffic volume of an Ethernet frame and controls to transmit and receive signals with the same connection standard as the Ethernet interface And a control unit for controlling the internal clock so as to coincide with a request speed of the Ethernet interface and a speed provided by one wavelength of a WDM-PON (WDM-PON), so as to accommodate the Ethernet frame output from the Ethernet interface. And a PHY (physical) module unit for performing a PHY operation.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a WDM-PON Ethernet adapter apparatus 200 capable of adapting an Ethernet line rate according to an embodiment of the present invention.

The Ethernet adapter device 200 includes a flow control unit 210 and a physical layer (PHY) module unit 220.

The flow control unit 210 controls the amount of traffic of the Ethernet frame. The flow control unit 210 may be a gigabit-ethernet independent independent interface (GMII) or a multimedia independent interface (MII) Or the like, to the same interface as the Ethernet interface 100 of FIG.

The PHY module 220 variably generates its own internal clock using information provided by the band matching unit 300 that measures the quality of a WDM (Wavelength-Division Multiplexing) transmission interval and determines an optimal transmission rate. That is, the PHY module unit 220 generates a clock according to the operation speed and processes the serial signal. At this time, the PHY module 220 performs a function according to the international standard IEEE802.3 PHY chip, but the transmission speed is lower than that of the wavelength division multiplexing passive optical network system (WDM-PON) The maximum transmission rate is matched.

Meanwhile, the band matching device 300, which is a lower layer of the Ethernet adapter device 200, performs a band setting function. Since the degree of attenuation varies depending on the distance and wavelength of the optical signal, the performance of the WDM-PON may be different from that of the WDM-PON. For example, since it is possible to transmit data from several tens of Mbps to several hundreds of Mbps per wavelength, OLT (Optical Line Termination) located at the national office and ONU (Optical Network Unit) located at the subscriber side among constituent elements of the WDM- The optimal transmission rate is determined in a given environment. The transmission rate thus set becomes a transmission limit value for transmitting a physical signal for each wavelength.

That is, when the WDM-PON is initially initialized, the band matching unit 300 determines the optimal transmission rate in the process of determining the variable physical speed between the OLT and the ONU (or ONT) Up table that records the maximum speed that can be transmitted depending on the environment.

Accordingly, the PHY module 220 can maintain the maximum transmission efficiency by variably generating a line clock with reference to the lookup table. As a result, the PHY module 220 can arbitrarily set the transmission clock rate to any arbitrary value such as 210 Mbps, 220 Mbps, or 500 Mbps The band can be provided at the operating speed.

2 is a detailed configuration diagram of the WDM-PON Ethernet adapter apparatus 200 of FIG.

The flow control unit 210 includes a frame reception buffer 211, a flow control signal generation unit 212, a cyclic redundancy check (CRC) checking unit 213, and a frame transmission buffer 214.

The frame reception buffer 211 stores the Ethernet frame when it is received from the Ethernet interface (GMII / MII) 100. Here, if the transmission speed of the physical layer (not shown) of the WDM-PON is lower than that of the Ethernet interface 100, the frame reception buffer 211 temporarily stores the Ethernet frame received from the Ethernet interface 100 To match the transmission speed of the physical layer of the WDM-PON. For this purpose, it is desirable that the frame reception buffer 211 has a sufficient size to be capable of buffering the instantaneous incoming traffic.

Although not shown in FIG. 2, the physical layer (not shown) of the WDM-PON is connected to the band matching device 300 and receives signals processed through the WDM-PON Ethernet adapter 200, All or a part of the wavelengths are accommodated in one wavelength, or only one of the different signals corresponding to each wavelength is associated with each other and transmitted to an optical network unit (ONU) as individual wavelengths.

On the other hand, the flow control signal generator 212 sends an alert signal to the external (Ethernet MAC layer) when the storage amount of the frame reception buffer 211 reaches a certain threshold value.

In general, a method of reliably limiting the amount of Ethernet traffic flowing through the Ethernet interface 100 to a transmission rate or less provided by the physical layer (not shown) of the WDM-PON may be limited by limiting the number of subscriber ports, To control the amount of traffic flowing through. This can be controlled via operational parameters when initializing the system regardless of the warning signal, and the processor can intelligently control when a warning signal is given via the host interface. However, since the subscribers do not always transmit data at the maximum data rate provided by the physical layer, it is necessary to allow oversubscribing to some degree, thereby increasing the efficiency of the network. Therefore, when the traffic is instantaneously flooded, the frame reception buffer 211 reaches a certain threshold, and the flow control signal generator 212 generates a warning signal accordingly.

In this manner, when the alert signal is generated in the flow control signal generator 212, the Ethernet interface 100 is solved by the following two methods. The first is to use an Ethernet backpressure. This is hypothesized to be a frame collision situation and informs the Ethernet interface 100 that the response speed is fast in such a manner that the frame is not sent for a given back off time. Since the signal existing on the Ethernet interface 100 can be used, it can be implemented simply.

The second is a method of generating a pause frame so that the subscriber can not generate traffic to the subscriber for the time specified in the frame. A pause frame may be generated in the Ethernet adapter device 200 and transmitted in a reverse direction or may be generated and transmitted by a processor that senses an alert signal through a host interface. Compared to Ethernet Backpressure, it has a somewhat complicated implementation and a slow response but strong controllability. At this time, a pause frame is a kind of hardware signal which is generated to monitor overflow of a buffer in the Ethernet adapter apparatus 200 to prevent overflow.

The CRC checker 213 uses a cyclic binary code to detect an error occurring in the data transmission process. The CRC checker 213 divides the data into blocks on the transmission side and adds a cyclic code obtained by the special calculation of the binary polynomial to each block, , It is checked whether or not a transmission error is caused by whether or not the same cyclic code is obtained by the same calculation on the receiving side. This method is more accurate than the method using parity bits, so it has excellent error detection capability and is simple in error detection circuit of encoder and decoder, and is used in communication protocols such as X-Modem and Commit.

The frame transmission buffer 210 temporarily stores transmission data received from the transmission unit 260 and transmits the transmission data to the Ethernet interface 100.

The PHY module 220 includes a receiving unit 230, a variable clock generator 240, a receiving clock regenerator 250, and a transmitting unit 260.

The receiving unit 230 includes a CRC checking unit 231, a coding unit 232, a FIFO (First In First Out) 233, a PTS (parallel to serial) 234, and a transmission buffer 215.

The CRC checking unit 231 performs a CRC check on the frame received from the frame receiving buffer 211. [ The CRC checking unit 231 preferably has the same function as the CRC checking unit 213.

The coding unit 232 performs 8B / 10B (in case of GMII) or 4B / 5B (MII) coding of the output signal of the CRC checking unit 231 and the FIFO 233 outputs a signal output from the coding unit 232 And the PTS 234 converts the parallel signal output from the FIFO 233 into a serial signal. The transmission buffer 235 buffers the output signal of the PTS 234 and transmits the buffered signal to the band matching unit 300.

That is, the receiving unit 230 performs a CRC check on the frame read from the frame receiving buffer 211 and then flows into the FIFO 313 through 8B / 10B (in case of GMII) or 4B / 5B (MII) Serialized by the PTS 234, and then transmitted to the band matching device 300 through the transmission buffer 315.

The variable clock generator 240 generates a variable clock according to an output signal of the band matching device 300 and transmits the generated clock to the receiver 230.

The reception clock regenerator 250 generates a clock signal according to an output signal of the band matching unit 300 and transmits the generated clock signal to the transmission unit 260.

The transmission unit 260 includes a reception buffer 261, a serial to parallel (STP) 262, and a decoding unit 263. [

The receiving buffer 261 buffers the signal output through the band matching unit 300 and the STP 262 converts the serial signal output from the receiving buffer 261 into a parallel signal. The decoding unit 263 decodes the STP And transmits the decoded signal to the frame transmission buffer 214.

That is, the transmitting unit 260 converts the signal input through the band matching unit 300 into a parallel signal from the STP 262 via the receiving buffer 261, decodes it in the coding unit 262, 214).

In this way, the PHY module unit 220 of the Ethernet adapter apparatus 210 of the present invention is functionally similar to the international standard IEEE 802.3 Ethernet PHY function (PCS + PMA), but the internally operating speed is equivalent to the international standard IEEE 802.3 Ethernet It is different from PHY.

That is, according to the WDM-PON transmission rate information provided by the band matching unit 300, the PHY module unit 220 of the present invention can transmit not only standard speeds of 125 Mbps and 1250 Mbps but also arbitrary Lt; RTI ID = 0.0 > physical < / RTI >

Hereinafter, with reference to FIG. 3, the operation of the variable clock generator 240 for adapting the Ethernet line speed of FIG. 2 will be described in detail.

)로 분주한 값을 출력으로 제공하여 임의의 동작속도를 위한 클럭을 발생시킨다.3, when the reference clock R [Hz] is given, the variable clock generator 240 sets the frequency to 1 / (n + 1)

) As an output to generate a clock for an arbitrary operating speed.

To this end, the variable clock generator 240 includes a counter 241, a decoder 242, a selector 243, and a register 244.

The counter 241 operates based on the reference clock as an input source. 0 (decimal 0) to 11 ... 1 < / RTI ^> (decimal number 2 < ^{RTI ID =} 0.0 > ^m- 1). ≪ / RTI >

으로 디코딩하여 출력한다. 즉, 디코더(242)는 카운터(241)로부터 출력되는 m 개의 출력신호를 해독하고, 그 해독된 값에 따라 해당하는 출력으로 신호를 발생시킨다. 또한, 디코더(242)는 2^m 개의 출력선 (L₀, L₁, …L_2m-1)을 가지고 있으며, 카운터(241)의 값에 따라 어느 순간에 단 하나의 출력선에서만 하이레벨의 출력신호를 출력한다.The decoder 242 receives the output signal of the counter 241

And outputs the decoded data. That is, the decoder 242 decodes the m output signals output from the counter 241, and generates signals corresponding to the decoded values. Also, the decoder 242 has 2 ^m output lines (L ₀ , L ₁ , ..., L _2m-1 ), and according to the value of the counter 241, at a certain moment, And outputs a signal.

The selector 243 selects one of 2 ^m output signals received from the decoder 242. That is, the selector 243 selects only one of the 2 ^m outputs of the decoder 322 according to the value of the register 244 and sends the final output. The final output of the selector 243 is output to the Ethernet adapter 200, As shown in Fig.

The register 244 is implemented with an m-bit register that stores a variable value (n) for controlling the output value of the selector 243. That is, the register 244 having an m-bit length determines the output value by referring to the value of the look-up table of the band matching device 300, and the output value is an element that determines the operation speed of the clock.

Hereinafter, a process of determining the operating clock speed of the variable clock generator 240 of FIG. 3 will be described in detail.

If the reference clock R [Hz] is normally supplied through the commercial process chip and the reference clock R [Hz] is divided by R / (n + 1) [Hz], the value of the register 244 is set to n However, it may be set to 0? 2 ^m -1.

Initially, when the counter 241 starts counting from 0 and counts n, that is, when the clock passes n + 1 cycles, the output of the decoder 242 goes from L ₀ to L _n once at a high level.

At this time, if the value of the register 244 is set to n, the selector 243 selects only L _{n as the} output, so that the final output becomes high level only once during the elapse of the reference clock n + 1 cycle .

Since the final output of the selector 243 acts as a reset signal of the counter 241, the counter 241 again counts from 0 to n from the beginning.

Accordingly, the variable clock device 240 performs a function of dividing the reference clock by (n + 1) according to the value n set in the register 244.

Tables 1 and 2, illustrated below, show the output clock values divided by the value of the register 244, respectively, given the reference clocks of 1000 MHz and 2100 MHz. Since the implementation process (FPGA) that is commercialized has a built-in PLL, it can easily generate a reference clock of 1000 MHz or 2100 MHz by multiplying it by 8 or 16 times by receiving 125 MHz clock from GMII.

Ref. CLK n +1 One 2 3 4 5 6 7 8 1000 1000 500.0

333.

250.0 210.0 166.

142.9 125 2100 2100 1000 666.

500.0 400.0 333.

285.7 250

Ref. CLK n +1 9 10 11 12 13 14 15 16 1000

111.

100.0 90.9 83.

76.9 71.4 66.

62.5 2100 222.

210.0 181.8 166.

153.8 142.9 133.

125.0

Table 1 shows the reference clock divided by 1000 MHz and the value of n. Table 2 shows the reference clock divided by 2100 MHz and the clock value divided by n. The unit is MHz.

For example, if the transmission rate that one wavelength can provide in the WDM-PON is a value between 100 and 500 Mbps depending on a given environment, a counter 241 using a reference clock of 1000 MHz and m = Can provide seven clocks, and it can provide 13 different clocks using 2100 MHz and a counter (241) with m = 4 bits. Therefore, as the value of the reference clock is large and the length of the counter becomes longer, various values can be provided.

In this way, when the required rate of the Ethernet interface and the speed provided by one wavelength of the WDM-PON do not match, that is, when the transmission rate provided per wavelength is higher or lower than the transmission rate requested by the Ethernet, 240), the Ethernet frame can be accommodated and the transmission efficiency can be maximized.

Further, by using the apparatus of the present invention, WDM-PON can be applied to FTTC (Fiber to the Curb), FTTCab (Fiber to the Cabinet), FTTB (Fiber to the Building) including FTTH -PON, it is possible to maximize the transmission efficiency and appropriately adjust the bandwidth provided per subscriber.

For example, when the Ethernet adapter device 200 of the present invention is applied to a subscriber area requiring 30 Mbps, providing 500 Mbps per wavelength can provide about 5 times efficiency at a minimum cost.

As described above, according to the present invention, when the Ethernet interface required speed and the speed provided by one wavelength of the WDM-PON are inconsistent, the Ethernet frame is accommodated by matching the speed mismatch using the variable clock generator, There is a maximizing effect.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. As well.

Claims (15)

A flow control unit for controlling an amount of traffic of the Ethernet frame and controlling the sending and receiving of the signal with the same connection standard as the Ethernet interface; And (PHY) for accommodating an Ethernet frame output from the Ethernet interface by varying an internal clock so that a required speed of the Ethernet interface matches a speed provided by one wavelength of a WDM-PON (WDM-passive optical network) physical module unit. The WDM-PON Ethernet adapter device is adaptable to Ethernet line speed. 2. The apparatus of claim 1, A frame reception buffer for storing an Ethernet frame received from the Ethernet interface; A flow control signal generator for generating an alert signal to the Ethernet interface when the storage amount of the frame reception buffer reaches a predetermined threshold value; And A frame transmission buffer for storing transmission data received from the PHY module and transmitting the transmission data to the Ethernet interface; Wherein the WDM-PON Ethernet adapter device is capable of adapting the Ethernet line rate. 3. The apparatus of claim 2, And the Ethernet frame received from the Ethernet interface is temporarily stored to match the transmission rate of the physical layer of the WDM-PON when the transmission rate of the physical layer of the WDM-PON is lower than the rate of the Ethernet layer. WDM-PON Ethernet adapter device with adaptable Ethernet line rate. The apparatus of claim 2, wherein the Ethernet interface comprises: Wherein when the warning signal is received from the flow control signal generator, the number of subscriber ports is limited or the amount of traffic flowing through port parameter control is adjusted. The apparatus of claim 2, wherein the Ethernet interface comprises: Wherein when the warning signal is received from the flow control signal generator, the subscriber does not allow the subscriber to generate traffic for a time specified in the frame. The method according to claim 1, And a bandwidth matcher for determining an optimal transmission rate of the WDM-PON transmission interval. The WDM-PON Ethernet adapter according to claim 1, 7. The apparatus of claim 6, A receiving unit for receiving the Ethernet frame through the flow control unit, coding and serializing the Ethernet frame, and outputting the encoded Ethernet frame to the band matching unit; A variable clock generator for varying an internal clock according to an output signal of the band matching unit and applying the variable clock to the receiver; A transmitter for parallelizing and decoding a transmission signal applied through the band matching unit and applying the parallelized and decoded signals to the flow control unit; And And a reception clock regenerator for generating a clock signal according to an output signal of the band matching unit and applying the generated clock signal to the transmission unit. 8. The apparatus of claim 7, A CRC checking unit for performing a CRC check on the received Ethernet frame; A coding unit for coding an output signal of the CRC checking unit; A FIFO for outputting an output signal of the coding unit in a FIFO manner; A PTS (Parallel to Serial) for converting a signal output from the FIFO into a serial signal; And And a transmission buffer for buffering a signal output from the PTS and transmitting the signal to the band matching unit. 8. The apparatus of claim 7, A receiving buffer for buffering a transmission signal received from the band matching unit; An STP (Serial to Parallel) for parallelizing the transmission signal output from the reception buffer; And And a decoding unit decoding the parallel transmission signal and applying the decoding result to the flow control unit. 8. The variable clock generating circuit according to claim 7, A counter for counting the reference clock as an input source; A decoder for decoding the output signal of the counter and outputting a plurality of output signals; A selector for selecting one of the plurality of output signals and applying the selected one to the PHY module; And And a register for storing a variable value for controlling an output value of the selection unit. The WDM-PON Ethernet adapter apparatus according to claim 1, 11. The apparatus of claim 10, According to the change of the reference clock, OO ... 0 (decimal 0) to 11 ... 1 < / RTI ^> (decimal number 2 ^{m <} -1) < / RTI > of the WDM-PON Ethernet adapter. 12. The apparatus of claim 11, The m output signals

And the WDM-PON Ethernet adapter device is capable of adapting the Ethernet line rate. 13. The apparatus of claim 12, And receives an output signal of the selection unit as a reset signal. 14. The semiconductor memory device according to claim 13, And the variable value is determined by referring to a value of a lookup table stored in the band matching unit. 15. The apparatus according to claim 14, And outputting the output signals of the decoder according to a variable value of the register and outputting the selected signals.

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