KR100788500B1 - Vertex processing apparatus and method having multi-stage pipeline structure - Google Patents

Abstract

A device and a method for processing a vertex in a multi-stage pipeline structure are provided to reduce the maximum delay between respective execution codes to three stages by using an ALU(Arithmetic Logic Unit) of the multi-stage pipeline structure sequentially connecting operators. A first resister(310a) stores data for processing the vertex and a second register stores an operating result. An instruction fetch unit(300) sequentially fetches an instruction including an OP(Operation) code and more than one operand. A decoding unit(320) decodes the instruction and reads the needed data from the first register according to the operand. The ALU(330) comprises a plurality of operators, and sequentially processes/outputs the data through more than one operator according to a type of the OP code. A write back unit(340) stores an operation result of the prior OP code to a second register(310b) and temporally stores other results in the inside to process other result in the next stage.

Description

Vertex processing apparatus and method having multi-stage pipeline structure

1 is a diagram illustrating a pipeline flow of a conventional executable code.

2 is a diagram illustrating execution code classification of instructions according to an exemplary embodiment of the present invention.

Figure 3 is a block diagram of a vertex processing apparatus according to an embodiment of the present invention.

FIG. 4 shows an example of pipeline flow in the vertex processing apparatus shown in FIG. 3. FIG.

5 is another example of a multi-stage pipeline flow in the vertex processing apparatus shown in FIG.

6 is a flowchart of an arithmetic operation method in an arithmetic logic module according to a preferred embodiment of the present invention.

7 is a flowchart illustrating a calculation result processing method in a writeback module according to an exemplary embodiment of the present invention.

8 is a flowchart of a method of processing a vertex with reduced delay time due to a replacement of a register according to another exemplary embodiment of the present invention.

9 is a diagram illustrating a delay time according to the replacement of a conventional register.

10 illustrates a vertex processing method with reduced delay time in accordance with the present invention.

<Description of the symbols for the main parts of the drawings>

300: instruction drawing module

310a: first register

310b: second register

320: decoding module

330: arithmetic logic unit

340: light uncle

350: forwarding part

The present invention relates to a vertex processing apparatus, and more particularly, it is necessary to structure a stage in a multi-stage pipeline during one cycle from an instruction fetch to a write back operation when performing a vertex processing instruction. It relates to a vertex processing apparatus and a method for minimizing the number of stages.

OpenGL ES (Open Graphics Library Embedded System) is a cross-platform application program interface (API) for two-dimensional and three-dimensional graphics functions on embedded systems including automobiles, various facilities and portable devices. )to be. It is a subset of the Open Graphics Library (OpenGL), a three-dimensional graphics standard for PC environments, that provides a flexible yet powerful low-level interface between software applications and the graphics engine of hardware or software.

OpenGL ES can be used under embedded systems such as mobile communication devices, personal digital assistants (PDAs), mobile multimedia devices (PMPs) and the like, automotive controls, refrigerator controls, and factory robot controls. It is a software solution that processes 3D graphics operations to provide 3D games and a variety of advanced 3D graphics features.

Graphics hardware that supports OpenGL ES is a hardware implementation of the three-dimensional algorithm provided by OpenGL ES, and is a device for processing three-dimensional graphics operations in real time. Conventional graphics hardware processed three-dimensional data according to a fixed algorithm.

A typical example of an embedded system is a mobile terminal that is a mobile device. Currently, portable terminals equipped with a 3D graphics engine (ie, graphics hardware) are processing graphics operations through the following process.

The shape of the object to be expressed is divided into a polygon set of triangles. Here, three vertices constituting each polygon are called vertices. The graphics hardware receives data from the application interface, including the three vertices' positions, colors, normal vectors, and texture coordinates.

For vertices received through vertex processing, matrix coordinates are used to determine the coordinates on the screen, and the brightness of the points is determined according to an illumination model (eg, phong illumination model).

And through the primitive assembly process, the coordinate transformation and lighting calculation points are collected to form a triangle. The rasterizer process then determines the pixels the triangle occupies on the screen.

Based on the specified state information, the pixel data determined through the rasterizer process is processed through pixel processing (ie, texture operation, color sum, and fog effect) to determine the final color of the pixel data, and the rendered pixel is output. do.

When the vertex processing process is specified, it is divided into a process of converting the coordinates of the vertex from the model coordinate system to the screen coordinate system and the lighting calculation process.

The coordinates of the vertices included in the vertex data are converted from the coordinate system in which the models are defined (generally, the center of the model is the origin) to the world coordinate system, a virtual world coordinate system in which several models coexist. That is, the points on the world coordinate system are acquired through a process of moving, rotating, and scaling the points on the model coordinate system. Then, the points of the world coordinate system are transformed into the view coordinate system, which is the coordinate system centered on the camera calculated through movement and rotation, and the projection transformation is performed to the projection coordinate system, which is the coordinate system corresponding to the result of perspective projection. Projection transformation is the process of making the x and y coordinates smaller as the points on the view coordinate system move away from the origin. And the size is converted according to the size of the screen to be expressed (viewport scale) and the coordinates are transformed into points on the screen coordinate system.

Ambient lighting, a component of light that is indirectly influenced by other objects around it, diffuse lighting, which is a component of light scattered and reflected from the surface of an object, and reflection from the surface of an object. It calculates lighting to determine vertex color by adding specular lighting that is light but has a specific direction (considering eye position).

An instruction for vertex processing as described above consists of an executable code and one or more operands. The set of executable codes is shown in Table 1 below.

There are 20 execution codes for conventional vertex processing, as shown in Table 1 above, and the delay time (Latency) in the calculation process by executing the execution code varies from 1 to 8 when calculated by the number of operation stages. Here, the number of operation stages refers to the number of stages required for operation in the operation logic module during one cycle from instruction fetching to writeback operation.

 In the processing of the vertex data, when the execution codes of Table 1 are executed in various orders, a large time delay occurs, and there is a problem in that performance decreases and efficiency decreases in the vertex processing process.

1 is a diagram illustrating a pipeline flow of a conventional executable code.

For example, assume that execution code is executed in order of vertex processing in order of RSQ, ADD, and DP3. In this case, eight stages are required to compute the first executable code, RSQ. After the operation of the first execution code RSQ is completed, the second execution code ADD is calculated only during the write back process of storing the operation result in each register. In this case, ADD requires only one stage for its own operation, but since the first execution code RSQ has a long delay time, a time delay occurs from 1 to 8 based on the clock CLK shown in FIG. .

That is, a problem occurs due to data dependency between RSQ, which is the current execution code, and ADD, which is the next execution code, and the next execution code cannot be executed or the entire pipeline must be designed in eight stages. There is this. In addition, in calculating the execution code in the order of RSQ, ADD, and DP3, a total of 14 clocks (requires 14 stages) of calculation time are required.

In addition, in processing vertex data, after decoding of the last instruction for vertex processing of the current vertex data is completed, the next vertex data is input by replacing an input register that stores the current vertex data. There is a problem in that a time interval for processing current vertex data and next vertex data increases in proportion to.

Accordingly, the present invention provides an apparatus and method for processing a vertex in a multi-stage pipeline structure that can reduce the maximum delay time between each execution code to three stages through an arithmetic logic module in a multi-stage pipeline structure in which operation units are sequentially connected.

In addition, the present invention is a vertex processing apparatus of a multi-stage pipeline structure capable of reducing the maximum delay time through an operation logic module having a special operation module for calculating a calculation result within one stage for a special execution code having a long delay time; It provides a way.

In addition, the present invention is an apparatus and method for processing a vertex in a multi-stage pipeline structure that efficiently defines the operation of the operation logic module by decoding the execution code using the execution code lookup table, and facilitates the expansion and modification of the execution code later. To provide.

In addition, the present invention provides a vertex processing method of a multi-stage pipeline structure having a constant delay regardless of the number of execution codes in processing each vertex data.

Other objects of the present invention will be readily understood through the following description.

In order to achieve the above object, according to an aspect of the present invention, a first register for storing data for vertex processing; A second register for storing an operation result; An instruction fetch module for sequentially fetching an instruction including an OP code and one or more operands; A decoding module for decoding the instruction and reading data required from the first register according to the operand; An arithmetic logic module (ALU) comprising a plurality of sequential arithmetic units, and sequentially calculating and outputting the data through one or more of the arithmetic units according to the type of the execution code; And a write back unit for storing an operation result of the execution code having the highest priority of the execution code among the operation results in the second register, and temporarily storing other operation results therein to be processed in the next stage. There may be provided a vertex processing apparatus of a multistage pipeline structure.

Preferably, in the vertex processing apparatus of the multi-stage pipeline structure according to the present invention, the arithmetic logic module performs one or more of a basic operation and a multiplication operation, and the basic operation result and the multiplication operation result which is the performance result, and a predetermined value. A first calculator for outputting one or more of a value and input data; A second operation unit configured to output a first addition operation result obtained by adding the output results of the first operation unit; And a third operation unit configured to output a second addition operation result obtained by adding the output results of the second operation unit. Here, the first operation unit, the second operation unit and the third operation unit has a pipeline structure, and each operation unit may perform calculations on different data at the same time.

In addition, the vertex processing apparatus of the multi-stage pipeline structure according to the present invention further comprises a source modifier for performing a swizzle operation of changing the order of input of data input to the arithmetic logic module as necessary. It may include.

The vertex processing apparatus of the multi-stage pipeline structure according to the present invention further includes a source modifier for performing a sign inversion operation for inverting a sign of data input to the arithmetic logic module as needed. It may include.

In addition, the vertex processing apparatus of the multi-stage pipeline structure according to the present invention, the decoding result from the writeback module before the operation result stored in the second register stored in the writeback module required by the decoding module It may further include a forwarding module (forwarding unit) for delivering to.

In the vertex processing apparatus of the multi-stage pipeline structure according to the present invention, the first register includes an input register for storing vertex data, a constant register for storing constant data, and a temporary register for storing the operation result. can do. Here, the decoding module may read one or more of the vertex data, the constant data, and the operation result from any one or more of the input register, the constant register, and the temporary register.

In the vertex processing apparatus of the multi-stage pipeline structure according to the present invention, the second register may include a temporary register for storing the operation result and an output register for storing output data. Here, the writeback module may store the operation result in any one of the temporary register and the output register.

In addition, in the vertex processing apparatus of the multi-stage pipeline structure according to the present invention, the execution code may be prioritized by a first in first out method.

In addition, in the vertex processing apparatus of the multi-stage pipeline structure according to the present invention, the writeback module may store the operation result of the execution code having a lower priority in the destination address when two or more operation results have the same destination address.

Further, in the vertex processing apparatus of the multi-stage pipeline structure according to the present invention, the arithmetic logic module may include a special arithmetic module which allows the arithmetic stage number to be 1 for a predetermined special execution code. Here, the special execution code may be EXP, LOG, EX2, LG2, RCP and RSQ.

The number of operation stages of the execution code may be any one of 1, 2, and 3, and the operation logic module may be divided into three operation units having a pipelined structure. Here, the number of operation stages of POW, DPH, DP3, and DP4 among the execution codes may be three, the number of operation stages of MAD and XPD may be two, and the number of operation stages of other execution codes may be one.

In the vertex processing apparatus of the multi-stage pipeline structure according to the present invention, the decoding module may decode the execution code using an execution code lookup table that determines a decoding method according to the type of the execution code.

In order to achieve the above object, according to another aspect of the invention, (a) receiving the executable code and data; (b) performing a first operation; (c) determining whether the number of operation stages of the executable code is one; (d) finally outputting the result of the execution in step (b) when the number of the operation stages of the execution code is 1, and performing a second operation when the operation stage is not 1; (e) determining whether the number of operation stages of the executable code is two; (f) finally outputting the result of the execution in the step (d) when the number of the operation stages of the execution code is 2, and performing a third operation when the execution stage is not 2; And (g) finally outputting the result of the performance in step (f).

Preferably, the vertex processing method of the multi-stage pipeline structure according to the present invention, after the step (g), (h) determining the priority of the execution code corresponding to the final output result; And (i) storing the execution result of the execution code having the highest priority in a destination register, and bypassing the execution result of the execution code in other destinations, when all of the execution result is stored in the destination register. The steps (h) to (i) can be repeated until.

In order to achieve the above objects, according to another aspect of the invention, (a) storing the vertex data for vertex processing in the input register; (b) sequentially receiving instructions for vertex processing of the vertex data and reading the vertex data from the input register; (c) decoding the instructions in machine language; (d) replacing the input register if the instruction is the last instruction for vertex processing of the vertex data, otherwise performing vertex processing according to the machine language and repeating steps (b) to (c) ; And (e) storing the next vertex data in the input register while performing the vertex processing according to the last instruction, and repeating the steps (b) to (d). Can be provided.

Preferably, in the vertex processing method of the multistage pipeline structure according to the present invention, the step (d) may be delayed by 2 clocks for the replacement of the input register.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the vertex processing apparatus and method of the multi-stage pipeline structure according to the present invention. In describing the present invention, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Numbers (eg, first, second, etc.) used in the description of the present specification are merely identification symbols for sequentially distinguishing identical or similar entities.

In the present invention, a cycle refers to a cycle of sequentially executing instruction fetching, instruction decoding, operation, and writeback operation in executing an instruction for vertex processing. In addition, a stage is a stage of operations required to execute one instruction, and instruction fetch, instruction decode, and writeback operations correspond to one stage, and arithmetic operations are performed in one to three stages in some cases. It becomes. That is, a calculation operation including a plurality of stages is included in one cycle, which is a period in which one instruction is executed. The operation stage number refers to the number of stages required for performing an operation operation in one cycle in which one instruction is executed.

2 is a diagram illustrating execution code classification of instructions according to an exemplary embodiment of the present invention. Although the execution code of Table 1 varies greatly from the delay time, that is, the number of operation stages to 1 to 8, the vertex processing apparatus of the present invention limits the execution code of the instruction for vertex processing to have a maximum number of operation stages of three. .

Execution code for vertex processing in the vertex processing apparatus of the present invention is, as in '210', ABS, ADD, ARL, DP3, DP4, DPH, DST, EX2, EXP, FLR, FRC, LG2, LIT, LOG, MAD, MAX, MIN, MOV, MUL, POW, RCP, RSQ, SGE, SLT, SUB, SWZ, XPD.

The basic syntax of the command is shown in Equation 1 below.

opcode destination operand, source operand0, (source operand1, source operand2)

An instruction consists of an opcode, a destination operand (hereinafter referred to as dest), and a source operand (hereinafter referred to as src).

The target and / or source operator writes directly the name of the variable or register bound with each register, and the present invention uses the index address of each register for reference of the operand. Target operand refers to the destination register for storing the operation result, and source operation refers to the input register, constant register, temporary register, address that stores data such as vertex data, constant data, intermediate operation result, and address value for operation. Points to registers, etc.

Each instruction basically has a target operand, and depending on the operation contents, there are one or three source operands. A four component vector has a vector format of [x, y, z, w] in which each data consists of four real sets. The s scalar is a value having only x components, and the ssss scalar has four components of x, y, z, and w, all of which are the same.

24 basic execution codes of the respective execution codes are shown in Table 2 below. Where a is an address register, v is a four-component vector, s is a scalar, ssss is a four-component scalar, normal is the basic executable code, and macro is the macro executable code.

(1) Absolute value (ABS) substitutes the absolute value of each component of x, y, z, w of src0 corresponding to four component vectors into x, y, z, w of dest, respectively. (2) ADD (Add two vectors) adds the values of x, y, z and w components of src0 and src1 corresponding to four component vectors and assigns them to x, y, z and w of dest, respectively. (3) ARL (Address register load) assigns the largest integer less than or equal to the value stored in src0 corresponding to the s scalar to a0 (the address register). According to the above description, the value assigned to a0 is the base address. (3) The 3-component dot product (DP3) calculates the dot product of three components of x, y, and z among src0 and src1 corresponding to the four component vector, and then calculates the dot product of the ssss scalar dest. Substitute in ingredients. (4) The 4-component dot product (DP4) calculates the inner product of four components of x, y, z, and w of src0 and src1 corresponding to the four component vectors, and then places the inner product on the four components of the ssss scalar dest. Assign. (6) Homogeneous dot product (DPH) finds the dot product of three components of x, y, and z among src0 and src1 corresponding to the four component vector, and then substitutes the dot product into x, y, z of the four component vector dest. Then, the value of the w component of src1 is substituted into the w component of dest. This is equivalent to setting the w component of src0 to 1.0 and applying the DP4 operation on src0 and src1. (7) A distance vector (DST) calculates a distance vector from an operand having two special formats. Four-component vectors src0 and src1, where src0 is [NA, d ² , d ² , NA], src1 is [NA, 1 / d, NA, 1 / d], NA is not computational and d is a vector X component of dest, the four-component vector, 1.0, y is the product of src0 and y components of src1, z is the z component of scr0, and w is the w component of src1. Let dest be of the form [1.0, d, d ² , 1 / d]. (8) EX2 (exponential base 2) assigns 2 ^src0 to 4 components of ssss scalar dest, with 2 as base and s scalar src0 as exponent. (9) EXP (exponential base 2 (approximate)) assigns the partially correct value of 2 ^src0 to the four-component vector dest with 2 as the base and s scalar src0 as the exponent. The x component of dest is substituted for the integer part of src0 (the largest integer less than src0), and the y component is substituted for the fractional part of src0 (src0 minus the largest integer less than or equal to src0). The z component is substituted with the form taking the approximate 2 exponent of src0, and 1.0 is substituted for the w component. (10) FLR (floor) substitutes the integer part (largest integer less than or equal to src0) of each component of src0 corresponding to the four component vector to each component of dest corresponding to the four component vector. (11) FRC (fraction) substitutes the fractional part (src0 minus the largest integer less than or equal to src0) of each component of src0 corresponding to the four component vector to each component of dest corresponding to the four component vector. (12) LG2 (logarithm base 2) substitutes the log value of base 2 for src0 corresponding to the s scalar to each component of the ssss scalar dest. (13) LOG (logarithm base 2 (approximate)) assigns the approximate value of the logarithm of base 2 to src0, the s scalar, to dest, a four-component vector. The x component of dest is substituted for the integer part of the logarithm base whose base is 2 with respect to src0, and the y component is substituted with the right-shifted value of src0 by the x component of dest. do. (14) Multiply and add (MAD) use all three source operations uniquely among the instructions in the present invention. The value obtained by adding each component of src2 to the product of four components vector src0 and src1 is substituted into each component of dest which is a four component vector. (15) MAX (Maximum) substitutes a larger value of each component of src0 and src1, which are four component vectors, into each component of dest, which is a four component vector. (16) MIN (Minimum) substitutes the smaller value of each component of src0 and src1 as four component vectors into each component of dest as a four component vector. (17) MOV (Move) substitutes the value of each component of src0 as a four component vector into each component of dest as a four component vector. (18) MUL (Multiply) substitutes the product of src0, which is a four component vector, and src1, into each component of dest, which is a four component vector. (19) RCP (Reciprocal) assigns the inverse of the value of the s scalar src0 to each component of the ssss scalar dest. (20) Reciprocal square root (RSQ) assigns the inverse of the square root of the s scalar src0 to each component of the ssss scalar dest. (21) SGE (set on Greater than or equal) compares each component of the four-component vector src0 and src1, and assigns 1.0 to src0 and 0.0 to less than src1 to each component of dest, the four-component vector. do. (22) Set on less than (SLT) compares each component of the four component vector src0 and src1 and substitutes 1.0 for src0 less than src1 and 0.0 for each component of dest, which is a four component vector. (23) SWZ (extended swizzle) is loaded with each component of src0, a four-component vector, 1.0 and 0.0, and whether there is a sign inversion for each component of dest, a four-component vector, and six values (each of src0). Component, 1.0, 0.0), and the value of any combination is substituted. (24) XPD (cross product) obtains the cross product of three components of x, y, z of four component vectors src0 and src1, and converts the cross product to the x, y, z components of dest of four component vectors. Assign. The w component is not defined.

The three macro executables are as follows:

(1) LIT (compute light coefficients) is an operation for accelerating lighting effects due to ambient light, scattered light, and reflected light for each vertex. The LIT operation is composed of a set of basic executable codes as shown in Equation 2 below.

LIT f, a, b

   Clamp tmp, a.0, b

   rLG2 tmp.w tmp.w

   MUL tmp.w tmp.w tmp.y

   rEX2 tmp.w tmp.w

   mulz f, tmp1.1xz1, tmp.w

(2) POW (exponentiate) obtains src0 ^src1 for s scalar src0 and src1 and assigns it to ssss scalar dest. The POW operation consists of a set of basic executable codes as shown in Equation 3 below.

POW f, a, b (f = a ^b )

   LG2 tmp, a

   MUL tmp, tmp, b

   EX2 f, tmp

(3) SUB (subtract) substitutes each component of dest as a four-component vector by subtracting the value of each component of src1 from each component of src0 as a four-component vector. The SUB operation consists of a set of basic executable codes such as Equation 4 below.

SUB f, a, b (f = a-b)

   ADD f, a, -b

The three macro execution codes can be reconstructed into 24 basic execution codes, and the vertex processing apparatus interprets the macro execution code as a set of basic execution codes as expressed in Equations 2 to 4 during the vertex processing. Therefore, the execution code actually used in the vertex processing apparatus in the present invention is 24 basic execution codes, and can be extended to other execution codes.

The above-described execution codes are basically classified into general execution code 220 having an operation stage number of 3 or less, and special execution code 225 having an operation stage number of 3 or more. The number of operation cycles is the number of clocks that represent the delay time during which the execution code performs a predetermined operation on the data indicated by the source operator and stores the result in the register indicated by the target operand.

The general execution code 220 is classified into a first group (operation stage number = 1), a second group (operation stage number = 2), and a third group (operation stage number = 3) according to the operation stage number. ADD, MUL, DST, MOV, MAX, MIN, SGE, SLT, ABS, ARL, FLR, FRC in the first group 230, 232, 238, MAD, XPD in the second group 236, Group 234 includes DP3, DP4, DPH.

The special execution code 242 includes EXP, LOG, EX2, LG2, RCP, and RSQ in which the number of operation stages is converted to 1 by a special operation module (to be described later with reference to FIG. 3).

The macro execution code 240 is composed of a LIT and a POW, and is interpreted as a set of a plurality of general execution codes 220 or special execution codes 242 by Equation 2 and Equation 3 described above.

Hereinafter, a vertex processing apparatus having a multi-stage pipeline structure in performing vertex processing using the execution codes having the maximum number of operation stages as described above will be described.

3 is a block diagram illustrating a vertex processing apparatus according to an exemplary embodiment of the present invention, and FIG. 4 is a diagram illustrating an example of a pipeline flow in the vertex processing apparatus illustrated in FIG. 3.

The vertex processing apparatus includes an instruction retrieval module 300, registers 310a and 310b, a decoding module 320, an arithmetic logic module 330, and a writeback module 340. If necessary, the forwarding module 350 and / or the source modification module 360 may be further included.

The instruction fetch module 300 sequentially fetches instructions including executable code and operations for vertex processing. Each execution code is prioritized in the writeback module 340, which will be described later, according to a drawing order in the instruction drawing module 300.

The register includes a first register 310a that stores data for vertex processing (for example, vertex data, constant data, intermediate calculation results, address data, and the like), and an operation result output from the calculation logic module 330 ( For example, a second register 310b for storing vertex processing output data, intermediate calculation result, address data, etc.) is included.

The first register 310a includes an input register 311 storing vertex data, a temporary register 312 storing intermediate calculation results, and a constant register 313 (or constant data storing constant data required for vertex processing). Address register 314 which stores the address where constant data is stored for reference.

The second register 310b includes an output register 316 for storing output data of which vertex processing is completed among the results calculated by the calculation logic module 330, a temporary register 312 for storing intermediate calculation results, and address data. Address register 314 to be included.

Here, the temporary register 312 and the address register 314 are registers common to the first register 310a and the second register 310b.

Vertex data is stream data of the vertices of the polygons constituting the object to be displayed on the screen. If you want to express an object on the screen three-dimensionally, the shape of the object to be expressed is divided into triangular polygon sets, and three vertex data constituting the polygon is processed through a vertex processing process to create a three-dimensional image. .

Vertex data includes attribute data such as position, color, normal vector, texture coordinate, and the like for each vertex. Each attribute data consists of four real sets. For example, the coordinate attribute data has four real numbers of x, y, z values representing three dimensions and w values representing the degree of projection, and the color attribute data is r (red) which is the brightness value of the basic three primary colors. It has four real numbers: the g (green), the b (blue) value, and the alpha (a) value representing the opacity.

Vertex data supports at least 16 attribute data in the OpenGL ARB extension 1.0 structure. 8 coordinates including coordinates, primary colors, secondary colors, normal vectors, vertex weights, fog coordinates, and up to 8 texture coordinates including first texture coordinates, second texture coordinates, and third texture coordinates. Can support attribute data.

The value of the vertex data is stored in an input register 311 or an address to which the vertex data can be referenced is stored in the input register 311. The decoding module 320 may read the value stored in the input register 311 or receive the vertex data with reference to the stored address. The vertex register 311 may read only and cannot change or write.

The constant register 313 stores constant data or an address to which the constant data can be referenced. Constant data are values used in performing vertex processing. For example, constant data is a value for matrix calculation, a specific color value, a value for lighting calculation, etc. Each constant data is composed of four sets of real numbers. At least 96 constants are supported in the OpenGL ARB extension 1.0 architecture. The constant register 313 can only read, not change or write.

Temporary register 312 stores temporary variables used during vertex processing, that is, intermediate computation results. Since the vertex data or the constant data used for the vertex processing are all four real sets, the temporary register 312 also basically consists of four real sets.

The temporary register 312 supports at least 12 in the OpenGL ARB 1.0 structure. In the present invention, since the macro execution code 240 is present among the execution codes 225, four additional temporary storage spaces are required. It supports 16 in total. While the vertex processing is being performed, the vertex processing device may write or read arbitrary data to the temporary register 312.

The address register 314 stores a base address that is a reference base when reading constant data using the constant register 313. The reference is set based on the base address, and it is read by referring to the relative position where the constant data is stored using the offset to the address where the constant data needed in the vertex processing is stored.

The output register 316 stores output data which is the final arithmetic result of vertex processing. The output data, i.e., the output variables, will then follow the graphics pipeline, such as primitive assemblies, rasterizers, pixel processing, etc., as described above. In the OpenGL ARB extension 1.0 structure, at least 13 output registers 316 are supported, and each output register 316 is configured to store four real sets. The output register 316 can only be written to.

In the present invention, the decoded executable code, vertex data, and constant data may be directly referred to through a pointer to each data stored in the memory, without using a separate storage device as described above. This is to alleviate time delay incurred in allocating separate storage spaces for copying each data. The decoded execution code, vertex data, and constant data can be read by the arithmetic logic module 330 to be described later. This is because it is used only.

The temporary register 312, the address register 314, and the output register 316 are devices in which data write operations are stored in each register during vertex processing. In the step of initializing the configuration of the vertex processing device, memory is allocated and used as much as the size of each register.

The decoding module 320 decodes the input command into machine language. The instruction has the same grammar structure as in Equation 1 above, and reads a value stored in a register indicated by the source operator. That is, the data stored in the register (input register 311, temporary register 312, constant register 313, address register 314 or more) required according to the instruction of the first register (310a) data Decoding modules 322, 324, 326 are read.

In this case, when data is read from each register, it is necessary to perform a swizzle and / or sign inversion operation to input the converted data to the arithmetic logic module 330 to be described later. Occurs. In this case, the vertex processing apparatus may further include a source modification module 360, and the source modification module 360 performs a swizzle operation or a sign inversion operation.

The swizzle operation means changing the value of each component when each data is four-component data having four components of x, y, z and w, for example. That is, it is possible to transform data by performing an operation such as changing the value of the x component to the y component and the value of the y component to the z component. The sign inversion operation inverts the sign of the values of each component of the data. In other words, if it has a positive value, the data is converted to have a negative value. The swizzle operation and / or sign inversion operation are utilized when necessary for effective vertex processing.

The executable code is transmitted to the executable code decoding module 328 by the executable code lookup table 315 with a corresponding value. Execution code lookup table 315 is a lookup table that is used to efficiently define the operation of the operation logic module 330 to be described later in decoding the executable code among the instructions and to facilitate the expansion or modification of the execution code in the future ( LookUp Table). Since the number of source operations required varies depending on the type of executable code, each group of executable code is grouped according to the number of source operations required and the type of destination address, and required for the same group of executable codes. Decoding efficiency can be improved by decoding only the field of the source operation region. That is, the execution code lookup table 315 determines the type of the execution code, and the execution code decoding module 328 decodes only the field of the predetermined region according to the group to which the execution code belongs.

The arithmetic logic module 330 receives executable code, data, etc., which are decoded by the decoding module 320, that is, machine language. The arithmetic logic module 330 is divided into three arithmetic units, and each arithmetic unit performs arithmetic operations sequentially for each stage and outputs arithmetic results.

The first operation unit outputs a basic operation result of performing a basic operation (addition, multiplication, comparison, fraction, floor, etc.) on the input data. In addition, the result of the multiplication operation is performed by performing a multiplication operation for calculating the cross product. The basic operation result and the multiplication operation result, the predetermined value (0 or 1) and the input constant data may be output values of each component. In each component, a multiplexer (MUX) is used to select the final output value of the first operation unit according to the execution code.

The second operation unit adds the basic operation results of the first operation unit and the output values output from the first operation unit for dot product operations DPH, DP3, and DP4 and cross product operations.

The third operation unit adds the x component output value and the z component output value in the second operation unit for the internal product operation.

Outputs from the first computing unit, the second computing unit, and the third computing unit are written back to the writeback module 340 through the first stage 332, the second stage 334, and the third stage 336, respectively, or the next calculator. Is passed to.

Each stage 332, 334, 336 outputs the operation result at the time when the operation of each execution code is completed. After the decoded execution code is transmitted to the operation logic module 330, the first stage 332 outputs the operation result of the execution code having the operation stage number 1, and the second stage 334 the execution code having the operation stage number 2 The third stage 336 outputs an operation result of the execution code of which the operation stage number is three. That is, the first stage 332 is a special execution code that is calculated by ADD, MUL, DST, MOV, MAX, MIN, SGE, SLT, ABS, ARL, FLR, FRC, and a special operation module to be described later. EX2, LG2, RCP, and RSQ include MAD and XPD in the second stage 334, and DP3, DP4, and DPH in the third stage 336. Each stage performs a computational process individually. Referring to FIG. 4, an example of fetching execution code in the order of DP3, MAD, and ADD will be given. It is assumed that the stage for the operation starts from the clock CLK 0 as shown in FIG. 4. When the clock is 0, the first DP3 transmitted to the arithmetic logic module 330 outputs an arithmetic result at clock 3, which is three stages later, corresponding to the execution code of the third stage 336. When the clock is 1, the MAD, which is the second-order execution code transmitted to the arithmetic logic module 330, corresponds to the execution code of the second stage 334, and the arithmetic result is output at clock 3, which is two stages later. When the clock is 2, the operation result is output at the clock 3, which is one stage later, corresponding to the execution code of the first stage 332, which is the third-order execution code transmitted to the operation logic module 330. Since each stage performs arithmetic processing individually, there exists a case where the arithmetic result of the execution code inputted sequentially is output simultaneously at the clock 3 time | point as mentioned above. In this case, the processing of each calculation result is performed by the writeback module 340 which will be described later.

Arithmetic logic module 330 includes a special computation module. The special arithmetic module designates the execution code that had a conventional delay time, that is, the number of operation cycles of 4 or more, as the special execution code in arithmetic operation of the execution code, and calculates each operation separately for the special execution code. To be Special execution code that performs separate operation in special operation module is EXP, LOG, EX2, LG2, RCP, RSQ.

The write back module 340 stores the operation result of the execution code output from each stage 332, 334, or 336 of the operation logic module 330 in the second register 310b. Storing the operation result stores the operation result of the execution code having the highest priority input to the operation logic module 330 according to the first in first out (FIFO) method in the corresponding destination register. The operation result is stored in the output register 316, the temporary register 312, the address register 314 and the like as described above according to the type.

However, as shown in FIG. 4, the operation logic module 330 may output two or more calculation results at the same time as each stage individually performs a calculation process by a multi-stage pipeline structure. In this case, the writeback module 340 stores the operation result of the execution code (DP3 in FIG. 4) having the priority of 1 in the corresponding destination register, and the execution code (MAD, ADD in FIG. 4) of the next priority. The operation result of is temporarily stored and bypassed internally for processing at the next stage. The priority of the calculation result (MAD, ADD in FIG. 4), which is bypassed at the next stage, that is, clock 4, is changed to the highest priority, and the priority of the calculation result output from the calculation logic module 330 is next. Becomes

In addition, the writeback module 340 outputs an operation result according to two or more execution codes from the operation logic module 330, and simultaneously stores the result of the operation at the same address of the second register 310b when the destination address is the same. In this case, the priority of each execution code is compared and the operation result of the execution code of the lower priority (or lower) is stored at the corresponding destination address. When the operation results of the higher priority (or higher) executable code are stored first, the operation results of the lower priority (or lower) executable code are overwritten in the same storage area. Therefore, the operation result of the high-priority (or high) executable code is meaningless and there is only one stage of delay in the entire vertex processing.

According to another preferred embodiment of the present invention, the vertex processing apparatus further includes a forwarding module 350.

The forwarding module 350 includes a writeback module before the data needed by the decoding module 320 to decode the executable code and the operand (for example, an intermediate operation result) is still stored in the register. If the data is stored at 340, the data is transferred directly from the writeback module 340 to the decoding module 320 so that no disturbance due to data dependency occurs.

In the present invention, the writeback module 340 and / or the forwarding module 350 may be configured as a multiplexer, so that the first stage 332, the second stage 334, and the third stage 336 of the arithmetic logic module 330 are included. It is possible to receive the output from and store the output of the selected stage in the designated second register 310b in accordance with the control signal.

FIG. 5 is another example of the multi-stage pipeline flow in the vertex processing apparatus shown in FIG. 3. In the case where the execution code is to be executed in the order of RSQ, ADD, and DP3 in the same manner as described above with reference to FIG. 1, the operation is completed at the time of clock 1 as the number of operation stages is 1 by the special operation module. In addition, unlike ADD having a time delay up to clock 8 in FIG. 1, the operation is started at clock 1. The DP3 starts operation at clock 2 when the operation of ADD is completed, and the operation is completed at clock 5 at the end of 3 clock cycles.

That is, when performing the calculation in the order of vertex processing RSQ, ADD, DP3 in order in the prior art as shown in Figure 1 compared to the operation is completed at the time of the clock 14 as shown in Figure 5 according to a preferred embodiment of the present invention As shown in FIG. 5, the operation is completed at clock 5, and the delay time is significantly reduced, and the amount of time delay is greatly reduced, thereby improving the performance of the vertex processing apparatus.

6 is a flowchart of an arithmetic operation method in an arithmetic logic module according to an exemplary embodiment of the present invention, and FIG. 7 is a flowchart of a method of processing an arithmetic result in a writeback module according to an exemplary embodiment of the present invention.

Referring to FIG. 6, in operation S600, the operation logic module 330 receives data decoded from the decoding module 320 and data read from the first register 310a.

In operation S610, the first operation unit of the operation logic module 330 performs a basic operation and a multiplication operation on the execution code. The result of the basic operation and the multiplication, the predetermined value (0 or 1), and the constant data are output.

In step S620, it is determined whether the number of operation stages of the execution code is one. If the number of calculation stages is 1, the flow advances to step S660 to finally output a value selected from the output results of the first calculation unit.

If the number of operation stages is not 1, the process proceeds to step S630 in which the second operation unit of the operation logic module 330 performs an addition operation on the basic operation result and the output result of the first operation unit for the internal operation or the external operation.

In step S640, it is determined whether the number of computation stages of the execution code is two. If the number of calculation stages is two, the flow advances to step S660 to finally output a value selected from the output results of the second calculation unit.

If the number of the operation stages is not 2, the process proceeds to step S650 where the third operation unit of the operation logic module 330 adds the value of the x component and the value of the z component among the output results of the second operation unit for the internal calculation.

In operation S660, the output from the third calculator is finally output as an operation result.

Referring to FIG. 7, in operation S700, the writeback module 340 receives an operation result from each stage 332, 334, or 336 of the operation logic module 330. The operation result may be output in only one stage or may be output simultaneously in two or more stages.

In operation S710, it is determined whether the priority of the machine language or the instruction corresponding to the operation result input is the highest priority. The operation result of the machine word or the instruction having the highest priority is stored in the destination register, that is, the second register 310b, in step S720. The operation result of the machine word or the instruction having the priority that does not correspond to the highest priority is bypassed while one stage elapses (step S730). Since the operation result of the highest priority is stored in the destination register in step S720, the priority of the operation result that was not the highest priority is increased (step S740), and the process returns to step S710 and the subsequent steps are repeated.

8 is a flowchart illustrating a vertex processing method of reducing a delay time according to a replacement of a register according to another exemplary embodiment of the present invention, FIG. 9 is a diagram illustrating a delay time according to a replacement of a conventional register, and FIG. According to the present invention.

In operation S800, the vertex processing apparatus stores vertex data for vertex processing in an input register. There is more than one vertex data, and vertex processing is performed on each vertex data. Therefore, when the vertex processing is completed for each vertex data, the input register replaces and stores the next vertex data.

In operation S810, the vertex processing apparatus receives one or more instructions for vertex processing of vertex data, vertex data from an input register, and data used for arithmetic operations for vertex processing from the first register 310a. Constant data, address data, intermediate calculation results).

The command received in step S820 is decoded in machine language.

In operation S830, it is determined whether the instruction is the last instruction among one or more instructions for vertex processing of the corresponding vertex data. If it is not the last instruction, the process proceeds to step S840 to perform vertex processing through an arithmetic operation corresponding to the instruction, and returns to step S810 to receive an instruction of a next rank for processing the next vertex of the vertex data.

If it is the last instruction as a result of the determination in step S830, the input register is replaced after the translation into the machine language (step S850). After decoding the last instruction, the value stored in the input register is no longer needed. A delay of two clocks is inevitable when replacing the input registers.

In operation S860, the vertex processing apparatus performs the vertex processing according to the last instruction and simultaneously stores the next vertex data by replacing the input register. Returning to step S810, the operation of the above-described steps is repeated for the next vertex data.

Conventionally, in outputting data in which the first vertex data is vertexed, an input (T1) of an instruction, a decode (T2) in machine language, a source modification (T3) as necessary, and an operation are performed in a logic module. There are output data delays (T1 to T6) 910 according to arithmetic operations (ALU_0 (T4), ALU_1 (T5), and ALU_2 (T6)) of the execution code according to the number of cycles. The first vertex processing time (T1-T8) of 920 was taken. After the first vertex processing was completed (T8), the vertex processing for the second vertex data was possible after a delay of a replacement time (T8 to T9) for replacing the registers. As a result, the vertex processing time of the first vertex data increases in proportion to the number of instructions for vertex processing of the first vertex data, and there is a problem in that the input point T9 of the instruction for vertex processing of the second vertex data is delayed.

However, referring to FIG. 10, in the present invention according to the method illustrated in FIG. 8, the replacement of the input register starts immediately from T17, at which time the input of the instruction is completed, and the second vertex data at T19 after a delay of two clocks. To input the vertex processing of the second vertex data. Accordingly, as the vertex processing of the first vertex data is performed in the arithmetic logic module, the decoding module 320 decodes an instruction regarding the second vertex data. Therefore, regardless of the number of instructions for vertex processing of vertex data, the delay time between the first vertex data and the second vertex data can be reduced by two clocks. Of course, the same content is applicable to each vertex data that must be processed sequentially.

As described above, the vertex processing apparatus and method of the multi-stage pipeline structure according to the present invention can reduce the maximum delay time between each execution code to three stages through the arithmetic logic module of the multi-stage pipeline structure in which the operation units are sequentially connected. Do.

In addition, it is possible to reduce the maximum delay time through an arithmetic logic module having a special arithmetic module for calculating a calculation result within one stage for a special execution code having a long delay time.

In addition, by using the executable code lookup table to decode the executable code, there is an advantage of efficiently defining the operation of the arithmetic logic module and facilitating extension and modification of the executable code later.

In addition, the processing of each vertex data has the advantage of having a constant delay regardless of the number of execution code.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (21)

A first register for storing data for vertex processing; A second register for storing an operation result; An instruction fetch module for sequentially fetching an instruction including an OP code and one or more operands; A decoding module for decoding the instruction and reading data required from the first register according to the operand; An arithmetic logic module (ALU) comprising a plurality of sequential arithmetic units, and sequentially calculating and outputting the data through one or more of the arithmetic units according to the type of the execution code; And A write back unit for storing an operation result of the execution code having the priority of the execution code among the operation results in the second register, and temporarily storing the operation result therein to be processed in the next stage Vertex processing device of a multi-stage pipeline structure comprising a. The logic module of claim 1, wherein the arithmetic logic module comprises: A first operation unit configured to perform at least one of a basic operation and a multiplication operation, and output at least one of a basic operation result and a multiplication operation result, a predetermined value, and input data; A second operation unit configured to output a first addition operation result obtained by adding the output results of the first operation unit; And And a third operation unit configured to output a second addition operation result obtained by adding the output results of the second operation unit. The method of claim 2, And the first operation unit, the second operation unit, and the third operation unit have a pipelined structure, and each operation unit can simultaneously perform operations on different data. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, And a source modifier for performing a swizzle operation for changing the input order of the data input to the arithmetic logic module as necessary. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, The method of claim 1, The multi-stage pipeline further includes a forwarding unit for transferring the calculation result from the writeback module to the decoding module before the operation result stored in the second register stored in the writeback module required by the decoding module. Vertex processing unit of the structure. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the first register, An input register for storing vertex data, A constant register for storing constant data, And a temporary register for storing the operation result. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the second register, A temporary register for storing the operation result; And an output register for storing output data. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9, And the writeback module stores the operation result in one of the temporary register and the output register. The method of claim 1, The execution code is a vertex processing apparatus of a multi-stage pipeline structure, characterized in that the priority is determined by the First In First Out (First In First Out) method. The method of claim 1, The writeback module vertex processing apparatus of the multi-stage pipeline structure, when the destination address of the two or more calculation results are the same, the operation result of the execution code of the lower priority is stored in the destination address. The method of claim 1, And the arithmetic logic module includes a special arithmetic module for causing the number of arithmetic stages to be 1 for a predetermined special execution code. Claim 14 was abandoned when the registration fee was paid. The method of claim 13, The special execution code is a vertex processing apparatus of a multi-stage pipeline structure, characterized in that the EXP, LOG, EX2, LG2, RCP and RSQ. The method of claim 13, The number of arithmetic stages of the execution code is any one of 1, 2, and 3, and the arithmetic logic module is divided into three arithmetic unit having a pipeline structure, characterized in that the multi-stage pipeline structure vertex processing apparatus. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 15, And wherein the number of operation stages of POW, DPH, DP3, and DP4 is 3, the number of operation stages of MAD and XPD is 2, and the number of operation stages of other execution codes is 1 in the execution code. The method of claim 1, And the decoding module decodes the execution code using an execution code lookup table that determines a decoding method differently according to the type of the execution code. (a) receiving execution code and data; (b) performing a first operation; (c) determining whether the number of operation stages of the executable code is one; (d) finally outputting the result of the execution in step (b) when the number of the operation stages of the execution code is 1, and performing a second operation when the operation stage is not 1; (e) determining whether the number of operation stages of the executable code is two; (f) finally outputting the result of the execution in the step (d) when the number of the operation stages of the execution code is 2, and performing a third operation when the execution stage is not 2; And (g) finally outputting the result of performing in step (f) Vertex processing method of a multistage pipeline structure comprising a. The method of claim 18, wherein after step (g), (h) determining a priority of execution code corresponding to the final output result; And (i) storing the result of execution of the execution code having the highest priority in a destination register, and bypassing the execution result of the execution code other than that; And repeating steps (h) to (i) until all of the results are stored in the destination register. (a) storing vertex data for vertex processing in an input register; (b) sequentially receiving instructions for vertex processing of the vertex data and reading the vertex data from the input register; (c) decoding the instructions in machine language; (d) replacing the input register if the instruction is the last instruction for vertex processing of the vertex data, otherwise performing vertex processing according to the machine language and repeating steps (b) to (c) ; And (e) storing the next vertex data in the input register while performing the vertex processing according to the last instruction, and repeating steps (b) to (d). The method of claim 20, And step (d) is delayed by two clocks for replacement of the input register.

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