KR100788223B1 - Differential output circuit with stable duty - Google Patents

Differential output circuit with stable duty Download PDF

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Publication number
KR100788223B1
KR100788223B1 KR1020060079374A KR20060079374A KR100788223B1 KR 100788223 B1 KR100788223 B1 KR 100788223B1 KR 1020060079374 A KR1020060079374 A KR 1020060079374A KR 20060079374 A KR20060079374 A KR 20060079374A KR 100788223 B1 KR100788223 B1 KR 100788223B1
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South Korea
Prior art keywords
mos transistor
channel mos
voltage
gate
circuit
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KR1020060079374A
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Korean (ko)
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KR20070023552A (en
Inventor
야스시 아오키
마사토모 에이미츠
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엔이씨 일렉트로닉스 가부시키가이샤
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Priority to KR1020060079374A priority patent/KR100788223B1/en
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • H03K3/356113Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00369Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528Interface arrangements of complementary type, e.g. CMOS with at least one differential stage

Abstract

The differential output circuit includes a bias circuit coupled with the first voltage. The input circuit portion includes first and second MOS transistors of a first conductivity type, the first and second MOS transistors being connected to the first voltage through a bias circuit, and the gates of the first and second MOS transistors being differential inputs. Receive the signal. The third and fourth MOS transistors of the second conductivity type are connected with the first and second MOS transistors through the first and second resistive elements, respectively, and with the second voltage. The first connection node between the first MOS transistor and the first resistive element is connected with the gate of the fourth MOS transistor, and the second connection node between the second MOS transistor and the second resistive element is connected with the gate of the third MOS transistor. do. The differential output signal is output from the first output node between the first resistor element and the third MOS transistor and the second output node between the second resistor element and the fourth MOS transistor in response to the differential input signal.
Differential output circuit, differential input signal, differential output signal

Description

DIFFERENTIAL OUTPUT CIRCUIT WITH STABLE DUTY}

1 is a circuit diagram showing the configuration of a conventional differential output circuit.

2 is a circuit diagram showing a configuration of a differential output circuit according to an embodiment of the present invention.

3 shows frequency characteristics in a conventional differential output circuit and a differential output circuit of a first embodiment.

4A to 4C are diagrams showing input / output waveforms of the conventional differential output circuit and the differential output circuit of the first embodiment.

5 is a circuit diagram showing a configuration of a differential output circuit according to a second embodiment of the present invention.

6 is a circuit diagram showing a configuration of a differential output circuit according to a third embodiment of the present invention.

7 is a circuit diagram showing a configuration of a differential output circuit according to a fourth embodiment of the present invention.

8 is a circuit diagram showing a configuration of a differential output circuit according to a fifth embodiment of the present invention.

9 is a circuit diagram showing a configuration of a differential output circuit according to a sixth embodiment of the present invention.

10A-10C illustrate an embodiment in which a capacitance element consists of one or more MOS transistors.

Explanation of symbols on the main parts of the drawings

N11a, N11b, N12a, N12b, N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N7, N8, N9: N-channel MOS transistors

P11a, P11b, P1a, P1b, P7: P-channel MOS transistors

R1a, R2a, R1b, R2b: resistor R1: feedback resistor

VDD: High Voltage Power VSS: Low Voltage Power

C1a, C1b, C2: capacitance elements 1a, 1b, 2a, 2b: connection nodes

INa, INb, IN2a, IN2b: input terminal OUTa, OUTb: output terminal

The present invention relates to a differential output circuit for outputting a differential signal in response to a differential input signal.

In connection with the high speed operation of semiconductor integrated circuits, differential signals are often used as an interface between circuits. Differential signals prevail over noise resistance and are difficult to accommodate the effects of changes in the fabrication of circuits. A differential output circuit for generating a differential signal is disclosed in Japanese Patent Application Laid-Open (JP P2004-128747A). 1 is a circuit diagram of a differential output circuit. As shown in FIG. 1, the differential output circuit is provided with N-channel MOS transistors N11a, N11b, N12a and N12b, P-channel MOS transistors P11a and P11b and a resistor element R. As shown in FIG.

The MOS transistors P11a, N12a and N11a are connected in series between the high voltage power supply VDD and the low voltage power supply VSS. That is, the source of the N-channel MOS transistor N11a is connected to the low voltage power supply VSS, and the drain of the N-channel MOS transistor N11a is connected to the source of the N-channel MOS transistor N12a. Connected. The source of the P-channel MOS transistor P11a is connected to the high voltage power supply VDD, and the drain of the P-channel MOS transistor P11a is connected to the drain of the N-channel MOS transistor N12a. Similarly, the MOS transistors P11b, N12b and N11b are connected in series between the high voltage power supply VDD and the low voltage power supply VSS. That is, the source of the N-channel MOS transistor N11b is connected to the low voltage power supply VSS, and the drain of the N-channel MOS transistor N11b is connected to the source of the N-channel MOS transistor N12b. The source of the P-channel MOS transistor P11b is connected to the high voltage power supply VDD, and the drain of the P-channel MOS transistor P11b is connected to the drain of the N-channel MOS transistor N12b.

The gate of the N-channel MOS transistor N12a and the gate of the N-channel MOS transistor N12b are connected to the high voltage power supply VDD. Therefore, the N-channel MOS transistor N12a and the N-channel MOS transistor N12b are always turned on and function as a resistive element. The input terminal INa is connected to the gate of the N-channel MOS transistor N11a, and the input terminal INb is connected to the gate of the N-channel MOS transistor N11b. The input signal applied from the input terminal INa and the input signal applied from the input terminal INb function as differential signals and have opposite phases with respect to each other.

The node a between the N-channel MOS transistor N12a and the N-channel MOS transistor N11a is connected to the gate of the P-channel MOS transistor P11b. The node b between the N-channel MOS transistor N12b and the N-channel MOS transistor N11b is connected to the gate of the P-channel MOS transistor P11a. The node between the N-channel MOS transistor N12a and the P-channel MOS transistor P11a is connected to the output terminal OUTb, and the node between the N-channel MOS transistor N12b and the P-channel MOS transistor P11b. Is connected to the output terminal OUTa. The resistor element R is connected between the output terminal OUTa and the output terminal OUTb.

The operation of the differential output circuit is described below. The circuit shown in FIG. 1 can be considered to be a composite of two circuit sections for two signal routes. The first signal route is a signal route for receiving a signal from the input terminal INa and outputting the signal from the output terminal OUTa. The second signal route is a signal route for receiving a signal from the input terminal INb and outputting a signal from the output terminal OUTb.

In the first signal route, the N-channel MOS transistor N11a comprises a source grounded amplifying circuit having, as a load resistor, an N-channel MOS transistor N12a and a P-channel MOS transistor P11a. Configure. The output is obtained from the connection node (a) between the load resistor and the N-channel MOS transistor N11a. The signal at node (a) is applied to the gate of P-channel MOS transistor P11b. The P-channel MOS transistor P11b constitutes a source ground amplifier circuit having an N-channel MOS transistor N11b and an N-channel MOS transistor N12b as load resistance. Therefore, the signal applied from the input terminal INa is amplified by a two-stage amplifying circuit composed of the N-channel MOS transistor N11a and the P-channel MOS transistor P11b and output from the output terminal OUTa. The output signal output to the output terminal OUTa is negatively fed back to the input side through the resistor element R. As shown in FIG. Therefore, the gain of the two-stage amplifying circuit is suppressed, thereby extending the flat band range in the frequency characteristic.

Similarly, in the second signal route, the N-channel MOS transistor N11b constitutes a source ground amplifier circuit having an N-channel MOS transistor N12b and a P-channel MOS transistor P11b as load resistors. The output is obtained from the connection node b between the load resistor and the N-channel MOS transistor N11b. The signal at this node (b) is applied to the gate of the P-channel MOS transistor P11a. The P-channel MOS transistor P11a constitutes a source ground amplifier circuit having an N-channel MOS transistor N11a and an N-channel MOS transistor N12a as a load resistor. Therefore, the signal applied from the input terminal INb is amplified by the two-stage amplification circuit composed of the N-channel MOS transistor N11b and the P-channel MOS transistor P11a and output from the output terminal OUTb. The output signal output to the output terminal OUTb is negatively fed back to the input side through the resistance element R. Therefore, the acquisition of the two-stage amplification circuit is suppressed, thereby extending the smooth band range in the frequency characteristic.

The signal applied to the input terminal INa and the signal applied to the input terminal INb function as differential signals and have opposite phases with respect to each other. In this input signal, a small signal is superimposed on an offset voltage signal. Therefore, when the signal applied to the input terminal INa is higher than the offset voltage signal, the signal applied to the input terminal INb is lower than the offset voltage signal. For this reason, the voltage of the node b is higher than the voltage when the offset voltage signal is applied to the input terminal INb. The voltage of the node b is applied to the gate of the P-channel MOS transistor P11a serving as the load resistor of the N-channel MOS transistor N11a, so that the on resistance of the P-channel MOS transistor P11a is high. Therefore, the amplification factor of the signal applied from the input terminal INa through the N-channel MOS transistor N11a becomes higher. That is, the amplification operation is stronger compared to the case where only a single N-channel MOS transistor N11a is in use. When the characteristic parameter is set and SPICE is used to perform the simulation, the frequency performance of this circuit has a smooth gain of about 12 dB up to about 2 GHz, as shown by the broken line in FIG.

As described above, the differential output circuit shown in FIG. 1 can process signals in a wide frequency band. Typically, the differential signals applied to the input terminals INa and INb have approximately the same offset. However, as shown in Fig. 4A, when the offset of the differential signal applied to the input terminals INa and INb is different (difference x), this differential output circuit is smooth from DC component to AC component over a wide frequency band. Since it has amplification characteristics, the offset is also amplified. For this reason, the difference between the offsets is also amplified, and the difference is increased. In particular, when the frequency of the small signal includes a component of 2 GHz or more, the amplification coefficient of the small signal is lower than that of the DC component. Thus, as shown in Fig. 4C, the difference in the offset is amplified by x " and its signal component is amplified by y " In this case, the efficiency of the differential signal is lowered.

It is therefore an object of the present invention to provide a differential output circuit to compensate for the degradation of the efficiency of the differential signal.

In an aspect of the invention, the differential output signal comprises a bias circuit coupled with the first voltage. The input circuit portion includes first and second MOS transistors of a first conductivity type, the first and second MOS transistors being connected to the first voltage through a bias circuit, and the gates of the first and second MOS transistors being differential Receive an input signal. The third and fourth MOS transistors of the second conductivity type are connected to the first and second MOS transistors, respectively, through the first and second resistor elements and to the second voltage. The first connection node between the first MOS transistor and the first resistive element is connected with the gate of the fourth MOS transistor, and the second connection node between the second MOS transistor and the second resistive element is connected with the gate of the third MOS transistor. Connected. The differential output signal is output from the first output node between the first resistor element and the third MOS transistor and the second output node between the second resistor element and the fourth MOS transistor in response to the differential input signal.

Here, the first and second resistive elements may be composed of fifth and sixth MOS transistors of the first conductivity type, each having a gate connected with the second voltage.

The bias circuit also includes a third resistor element coupled between the first MOS transistor and the first voltage; A fourth resistive element connected between the second MOS transistor and the first voltage; A first capacitance element coupled between the first MOS transistor and the first voltage; And a second capacitance element coupled between the second MOS transistor and the first voltage.

In this case, the third and fourth resistive elements may be composed of seventh and eighth MOS transistors of the first conductivity type, each having a gate connected with the second voltage. In addition, each of the first and second capacitance elements may be composed of a MOS transistor having a source and a drain connected to the first voltage, and a gate connected to the predetermined voltage.

In addition, the bias circuit further comprises: a third resistor element connected between the first MOS transistor and the first voltage; A fourth resistive element connected between the second MOS transistor and the first voltage; It may also include a capacitance element connected between the first node between the first MOS transistor and the third resistive element and the second node between the second MOS transistor and the fourth resistive element. In such a case, the third and fourth resistive elements may be composed of the seventh and eighth MOS transistors of the first conductivity type each having a gate connected with the second voltage. The capacitance element further includes a first additional MOS transistor having a source and a drain connected to the first node and a gate connected to the second node, and a second additional MOS having a source and a drain connected to the second node and a gate connected to the first node. It may be composed of a transistor.

In addition, the differential output circuit may further include a fifth resistor element between the first and second output nodes. In this case, the fifth resistor element may be composed of a ninth MOS transistor of the first conductivity type having a gate connected with a predetermined voltage.

In addition, the input circuitry may further include tenth and eleventh MOS transistors of the first conductivity type provided in parallel with the first and second MOS transistors, respectively, for connecting the gate with the second differential input signal. Instead, the input circuitry may further include tenth and eleventh MOS transistors of the first conductivity type provided in series with the first and second MOS transistors, respectively, for connecting the gate to the second differential input signal.

Hereinafter, a differential output circuit of the present invention will be described with reference to the drawings. 2 is a circuit diagram of a differential output circuit according to the first embodiment of the present invention. The differential output circuit of the first embodiment includes N-channel MOS transistors N1a and N1b, P-channel MOS transistors P1a and P1b, resistor elements R1a, R2a, R1b and R2b, and capacitance elements C1a and C1b. )

The parallel connection of the resistor element R2a and the capacitance element C1a, the N-channel MOS transistor N1a, the resistor element R1a and the P-channel MOS transistor P1a are a low voltage power supply VSS and a high voltage power supply VDD. Are connected in series. That is, the source of the N-channel MOS transistor N1a is connected to the low voltage power supply VSS through the parallel connection of the resistance element R2a and the capacitance element C1a. The parallel connection of the resistive element R2a and the capacitance element C1a functions as a bias circuit for the N-channel MOS transistor N1a. The connection node 1a exists between the source of the N-channel MOS transistor N1a and this bias circuit. The drain of the N-channel MOS transistor N1a is connected to the drain of the P-channel MOS transistor P1a through the resistor element R1a. The connection node 2a exists between the drain of the N-channel MOS transistor N1a and the resistance element R1a and is further connected to the gate of the P-channel MOS transistor P1b. The gate of the N-channel MOS transistor N1a is connected to the input terminal INa. The source of the P-channel MOS transistor P1a is connected to the high voltage power supply VDD. The connection node between the drain of the P-channel MOS transistor P1a and the resistor element R1a is connected to the output terminal OUTb.

Symmetrically, the parallel connection of the resistor element R2b and the capacitance element C1b, the N-channel MOS transistor N1b, the resistor element R1b and the P-channel MOS transistor P1b are connected with the low voltage power supply VSS. Connected in series between high voltage power supplies (VDD). That is, the source of the N-channel MOS transistor N1b is connected to the low voltage power supply VSS through the parallel connection of the resistance element R2b and the capacitance element C1b. The parallel connection of the capacitance element C1b and the resistance element R2b functions as a bias circuit of the N-channel MOS transistor N1b. The connection node 1b exists between the source of the N-channel MOS transistor N1b and this bias circuit. The drain of the N-channel MOS transistor N1b is connected to the drain of the P-channel MOS transistor P1b through the resistor element R1b. The connection node 2b exists between the drain of the N-channel MOS transistor N1b and the resistance element R1b and is further connected to the gate of the P-channel MOS transistor P1a. The gate of the N-channel MOS transistor N1b is connected to the input terminal INb. The source of the P-channel MOS transistor P1b is connected to the high voltage power supply VDD. The connection node between the drain of the P-channel MOS transistor P1b and the resistance element R1b is connected to the output terminal OUTa.

The N-channel MOS transistor N1a has a load circuit composed of the P-channel MOS transistor P1a and the resistive element R1a, and a bias circuit composed of the resistive element R2a and the capacitance element C1a. Has The signal input from the input terminal INa is connected to the gate of the N-channel MOS transistor N1a and amplified. This amplifying circuit applies its output to the gate of the P-channel MOS transistor P1b connected to the node 2a. The P-channel MOS transistor P1b constitutes an amplifier circuit in which the load circuit is composed of the N-channel MOS transistor N1b, the resistance elements R1b and R2b, and the capacitance element C1b. The signal is amplified by the P-channel MOS transistor P1b and output to the output terminal OUTa. Similarly, the N-channel MOS transistor N1b is connected to a load circuit composed of the P-channel MOS transistor P1b and the resistor element R1b and a bias circuit composed of the resistor element R2b and the capacitance element C1b, The signal applied from the input terminal INb is connected to the gate of the N-channel MOS transistor N1b and thereby amplified. This amplifying circuit applies the output to the gate of the P-channel MOS transistor P1a connected to the node 2b. The P-channel MOS transistor P1a constitutes an amplifier circuit in which the load circuit is composed of the N-channel MOS transistor N1a, the resistor elements R1a and R2a, and the capacitance element C1a. The signal is amplified by the P-channel MOS transistor P1a and output to the output terminal OUTb.

An amplifier circuit having an N-channel MOS transistor N1a or N1b as an amplifying element has a resistor element R2a or R2b and a capacitance element C1a or C1b between its source and the low voltage power supply VSS as a bias circuit. In such a bias circuit, the resistor element R2a or R2b mainly operates for the DC component, and the capacitance element C1a or C1b mainly operates as a bypass capacitor for the high frequency component. When a bias resistor is present between the source of the N-channel MOS transistor Nla or Nib and the low voltage power supply VSS, the signal output to the node 2a or 2b is an attenuated signal from the input signal. Since the resistive element R2a or R2b mainly operates for the DC component, the input signal can be greatly attenuated based on the resistance value of the resistive element R2a or R2b. In addition, for the high frequency component, the source of the N-channel MOS transistor N1a or N1b is set to a short-circuit state with respect to the low voltage power supply VSS. Thus, this circuit amplifies the input signal. Therefore, as shown by the solid line in FIG. 3, the frequency characteristic of this differential output circuit has the characteristic of having the peak of attenuation with respect to DC component, and the peak of amplification of a high frequency component.

The signals applied to the input terminals INa and INb function as differential signals. As shown in Fig. 4A, signals having opposite phases overlap each offset voltage. If the offset voltages are equal to each other (x = 0) and the amplitudes y of the overlapping signals are equal to each other, a signal having an efficiency of 50% is obtained. Under normal conditions, each offset voltage is a substantially similar voltage. However, as shown in FIG. 4A, there may be a case where the difference x is generated at an offset voltage. In this case, even if the amplitudes y of the overlapping signals are equal to each other, the efficiency ratio of the differential signal is 60:40. Therefore, symmetry cannot be maintained.

When this differential signal is applied to the differential output circuit shown in Fig. 2, the DC component is attenuated and the high frequency component is amplified. That is, because each offset voltage is attenuated, as shown in Fig. 4B, the difference x 'between the offset voltages is reduced. In addition, since the signal is a high frequency component, as shown in Fig. 4B, the amplitude y 'of the synthesized signal is amplified. Thus, the efficiency ratio between the differential output signals approaches 50:50, which in turn improves.

5 is a circuit diagram showing the configuration of a differential output circuit according to a second embodiment of the present invention. In FIG. 2, the resistive elements R1a, R2a, R1b and R2b are replaced by N-channel MOS transistors N2a, N3a, N2b and N3b, and the resistive elements R1a, R2a, R1b and R2b are N-channel. It is obtained using the channel resistor of the MOS transistor. That is, each gate of the N-channel MOS transistors N2a, N3a, N2b and N3b is connected to the high voltage power VDD, and each transistor is always on. The ON resistance value of each transistor is set according to the size of the transistor.

FIG. 6 is a circuit diagram showing the configuration of the differential output circuit according to the third embodiment of the present invention, in which the capacitance elements C1a and C1b of FIG. 5 are replaced by the capacitance elements C2. Capacitance elements C1a and C1b are charged and discharged with the superimposition signal. The signal on the input terminal INa side and the signal on the input terminal INb side are signals having phases opposite to each other, and their amplitudes are substantially the same. That is, the charging of the capacitance element C1a and the discharge of the capacitance element C1b, and the discharge of the capacitance element C1a and the charging of the capacitance element C1b are alternately performed. Thus, the charge is shifted between these capacitance elements during the charge / discharge operation. Therefore, even if the connecting ends of the capacitance elements C1a and C1b to the low voltage power supply VSS are connected to each other, the connection node substantially appears to be connected to the low voltage power supply VSS. This means that the capacitance elements C1a and C1b can be replaced by the capacitance element C2, and the capacitance elements can be integrated into one unit.

7 is a circuit diagram showing the configuration of a differential output circuit according to a fourth embodiment of the present invention, wherein the differential output circuit has a negative feedback circuit from the output terminal to the input side. This differential output circuit is designed such that the feedback resistor element R1 is inserted between the output terminals OUTa and OUTb of the differential output circuit shown in FIG. Since negative feedback has been applied by the resistive element R1, the gain is limited. Thus, the flat frequency band in the frequency characteristic of the gain is expanded.

FIG. 8 is a circuit diagram showing a configuration of a differential output circuit according to a fifth embodiment of the present invention, the differential output circuit having a negative feedback circuit from the output terminal to the input side, similar to the differential output circuit shown in FIG. . This differential output circuit is designed such that the feedback resistor element R1 is inserted between the output terminals OUTa and OUTb of the differential output circuit shown in FIG. Since negative feedback is applied by the resistive element R1, the gain is limited. Therefore, the smooth frequency band in the frequency characteristic of the gain is expanded. The frequency characteristic of the amplitude gain indicated by the solid line in FIG. 3 is the simulation result after the circuit constant is set in this circuit. Thus, the band of the smooth frequency characteristic is widened, and attenuation with a large gain such as -10 dB for the DC component is obtained.

FIG. 9 is a circuit diagram showing a configuration of a differential output circuit according to a sixth embodiment of the present invention, wherein the sum of two differential signals is applied to the signal input portion of the differential output circuit shown in FIG. The N-channel MOS transistor N4a is connected in parallel with the N-channel MOS transistor N1a. The gate of the N-channel MOS transistor N4a is connected to the input terminal IN2a to which the second differential signal is input. In addition, the N-channel MOS transistor N4b is connected in parallel with the N-channel MOS transistor N1b. The N-channel MOS transistor N4b is connected to the input terminal IN2b to which the second differential signal is input. In this way, since the transistors are connected in parallel, the logical sum of the input signals can be determined. In addition, since the transistors are connected in parallel, the logical sum of many signals can be determined. Also, although not shown, when the transistors are connected in series, a logical product can be determined. Since the transistors are coupled in series and in parallel, different logic operations can be combined.

As shown in Figs. 10A to 10C, the above-described capacitance elements C1a, C1b and C2 can be obtained by using N-channel MOS transistors and / or P-channel MOS transistors. That is, as shown in FIG. 10A, the capacitance elements C1a and C1b connected to the low voltage power supply VSS are preferably obtained by using the gate capacitance of the N-channel MOS transistor N7. Also, as shown in Fig. 10B, the capacitance element connected to the high voltage power supply VDD is preferably obtained by using the gate capacitance of the P-channel MOS transistor P7. Also, as shown in Fig. 10C, the capacitance element C2 is preferably obtained by using the gate capacitance of the N-channel MOS transistors N8 and N9.

In this way, the differential output circuit of the present invention has a high amplitude gain in the high frequency band and attenuates the DC component. With this characteristic, the offset difference of the differential signal is small in the output signal. Therefore, distortion compensation for the efficiency ratio is achieved.

Claims (12)

  1. A bias circuit coupled with the first voltage;
    An input circuit portion comprising first and second MOS transistors of a first conductivity type, wherein the first and second MOS transistors are connected to the first voltage through the bias circuit, and are connected to each other of the first and second MOS transistors. The input circuit portion for receiving a differential input signal;
    First and second resistive elements; And
    A third and fourth MOS transistor of a second conductivity type connected to said first and second MOS transistors through said first and second resistive elements, respectively, and to a second voltage,
    A first connection node between the first MOS transistor and the first resistor element is connected to a gate of the fourth MOS transistor,
    A second connection node between the second MOS transistor and the second resistor element is connected to a gate of the third MOS transistor,
    The differential output signal is output from a first output node between the first resistor element and the third MOS transistor and a second output node between the second resistor element and the fourth MOS transistor in response to the differential input signal. , Differential output circuit.
  2. The method of claim 1,
    Wherein said first and said second resistive element each comprise a fifth and a sixth MOS transistor of said first conductivity type having a gate connected with said second voltage.
  3. The method of claim 1,
    The bias circuit,
    A third resistor connected between the first MOS transistor and the first voltage;
    A fourth resistor connected between the second MOS transistor and the first voltage;
    A first capacitance element coupled between the first MOS transistor and the first voltage; And
    And a second capacitance element coupled between the second MOS transistor and the first voltage.
  4. The method of claim 3, wherein
    And the third and fourth resistive elements each comprise a seventh and eighth MOS transistor of the first conductivity type having a gate connected with the second voltage.
  5. The method of claim 3, wherein
    Wherein the first and second capacitance elements each comprise a MOS transistor having a source and a drain coupled to the first voltage and a gate coupled to a predetermined voltage.
  6. The method of claim 1,
    The bias circuit,
    A third resistor connected between the first MOS transistor and the first voltage;
    A fourth resistor connected between the second MOS transistor and the first voltage; And
    And a capacitance element coupled between a first node between the first MOS transistor and the third resistive element and a second node between the second MOS transistor and the fourth resistive element.
  7. The method of claim 6,
    And the third and fourth resistive elements each comprise a seventh and eighth MOS transistors of the first conductivity type having a gate connected with the second voltage.
  8. The method of claim 6,
    The capacitance element includes a first additional MOS transistor having a source and a drain connected to the first node and a gate connected to the second node, and a source having a source and a drain connected to the second node and a gate connected to the first node. Differential output circuit, consisting of two additional MOS transistors.
  9. The method according to any one of claims 1 to 8,
    And a fifth resistor element between the first output node and the second output node.
  10. The method of claim 9,
    And said fifth resistive element is comprised of a ninth MOS transistor of said first conductivity type having a gate connected to a predetermined voltage.
  11. The method according to any one of claims 1 to 8,
    The input circuit unit,
    And a tenth and eleventh MOS transistor of the first conductivity type provided in parallel to the first and the second MOS transistors, respectively, for connecting a gate with a second differential input signal.
  12. The method according to any one of claims 1 to 8,
    The input circuit unit,
    And a tenth and eleventh MOS transistor of the first conductivity type provided in series with the first and second MOS transistors, respectively, for connecting a gate with a second differential input signal.
KR1020060079374A 2005-08-23 2006-08-22 Differential output circuit with stable duty KR100788223B1 (en)

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JPJP-P-2005-00240748 2005-08-23
KR1020060079374A KR100788223B1 (en) 2005-08-23 2006-08-22 Differential output circuit with stable duty

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KR1020060079374A KR100788223B1 (en) 2005-08-23 2006-08-22 Differential output circuit with stable duty

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KR100788223B1 true KR100788223B1 (en) 2007-12-26

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06204852A (en) * 1992-10-02 1994-07-22 Internatl Business Mach Corp <Ibm> Differential output circuit
US20030042983A1 (en) 2001-09-04 2003-03-06 Hollenbeck Neal W. Single ended input, differential output amplifier
US6590435B1 (en) 2001-08-16 2003-07-08 National Semiconductor Corporation Output differential voltage (VOD) restriction circuit for use with LVDS input buffers
JP2004128747A (en) 2002-09-30 2004-04-22 Nec Electronics Corp Differential output circuit and circuit using it

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06204852A (en) * 1992-10-02 1994-07-22 Internatl Business Mach Corp <Ibm> Differential output circuit
US6590435B1 (en) 2001-08-16 2003-07-08 National Semiconductor Corporation Output differential voltage (VOD) restriction circuit for use with LVDS input buffers
US20030042983A1 (en) 2001-09-04 2003-03-06 Hollenbeck Neal W. Single ended input, differential output amplifier
JP2004128747A (en) 2002-09-30 2004-04-22 Nec Electronics Corp Differential output circuit and circuit using it

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