KR100781268B1 - Digital broadcasting conditional access receiving system and method thereof - Google Patents

Abstract

The present invention relates to a digital broadcast limited reception system and a method thereof, and includes three CAS (Conditional Access System) modules to encrypt digital broadcasting information to the outside, thereby protecting digital broadcasting information and keys reliably. . In addition, the present invention provides a digital broadcast limited reception system and method which can be configured more compactly and can operate flexibly regardless of the memory location by taking a configuration of setting a register without providing a smart card. .

CAS, Memory, Digital, Broadcast, MAC

Description

Digital broadcasting limited reception system and its method {DIGITAL BROADCASTING CONDITIONAL ACCESS RECEIVING SYSTEM AND METHOD THEREOF}

1 is a block diagram illustrating a general digital broadcast limited reception system.

2 is a flowchart illustrating a general digital broadcast restriction reception method.

3 is a block diagram of a digital broadcast limited reception system according to a preferred embodiment of the present invention.

4 is a flowchart illustrating a digital broadcast restriction reception method according to an exemplary embodiment of the present invention.

5 is a block diagram illustrating a protocol stack in an OSI 3 layer.

6 shows the structure of an MPE-FEC frame.

7 shows an example of memory data access for having an MPE-FEC frame structure.

<Explanation of symbols for the main parts of the drawings>

101, 201: TS packet control module 102, 202: second casing module

103, 203: TS packet parsing module

104, 204: first and second address control module

105, 205: RS decoder 106, 207: memory access unit (MAU)

107, 208: ARBITER 108, 209: memory

109, 110, 210, 211: Host I / F

206: second casing module 212: third casing module

213: host

The present invention relates to a digital broadcast receiver, and more particularly, to a system and method for limited reception of digital broadcast.

In the digital broadcasting system, pay broadcasting is provided by using a specific method. In order to watch the pay broadcasting, a CAS (Conditional Access System) module must be mounted in the broadcast receiver.

The CAS module may be implemented in a built-in type and an externally inserted type, but the CAS module may be installed inside a chip that manages a data link layer (MAC-Layer) that manages transmission error detection and error control of a data block through a communication medium. The memory for storing digital broadcast information is provided outside the chip that is in charge of the data link layer.

1 is a block diagram of a general digital broadcast limited reception system 100 in a DVB-H receiver.

As shown in FIG. 1, a block diagram showing a part of a chip in charge of a data link layer (MAC Layer) in a digital broadcast receiver is shown. In general, the digital broadcast limited reception system 100 includes one casing module. .

In brief, the configuration, the TS packet control module 101 for controlling the received TS packet, the first casing module 102 to perform descrambling if the received TS packet is scrambled, parsing the descrambled TS packet A TS packet parsing module 103 for parsing a section and extracting an IP datagram, that is, IP data, and first and second address control modules 104 for address-controlling and storing the extracted IP data. The memory 108 in which the IP data is stored, the RS decoder 105 which reads the IP data stored in the memory 108 and performs RS decoding, and stores the data again in the memory 108, the IP data or the RS decoding. A memory access unit (MAU) 106 for reading / writing the performed IP data, an arbiter 107 for controlling the priority of the MAU, and the IP data. Host (Host or CPU) (1 11) Host I / F (Interface) (109, 110) for connecting to the host 111 to read and play the IP data stored in the memory 108 through the host I / F (110).

In brief, if the TS packet signal transmitted from the transmitter is scrambled, the cas module 102 undergoes a descrambling process, and parses the descrambled TS packet signal to extract IP data. The extracted IP data is address-controlled and stored in the memory 108 located inside or outside the chip that is in charge of the data link layer. Since the IP data stored in the memory 108 is data which has not been subjected to error correction, the RS decoder 105 corrects the error and stores the data again in the memory 108, where the RS decoded and stored IP data is hosted. 111 will read and play.

In this case, if the transmitted TS packet signal is not scrambled, the TS packet signal is directly played by the host 111 through the host I / F 109 in the cas module 102 or bypassed by the first cas module 102. Done.

Also, since the output of the physical layer, which is an input of the data link layer, is a transport stream (TS) packet rather than an IP datagram, an IP datagram is extracted from the TS packet. To do this, TS packet decoding and section decoding must be performed. When the transmitter transmits the TS packet to the receiver, only the payload section except for the header of the TS packet is scrambling and transmitted. The receiving end may determine whether or not it is scrambled by looking at the Transport Scrambling Control (TSC) field of the TS packet header.

The foregoing structure is shown in FIG. 5 and will be described in detail below.

However, digital broadcast receivers are becoming smaller and smaller in size, and for miniaturization, the digital broadcast reception limiting system is configured such that the location of the memory 108 is located outside the chip representing a part of the data link layer.

Therefore, since the IP data is stored in the memory 108 located outside the chip that is in charge of the data link layer or is descrambled when read, there is a risk of being easily exposed to security.

2 is a flowchart illustrating a general digital broadcast restriction reception method in a DVB-H receiver.

As shown, the header portion of the received TS packet signal is parsed (S301), and it is determined whether the received TS packet is scrambled (S302). If scrambling is performed, the process proceeds to the step of performing descrambling (S303). If it is determined that the descrambling is performed, the first casing module 102 bypasses the bit of the TSC if it is not even / odd. The next step is to proceed to the address control step (S304). In addition, if it is determined that descrambling, the process proceeds directly to the address control step (S304). Next, the data is stored in the memory (S305), the RS decoding is performed through the step of performing the RS decoding (S306), and stored in the memory (S307). Next, the host reads and plays the IP data stored in the memory (S308).

However, in the digital broadcasting reception system of this type, since the memory is exposed to the outside when the digital broadcasting information is stored in the memory or the digital broadcasting information stored in the memory is read and played from the host, the broadcasting is provided for a fee. There was a problem that information could not be protected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a digital broadcast limited reception system and method capable of reliably protecting digital broadcast information and keys.

It is still another object of the present invention to provide a digital broadcast limited reception system and method capable of blocking outgoing information in advance by using a conditional access system (CAS) and reliably protecting broadcast information and keys.

The digital broadcast limited reception system according to the present invention for achieving the above object is a digital broadcast reception system having a first casing module and a memory, the digital broadcast reception system having a first casing module and a memory, A TS packet signal parsing unit for descrambling and parsing a transport stream (TS) packet signal in the first casing module, extracting IP data of the parsed signal, and controlling the address; A second casing module configured to perform scrambling based on a data link layer chip position of a memory to store the IP data and to descramble the IP data based on a data link layer chip position of a memory to be read; An RS decoding unit for performing error correction by calling the stored IP data processed by the second casing module; And a third casing module configured to perform descrambling based on the position of the data link layer chip of the memory when the IP data stored in the memory is read to play the stored IP data.

Here, the second casing module and the third casing module store and calculate a scrambler for scrambling IP data, a descrambler for descrambling IP data, control logic for generating and interpreting control data, and a key. It consists of a key register.

At this time, it is desirable to download the key periodically through the wired / wireless to the set register.

The IP data on which the error correction is performed is stored after performing scrambling based on the location of the data link layer chip of the memory.

The IP data on which the error correction is performed is stored after performing scrambling based on the location of the data link layer chip of the memory.
When the memory is located outside the chip that is responsible for the data link layer, the IP data is characterized in that any one of scrambling and descrambling is performed.

Digital broadcast limited reception method according to the present invention for achieving the above object is

(a) descrambling and parsing the received TS packet signal, and extracting IP data of the parsed signal to control an address;

(b) scrambling and storing the address controlled IP data in step (a);

(c) reading, descrambling, RS decoding, and then scrambling and storing the IP data stored in step (b);

and (d) reading and descrambling to play the stored IP data in step (c).

Here, in step (b), if the location of the memory in which the IP data extracted in step (a) is to be stored is located inside the chip in charge of the data link layer, the scrambling process performed when the extracted IP data is stored is omitted. It is possible.

Also, in the step (c), if the location of the memory in which the IP data to be read is located in the chip that is responsible for the data link layer, the descrambling / scrambling process performed before and after RS decoding is omitted to perform RS decoding. It is possible.

Here, in step (d), if the location of the memory in which the IP data to be read is stored is located inside the chip for the data link layer, the descrambling process performed when the IP data is read may be omitted. Do.

The present invention is characterized in that the digital broadcasting reception system includes three casing modules to more securely protect digital broadcasting information.

In addition, since the present invention is configured without a smart card module, a master private key (MPK) and an encryption master private key (EMPK) stored in the smart card are set. It is periodically updated and stored in wired and wireless registers via wired / wireless communication.

Other objects, features and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described by at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

3 is a block diagram of a digital broadcast limited reception system 200 according to a preferred embodiment of the present invention in a DVB-H receiver.

As shown in FIG. 3, similar to FIG. 1, a block diagram illustrating a part of a chip that is responsible for a data link layer in a digital broadcast receiver is a digital broadcast limited reception system 200 according to an embodiment of the present invention. ) Is further comprised of two casing modules.

In brief, the configuration of the TS packet control module 201 for controlling the received TS packet, the first cas module 202 for performing descrambling if the received TS packet is scrambled, the descrambled TS packet The TS packet parsing module 203 which parses and configures a section, and then extracts IP data, and the first and second address control modules 204 which store IP data by performing address control on the extracted IP data. A second casing module 206 that performs scrambling / descrambling when storing or reading the extracted IP data, a memory 209 in which the scrambled IP data is stored, and the IP data stored in the memory 209 RS decoder 205 reads and performs RS decoding and stores in memory 209, and memory accesses to read / store the IP data or IP data on which RS decoding has been performed Device (MAU: Memory Access Unit) 207, Arbiter (208) for controlling the priority of the MAU, Host I / F (Interface) (210, 211) for connecting the IP data to the host, If the IP data is scrambled when the IP data stored in the memory 209 is read through the host I / F 210, the third cas module 211 performing descrambling and the descrambled IP data are executed. It consists of the host 213 to play.

In brief, if the TS packet signal transmitted from the transmitter is scrambled, the cas module 202 undergoes a descrambling process, and parses the descrambled TS packet signal to extract IP data. The extracted IP data is address controlled and stored in a memory 209 located outside the chip in charge of the data link layer. At this time, since the IP data is descrambled, there is a risk of leakage to the outside for security reasons. have. Accordingly, the descrambled IP data is scrambled by the second cas module 206 and stored in the memory 209. Next, the scrambled IP data scrambled in the memory 209 is descrambled by the second cas module 206, read by the RS decoder 105, RS decoded, and then scrambled again and stored in the memory 209. do. At this time, since the RS decoded and stored IP data is scrambled, when the host 213 reads it, it is descrambled again by the third casing module 212 to be played by the host 213.

Here, if the transmitted TS packet signal is a signal that is not scrambled, the TS packet signal may be played in the host 213 directly through the host I / F 210 in the first casing module 202, or the second casing module 206. May be sent to the memory 209 and stored in the memory 209.

Therefore, in the digital broadcast limited reception system, the security of broadcast information can be ensured even if the memory adopts a configuration located outside the chip that is responsible for the data link layer.

In addition, the main point here is that the register type is set to I ² C type according to whether the location of the memory where the IP data is stored is located inside or outside the chip that is responsible for the data link layer in the digital broadcasting receiver. The two casing module 206 may be disabled.

If the memory 209 is located inside the chip in charge of the data link layer, since the third casing module 211 processes outgoing IP data, security can be thoroughly maintained. However, when the memory 209 is external, the second cas module 206 must be used. In practice, however, a slight delay may be generated when the second casing module is operated or not, but since the security is focused on the information, the information is not exposed to the outside.

Another advantage is that it does not have a smart card module, and the MPK (Master Private Key), which is currently stored using a smart card, is periodically downloaded through external wired / wireless communication. At this time, since the MPK tends to be exposed, the EMPK which encrypts the MPK is downloaded together according to a predetermined protocol.

The principle of operation is to decrypt the Entitlement Management Message (EMM) with the MPK from the MPK by decrypting the MPK with EMPK, and to decrypt the Entitlement Control Message (ECM) with the Key from the EMM. You will get the CW (Control Word) needed to run it.

The above-described operating principle is made in a smart card module, and in the embodiment according to the present invention, as described above, the MPK (Master Private) stored in the smart card may be configured to set a register without having a smart card module separately. Key) and EMPK (Encrypt Master Private Key) take a method of periodically updating and storing the set register through external wired / wireless communication.

Thus, the space required for using the smart card module can be reduced.

The operation of the casing module is basically a process of obtaining a CK (Common Key) from CW and a process of descrambling Scrambling Stream Data with CK.

Here, in the block configuration of the casing module, the first CAS modules 102 and 202 may include a descrambler, a control logic, and a key register, according to an embodiment of the present invention. The second cas module 206 and the third cas module 212 further include a scrambler, a descrambler, control logic, and a key register.

Accordingly, the digital broadcast limited reception system 200 according to the embodiment of the present invention has the configuration as described above, even if the memory that is easy to be exposed to the outside employs a configuration located outside the chip that is responsible for the data link layer. You can be sure of security.

4 is a flowchart illustrating a digital broadcast limited reception method according to a preferred embodiment of the present invention in a DVB-H receiver.

The first time a user sets up a register setting, it flows through the flow of the restricted receiving system block accordingly. However, the digital broadcast restriction reception method according to an embodiment of the present invention can operate the 3-CAS module flexibly.

As shown, the header portion (field) of the received TS packet signal is parsed (S401), and it is determined whether the received TS packet is scrambled (S402). If scrambling is performed, the process proceeds to the step of performing descrambling (S403). If the bit of the TSC is not even / odd in the first casing module, even if it is determined to be descrambling, the next step is bypassed. The process proceeds to the in-address control step S404. In addition, if it is determined that descrambling, the process proceeds directly to the address control step (S404).

Next, the TS packet is parsed to determine whether the location of the memory in which the extracted IP data is to be stored is located inside or outside the chip that is responsible for the data link layer (S405). Scrambling is performed (S406) and stored in the memory (S407). If it is determined that the location of the memory is located inside, the process proceeds to the step of storing the memory immediately (S407).

Next, it is determined whether the location of the memory from which the IP data is read to activate the RS decoding is located inside or outside the chip that is responsible for the data link layer (S409), and the location of the memory is outside the chip that is responsible for the data link layer. If it is determined to be in the second cas module descrambling (S409) and performs RS decoding (S410). If it is determined that the location of the memory from which the IP data is to be read is inside the chip in charge of the data link layer, the process proceeds to the step of performing RS decoding immediately (S410).

Next, it is determined whether the location of the memory in which the RS-decoded IP data is to be stored is located inside or outside the chip that is responsible for the data link layer (S411), and the location of the memory is outside the chip that is responsible for the data link layer. If it is determined to be in the second cas module scrambling is performed (S412), and stored in the memory (S413). If it is determined that the location of the memory in which the IP data is to be stored is inside the chip that is in charge of the data link layer, the process proceeds to the step of immediately storing the memory (S413).

Next, it is determined whether the location of the memory for reading the IP data to activate the host read start is located inside or outside the chip that is responsible for the data link layer (S414), and the location of the memory is outside the chip that is responsible for the data link layer. If it is determined that the third casing module descrambles the IP data (S415), and read from the host to play (S416). If it is determined that the IP data is inside the chip in charge of the link layer, the process proceeds to the step of playing directly from the host (S416).

In the above-described method, the digital broadcast restriction reception method according to an embodiment of the present invention may turn a flow according to a user's first register setting, but according to the location of the memory, 3-CAS Can be operated flexibly.

Therefore, the security of broadcast information can be assured even if the memory which is easy to be exposed to the outside employs a configuration located outside the chip that is responsible for the data link layer.

Hereinafter, a DVB-H protocol stack and a multi-protocol encapsulation (MPE) -forward error correction (FEC) frame structure will be briefly described to help understand the present invention. .

FIG. 5 is a block diagram illustrating a protocol stack as an OSI 3 layer, and is divided into a network layer, a data link layer, and a physical layer.

As shown, MPE, MPE-FEC, and IP / PSI (Program Specific Information) information of a datagram section structure are separated from a TS packet stream, and extracted from the section datagram as IP data from which headers and CRCs are removed. . Extracting the IP data from the TS packet is all performed at the data link layer. The IP data inside the chip that is in charge of the data link layer is stored in memory located inside or outside the chip that is in charge of the data link layer through the RS decoder, and the IP data is read from the host. Will play.

FIG. 6 shows the structure of an MPE-FEC frame. The MPE-FEC frame structure consists of 255 bytes and consists of 191 bytes of an application data table and 64 bytes of an RS data table.

RS decoding requires one row of MPE data and MPE-FEC data. However, since MPE and MPE-FEC Section data payloads are recorded continuously in vertical units, that is, in columns, in order to read the rows in order, the address must be read while jumping by the number of rows (no_of_row). No_of_row is defined as four of 256, 512, 768, and 1024 in the DVB-H specification. The MAU is designed to automatically jump addresses in units of no_of_row. When data enters in section unit, it contains information of Start Address, End Address, Start, End of MPE and MPE-FEC. When parsing the section structure and telling the MAU the address, it starts with the Start Address and jumps to the no_of_row unit to read the data and perform the write operation. In case of typical RS decoder, 32bytes symbol error is corrected.However, due to the characteristic of DVB-H data link layer that can determine the error through CRC check for each section, erasure RS decoding is used for error of maximum 64 bytes per row. I can correct it.

7 shows an example of memory data access for having an MPE-FEC frame structure.

As shown, the change of the address for reading data to perform RS decoding is shown as an example. Considering the data transmission in the MPE-FEC frame structure shown in Fig. 6, it can be considered that the data is all filled in the frame and the case is filled only to some extent. Here is a situation where only the latter is filled to some extent. In case of Read operation, all MPE-FEC frames are read. In case of Write operation, however, only MPE data is stored again. When not filled, the byte mask can be used to read how many bytes are filled when reading and writing in 4-byte units. Fill it with

Above, preferred embodiments of the present invention described above are disclosed for the above purposes, and such changes and implementations fall within the scope of the present invention.

The present invention provides two CAS modules inside the chip that is in charge of the data link layer and one CAS module located at the outside of the chip in the digital broadcasting reception system, thereby preventing information leaking from the inside of the chip to the outside in advance. In addition, the stream data can be safely delivered to be played on the host side.

Since a small size of CAS is used, the chip size can be reduced, and it can operate flexibly depending on whether the stream data is stored in the memory located inside the chip or the memory located outside the chip. You can play the data.

In addition, since the present invention can be configured without providing a smart card module, the chip size can be further reduced.

In addition, the present invention is widely applicable not only to DVB-H receivers, but also to data broadcasting layers of similar broadcasting systems, digital broadcasting limited reception systems, and broadcasting systems requiring modules, which are introduced for IP Data Casting (IPDC). CAS can also be applied to a scheme of dividing memory into blocks.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (10)

In the digital broadcast receiving system having a first casing module and a memory, A TS packet signal parsing unit for descrambling and parsing a transport stream (TS) packet signal in the first casing module, extracting IP data of the parsed signal, and controlling the address; A second casing module configured to perform scrambling based on a data link layer chip position of a memory to store the IP data and to descramble the IP data based on a data link layer chip position of a memory to be read; An RS decoding unit for performing error correction by calling the stored IP data processed by the second casing module; And a third casing module configured to perform descrambling based on the position of the data link layer chip of the memory when the IP data stored in the memory is read to play the IP data stored in error. . The method of claim 1, The second casing module and the third casing module, With a scrambler that scrambles IP data With a descrambler that descrambles IP data Control logic for generating and interpreting control data, And a key register for storing and operating keys. The method of claim 2, And the key is periodically downloaded to the set register via wired / wireless. The method of claim 1, And the called IP data performs error correction after descrambling based on the location of a data link layer chip in a memory. The method of claim 1, And the IP data on which the error correction is performed is stored after scrambling based on the location of the data link layer chip in the memory. The method of claim 1, And when the memory is located outside of a chip that is in charge of a data link layer, performing any one of scrambling and descrambling the IP data. (a) descrambling and parsing the received TS packet signal, and extracting IP data of the parsed signal to control an address; (b) scrambling and storing the address controlled IP data in step (a); (c) reading, descrambling, RS decoding, and then scrambling and storing the IP data stored in step (b); and (d) reading, descrambling and playing the stored IP data in the step (c). The method of claim 7, wherein Step (b) is If the location of the memory in which the IP data extracted in step (a) is to be stored is located inside the chip that is responsible for the data link layer, the scrambling process performed when storing the extracted IP data can be omitted. How to receive broadcast restrictions. The method of claim 7, wherein In step (c), In order to perform the RS decoding, if the location of the memory in which the IP data to be read is stored is located inside the chip for the data link layer, the descrambling / scrambling process performed before and after RS decoding can be omitted. Digital broadcast restriction reception method. The method of claim 7, wherein Step (d) For the IP data play, if the location of the memory in which the IP data to be read is located in the chip for the data link layer, the descrambling process performed when the IP data is read can be omitted. Digital broadcast restriction reception method.

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