KR100780670B1 - Sampling clock selection method and apparatus in wireless telecommunication system - Google Patents

Abstract

A method and an apparatus for selecting a sampling clock signal in a wireless communication system are provided to synchronize digital data signals outputted from respectively different channel cards and main stable communication by continuously monitoring sampling clock signals provided from more than two channel cards and using a normal high-priority sampling clock signal as a reference sampling clock signal. An apparatus for selecting a sampling clock signal in a wireless communication system comprises a clock judgment unit(30) and a clock selection part(40). The clock judgment unit(30) receives sampling clock signals from more than two channel cards, judges whether the received sampling clock signals respectively are normal, and outputs a detection signal for each of the sampling clock signals. The clock selection part(40), if detection signals are inputted from the clock judgment unit(30), confirms the normality or abnormality of the sampling clock signals according to their priority, selects a high-priority sampling clock signal among the normal sampling clock signals, and outputs it as a reference sampling clock signal. In case a sampling clock signal, of which the priority is higher than the selected and outputted sampling clock signal, is inputted normally, the clock selection part(40) outputs it as a reference sampling clock signal.

Description

Sampling clock selection method and apparatus in wireless telecommunication system

1 is a configuration diagram illustrating an example of a sampling clock signal selection device of a wireless communication system.

2A and 2B are diagrams illustrating another example of the sampling clock signal selection apparatus of the wireless communication system.

3 is a block diagram showing a sampling clock signal selection apparatus in a wireless communication system according to the present invention.

4 is a flowchart illustrating a sampling clock signal selection method in a wireless communication system according to the present invention.

5 is a block diagram of a base station in a wireless communication system according to the present invention.

6 is a configuration diagram of a repeater interface unit synchronized by a reference sampling clock signal according to the present invention.

Explanation of symbols on the main parts of the drawings

30: clock determination means 31: first clock signal determination unit

32: second clock signal discrimination unit 33: third clock signal discrimination unit

40: clock selector 50: main control and clock unit

52: GPS receiver / clock distributor 60: digital channel card unit

61: first channel card 62: second channel card

63: third channel card 71: transmission and reception unit

90 repeater interface unit

The present invention relates to a method and apparatus for selecting a sampling clock signal in a wireless communication system. More particularly, the present invention relates to a sampling clock signal provided from two or more channel cards. A sampling clock signal selection method and apparatus in a wireless communication system for synchronizing digital data signals output from different channel cards and maintaining stable communication by using them as sampling clock signals.

The present invention also relates to a method and apparatus for selecting a sampling clock signal in a wireless communication system which can be very easily applied to various boards that directly interface with a repeater interface board or a channel card of a wireless communication system.

Recently, with the development of electronic / communication technology, a mobile communication service using a wireless network has been provided. The mobile communication service provides a user with voice communication or other contents through a mobile terminal. Data communication is provided to receive content from the server. In order to perform the voice or data communication as described above, it is necessary to secure a communication channel between the mobile terminal, the base station, and the control station. The communication channel is mainly managed by a channel card installed inside the base station. When the channel card receives a radio frequency (RF) signal down-converted and converted into a digital signal, the channel card processes the converted digital signal to manage data transmission and reception and communication channels.

On the other hand, there is a limit to the communication channel that can be secured by one channel card, and as the number of service users increases, the channel card must be additionally configured to secure more communication channels.

That is, the base station configures two or more channel cards having different frequency bands according to frequency allocation, secures sufficient communication channels using the two or more channel cards, and provides data through each channel card. Will be processed and sent. In this case, the digital data signal and the sampling clock signal processed in each channel card have different propagation delays for each channel card, and thus the digital data signal processed in each channel card. Should be synchronized.

The present invention, as described above, by synchronizing the digital data signal processed in the wireless communication system using two or more channel cards, more specifically, two or more channel cards installed in the base station of the portable Internet system, in particular the wireless communication system It is to provide stable communication channel in portable internet system.

Another object of the present invention is to provide a sampling clock signal selection method and apparatus in a wireless communication system that can be very easily applied to various boards that interface directly with a repeater interface board or a channel card of a wireless communication system.

For this purpose, a sampling clock signal selection method in a wireless communication system according to the present invention comprises the steps of: receiving a sampling clock signal transmitted from two or more channel cards; Determining whether or not each sampling clock signal inputted from the channel card is normal; And outputting one reference sampling clock signal selected by a preset reference among the normal sampling clock signals.

In addition, it is preferable to give a priority to the sampling clock signal transmitted from the at least two channel cards, and to output a sampling clock signal having a higher priority among the normal sampling clock signals as a reference sampling clock signal.

That is, the sampling clock signal provided from the at least two channel cards is continuously monitored, a normal sampling clock signal having a high priority is output as the reference sampling clock signal, and different channels are used by using the output reference sampling clock signal. By synchronizing the digital data signals output from the card, stable communication can be maintained.

On the other hand, the sampling clock signal selection device in the wireless communication system according to the present invention receives the sampling clock signal transmitted from two or more channel cards, and determines whether or not each sampling clock signal is normal, the normal of the sampling clock signal Clock determination means for outputting a detection signal for whether or not, and receiving the detection signal output from the clock determination means to check whether the sampling clock signal is normal according to a given priority, priority of the normal sampling clock signal It characterized in that it comprises a clock selector for selecting a high sampling clock signal to output a reference sampling clock signal.

1 to 4 showing a preferred embodiment of the present invention, a method of selecting sampling clock signals output from different channel cards will be described. Using the selected sampling clock signal is shown in FIG. This will be described with reference. For reference, in the following description, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention are omitted. In addition, although the present invention is applied to the portable Internet system, the present invention is not limited thereto.

Selection of the sampling clock signal transmitted from one of the two or more channel cards is shown in FIG. That is, the clock selector 10 confirms whether each of the two or more channel cards are mounted, selects a sampling clock signal transmitted from any one of the mounted channel cards, and outputs it as a reference sampling clock signal. The digital data signal is synchronized with the reference sampling clock signal. However, the above method determines only the removal / mounting of the channel card, and outputs the reference sampling clock signal because the sampling clock signal output from the mounted channel card is output as the reference sampling clock signal. If a normal sampling clock signal cannot be output due to a failure or the like in a state in which the selected channel card is mounted, the normal reference sampling clock signal is not output, and thus the digital data signal cannot be synchronized, thereby making communication impossible. .

In order to solve the above problems, as shown in FIG. 2A, when a sampling clock signal transmitted from two or more channel cards is input to an OR gate 20 and the output is used as a reference sampling clock signal, Even if the sampling clock signal is not input from any one channel card as described above, the sampling clock signal input from one or more channel cards may be received and output. That is, even if the sampling clock signal of the third channel card is not transmitted, the sampling clock signals of the first channel card and the second channel card can be received and output as the reference sampling clock signal.

However, since the sampling clock signals output from the at least one channel card may have different transmission delay characteristics, the sampling clock signals output from the first, second, and third channel cards may be different from each other, as shown in FIG. 2B. When the input signal is input to the OR gate 20 with a different transmission delay characteristic, the reference sampling clock signal output from the OR gate 20 deteriorates the duty ratio so that the clock characteristic for synchronization of the digital data signal is not satisfied. There is a problem.

Hereinafter, a preferred example of a method and apparatus for selecting a sampling clock signal in a wireless communication system that solves the above problems will be described by applying to a wireless communication system having 3FA (Frequency Allocation).

3 is a block diagram showing a sampling clock signal selection device in a wireless communication system according to the present invention, comprising: clock determination means 30 for determining whether the sampling clock signal output from two or more channel cards is normal or not; And a clock selector 40 which outputs one sampling clock signal among the sampling clock signals output from the two or more channel cards according to the determination result of the clock determination means 30. The clock determination means 30 ) Is a first clock signal determination unit 31 that receives the sampling clock signal of the first channel card and determines whether it is normal, and a second clock signal determination unit that determines whether the sampling clock signal of the second channel card is normal. And a third clock signal discrimination unit 33 for receiving the sampling clock signal of the third channel card and determining whether it is normal.

The first clock signal determination unit 31 to the third clock signal determination unit 33 determine whether the sampling clock signal of the corresponding channel card is normal by using a digital programming phase-locked loop (DPPLL). Determining whether the input signal (signal transmitted from the actual channel card) and the normal sampling clock signal (set reference signal) match with each other, and if the input signal matches the reference signal, determine the first clock signal. The unit 31 to the third clock signal determination unit 33 output a specific value (for example, High) as a detection signal. Here, the DPPLL is a digital implementation of an analog phase-looked loop (PLL). When the DPPLL is implemented using a field-programmable gate array (FPGA), the normal sampling clock signal is generated by a separate configuration. Without doing so, it is possible to implement a program to determine whether the sampling clock signal transmitted from the channel card is normal. In addition, although the DPPLL is used as a means for determining whether the sampling clock signal of the corresponding channel card is normal, the present invention is not limited thereto. If the same function is performed, various ones may be applied according to the needs of those skilled in the art.

In addition, the first clock signal discrimination unit 31 to the third clock signal determination unit 33 may change a frequency of the input sampling clock frequency, and a phase of the input sampling clock signal to 0 °, respectively. Phase shifting function to change to 90 °, 180 °, 270 °, etc., and dynamic reconfiguration to reset the functions of the first clock signal discriminator 31 to the third clock signal discriminator 33. (Dynamic Reconfiguration) function is included.

The clock selector 40 receives a detection signal output from the first clock signal determination unit 31 to the third clock signal determination unit 33. When the detection signal is a specific value, the clock selection unit 40 receives the corresponding sampling clock signal. It is determined to be normal and is output as a reference sampling clock signal. In addition, when two or more detection signals having the specific value are selected, one of two or more normal sampling clock signals is selected and output as a reference sampling clock signal, preferably, the priority is given to the sampling clock signal, A sampling clock signal having a higher priority among normal sampling clock signals is output as a reference sampling clock signal.

Hereinafter, the operation of the sampling clock signal selection device in the portable Internet system having the 3FA configured as described above, in order of the sampling clock signal output from the third channel card from the sampling clock signal output from the first channel card Is assumed to be set, and will be described in more detail with reference to FIG. 4.

The first sampling clock signal transmitted from the first channel card is input to the first clock signal determination unit 31, and the first clock signal determination unit 31 determines whether the input sampling clock signal is normal by the DPPLL. Determine and output the result as a first detection signal.

The second sampling clock signal transmitted from the second channel card is input to the second clock signal determination unit 32, and the second clock signal determination unit 32 determines whether the input sampling clock signal is normal by the DPPLL. Determine and output the result as a second detection signal.

The third sampling clock signal transmitted from the third channel card is input to the third clock signal discrimination unit 33, and the third clock signal discrimination unit 33 determines whether the input sampling clock signal is normal by the DPPLL. Determine and output the result as a third detection signal.

It is preferable to simultaneously determine whether the sampling clock signals transmitted from the first to third channel cards are normal. In the following, a method of selecting any one of the first to third sampling clock signals is described in detail. Explain.

The clock selector 40 checks the first detection signal (S100), and when the first detection signal is a specific value (for example, High), the clock selector 40 normally operates in a state where the first channel card is mounted. In operation S102, the sampling clock signal transmitted from the first channel card is selected (S104), and the sampling clock signal of the selected first channel card is output as a reference sampling clock signal (S106).

If the first detection signal is not a specific value (for example, Low), the clock selector 40 determines that the first channel card is detached or malfunctions, and the second detection signal is detected. Check (S110). When the second detection signal has a specific value (for example, High), it is determined that the second channel card is normally operated in a mounted state (S112), and the sampling clock signal transmitted from the second channel card is determined. In operation S114, the sampling clock signal of the selected second channel card is output as a reference sampling clock signal in operation S106.

When the first and second detection signals are not a specific value (for example, Low), the clock selector 40 determines that the first and second channel cards are detached or malfunction, and the A sampling clock signal transmitted from the third channel card is selected (S116), and the sampling clock signal of the selected third channel card is output as a reference sampling clock signal (S106).

On the other hand, the clock selector 40 when all of the first detection signal to the third detection signal is not a specific value, that is, when all of the first channel card or the third channel card is mounted or malfunctions, The administrator is notified that an abnormality has occurred in the corresponding channel, and a method of informing the administrator of the abnormality of the corresponding channel may be a known remote monitoring method (or device). After selecting and outputting any one of the sampling clock signals of the first channel card to the third channel card as described above (S106), the process is repeated when a predetermined time has elapsed (S108). The output of the clock signal is maintained or changed.

That is, when a predetermined time elapses after the sampling clock signal transmitted from the third channel card is output as the reference signal, the first detection signal is reconfirmed (S100). In this case, the first clock signal determination unit 31 When the first detection signal output from the change from low to high (for example, when mounted in a state in which the first channel card is mounted), it is determined that the first channel card is normally operated (S102), The sampling clock signal transmitted from the first channel card is selected (S104), and the reference sampling clock signal from which the sampling clock signal of the third channel card is output is output as the sampling clock signal of the first channel card (S106). ). Here, the predetermined time may be variously applied according to the needs of those skilled in the art.

If the first detection signal is not a specific value (for example, Low), the clock selector 40 determines that the first channel card is still detached or malfunctions, and the second detection is performed. Check the signal (S110). When the second detection signal is changed from low to high, it is determined that the second channel card is normally operated (S112), and the sampling clock signal transmitted from the second channel card is selected (S114). The sampling clock signal of the two channel card is output as the reference sampling clock signal (S106).

In addition, when a predetermined time elapses after the sampling clock signal of the second channel card is output as the reference sampling clock signal, the first detection signal is reconfirmed (S100). In this case, the first clock signal determination unit ( When the first detection signal output from 31 is changed from low to high (for example, when the first channel card is mounted in a detached state), it is determined that the first channel card is normally operated (S102). Selects a sampling clock signal transmitted from the first channel card (S104), and outputs a reference sampling clock signal from which the sampling clock signal of the second channel card is output as the sampling clock signal of the first channel card; (S106).

That is, the first detection signal to the third detection signal is checked every predetermined time, and when the first detection signal is high, the first channel card is irrespective of the second detection signal and the third detection signal. Outputs a sampling clock signal as a reference sampling clock signal, and when the first sensing signal is low and the second sensing signal is high, sampling of the second channel card regardless of the third sensing signal. Outputs a clock signal as a reference sampling clock signal, and outputs the third sensed signal when the first sensed signal and the second sensed signal are low and the third sensed signal is high. .

The reference sampling output signal of the clock selector 40 as described above is a case where priority is set in the order of the sampling clock signal output from the third channel card from the sampling clock signal of the first channel card. Priority may be set by sequentially setting the first to third sensing signals output from the determination unit 31 to the third clock signal determination unit 33. That is, the clock selector 40 may select one of two or more input sampling clock signals or detection signals to set priorities. The method of setting the priority of the sampling clock signals or detection signals is as described above. Of course, it is not limited to being set.

The base station (RAS: Radio Access Station) to which the sampling clock signal selection apparatus according to the present invention configured as described above is applied, as shown in FIG. 5, the clock determination means 30, the clock selection unit 40, the main control and the clock unit 50, digital channel card unit 60, transmit / receive unit 71, high power amplifier unit 72, RF front-end unit 73, network interface switch unit 80, repeater interface unit 90, etc. It consists of.

The main control and clock unit (MCCU) 50 includes a base station management processor (RMP) RAS 51 and a GPS receiver / clock distribution 52. Unit. The base station management processor 51 manages a call processor, performs a function of collecting communication, control, and final alarm for a lower block to report to a control station, and performs a GPS receiver / clock. The divider 52 performs a function of distributing the clock-related signals received from the satellite to lower blocks in order to operate a portable Internet system requiring accurate time synchronization. The main control and clock unit can be operated in redundancy (dual main control and clock unit).

Digital Channel Card Unit (DCCU) 60 is a unit that processes MAC / PHY modems in portable Internet systems. ), And processes data transmission to and from the mobile terminal by performing a function such as subchannel allocation to the FUSC / PUSC, and also supports a reception diversity function to the repeater interface unit 90. The digital channel card unit 60 is connected to the transmission / reception unit 71 and the repeater interface unit 90 through a serial and serial converter (SerDes: Serial and Desrializer), and the main control and clock unit 50 and the network interface switch unit ( 80) and Ethernet to facilitate the data processing between the mobile terminal and the base station. The digital channel card unit 60 is composed of the first channel card 61 to the third channel card 63 in the portable Internet system having 3FA (Frequency Allocation) as in the preferred embodiment of the present invention.

The transceiver unit (TRXU) 71 converts the digital IF signal transmitted from the digital channel card unit 60 into an RF signal, and transmits it to the high power amplification unit 72, and transmits the signal from the RF front-end unit 73. The received RF signal is converted into a digital IF signal and transmitted to the digital channel card unit 60.

RAS High Power Amplifier Unit (RPAU) 72 performs a function of linearly high output amplifying the downlink signal of frequency uplink in the transmitting / receiving unit 71 without distortion. Transfer to front-end unit 73.

The RF front-end unit (RFEU) 73 performs transmission and reception signal path isolation, transmission and reception signal bandpass filtering, reception signal low noise amplification, and TDD switching, thereby providing a high power amplification unit ( The high power signal amplified at 72 is transmitted to the antenna, and the terminal signal received through the antenna is transmitted to the reception path of the transmission / reception unit 71.

The Network Interface Switch Unit (NISU) 80 includes an Ethernet L2 switch 81 for internal and external communication of a base station, and includes an external Ethernet interface and other additions with a control station. Provides an Ethernet interface to the device. In addition, the network interface switch unit 80 performs a function of collecting a hardware alarm for the lower block and reporting it to the main control and clock unit 50 as the upper unit.

The repeater interface unit (RIFU) 90 performs a function of providing an uplink / downlink interface path between the digital channel card unit 60 and the repeater. That is, it receives a digital IF signal from the digital channel card unit 60, converts it to an analog IF signal (UP Converting) and transmits it to the repeater through the repeater interface (I / F), and receives the analog from the repeater through the repeater interface. The IF signal is converted to a digital IF signal (down converting) and transmitted to the digital channel card unit 60.

Meanwhile, the digital data transmitted from the first channel card 61 to the third channel card 63 of the digital channel card unit 60 to the transmission / reception unit 71 or the repeater interface unit 90 are different from each other. It may have a transmission delay characteristic, and therefore, it is necessary to synchronize the respective digital data processed in the transmission / reception unit 71 or the repeater interface unit 90.

To this end, the first to third sampling clock signals output from the first channel card 61 to the third channel card 63 are respectively the first clock signal determination unit 31 of the clock determination means 30. To the third clock signal determination unit 33, the first clock signal determination unit 31 to the third clock signal determination unit 33 determines whether the input sampling clock signal is normal and accordingly the first The sensing signal to the third sensing signal are transmitted to the clock selector 40. The clock selector 40 checks whether the first to third sampling clock signals are normal by the first to third sensing signals, and references a sampling clock signal having a high priority among normal sampling clock signals. A sampling clock signal is selected and transmitted to the transmission / reception unit 71 and the repeater interface unit 90, and the transmission / reception unit 71 or the repeater interface unit 90 is configured to synchronize digital data by the transmitted reference sampling clock signal. Will be.

6 shows a configuration of the repeater interface unit 90 synchronized by the reference sampling clock signal, and receives digital data signals output from the first channel card 61 through the third channel card 63, respectively. First digital-to-analog converting the outputs of the first to parallel converters 91 to the third to parallel converters 93 and the first to parallel converters 91 to the third to parallel converters 93. A converter 96 to a third digital-to-analog converter 98. The analog signals converted by the first digital to analog converter 96 to the third digital to analog converter 98 are combined by a combiner through a frequency mixer and a band pass filter, respectively, and then output as a 3FA analog signal. At this time, if the synchronization of each analog signal input to the combiner does not match, it is impossible to output the 3FA analog signal including the correct information.

Accordingly, the reference sampling clock signal output from the clock selector 40 is converted into the first to parallel converter 91 to the third to parallel converter 93 and the first to analog converter 96 to the third digital /. Applied to analog converter 98 to synchronize the synchronization of the digital data signal. When the synchronization of the digital data signal is matched as described above, the synchronization of each analog signal input to the combiner is matched, so that the 3FA analog signal output from the combiner may include accurate information.

Although the present invention has been described in detail with reference to preferred embodiments, it will be apparent to those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. The embodiments are to be understood in all respects as illustrative and not restrictive.

In addition, the scope of the present invention is specified by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention. Should be interpreted as

According to the present invention, a digital data signal output from different channel cards is continuously monitored by using a sampling clock signal provided by the at least two channel cards and using a normal sampling clock signal having a high priority as a reference sampling clock signal. It has the effect of keeping the synchronous and stable communication.

In addition, according to the present invention, there is an effect that can be very easily applied to a variety of boards that directly interface with the repeater interface board or channel card of the wireless communication system.

Claims (16)

An apparatus for selecting a sampling clock signal in a wireless communication system, Clock determination means for receiving sampling clock signals transmitted from two or more channel cards, determining whether each sampling clock signal is normal, and outputting a detection signal for whether the corresponding sampling clock signal is normal; The detection signal output from the clock determination means is input to check whether the sampling clock signal is normal or not according to a given priority, and a sampling clock signal having a higher priority among normal sampling clock signals is selected as a reference sampling clock signal. A clock selector for outputting The clock selector, When a sampling clock signal having a higher priority than the sampling clock signal output as the reference sampling clock signal is normally input, the sampling clock signal having a higher priority is output as a reference sampling clock signal. Sampling clock signal selector. The method of claim 1, The clock determination means, And two or more clock signal determination units for receiving sampling clock signals transmitted from two or more channel cards, determining whether each sampling clock signal is normal, and outputting a detection signal for whether the corresponding sampling clock signal is normal. A sampling clock signal selection device in a wireless communication system. delete The method according to claim 1 or 2, The clock determination means, And a digital programming phase-locked loop (DPPLL) for determining whether the sampling clock signal is normal by determining whether the input signal transmitted from the channel card and the normal sampling clock signal match each other. Sampling clock signal selector. The method according to claim 1 or 2, The clock determination means, A sampling clock signal selection device in a wireless communication system, characterized in that it performs at least one of frequency synthesis, phase shift, and operation reconfiguration. As a base station in a wireless communication system, A digital channel card unit for receiving and processing digital IF signals received from a transmission / reception unit or repeater interface unit and transmitting the processed digital IF signals to the transmission / reception unit or repeater interface unit; A transceiving unit for converting and outputting a digital IF signal transmitted from the digital channel card unit to an RF signal, and converting the received RF signal into a digital IF signal and transmitting the digital IF signal to the digital channel card unit; A repeater interface unit which converts and outputs the digital IF signal received from the digital channel card unit into an analog IF signal, converts the received analog IF signal into a digital IF signal and transmits the digital IF signal to the digital channel card unit; Clock determination means for receiving a sampling clock signal transmitted from the digital channel card unit, determining whether each sampling clock signal is normal, and outputting a detection signal for whether the sampling clock signal is normal; And Receiving the detection signal output from the clock determination means to check whether the sampling clock signal is normal, and selects one of the normal sampling clock signal and transmits it to the transmission / reception unit and / or repeater interface unit as a reference sampling clock signal. A clock selector, The clock selector, And a sampling clock signal having a higher priority than the sampling clock signal outputted as the reference sampling clock signal is outputted as a reference sampling clock signal. The method of claim 6, The digital channel card unit, A first channel card for outputting a first sampling clock signal, a second channel card for outputting a second sampling clock signal, and a third channel card for outputting a third sampling clock signal, The clock determination means, A first clock signal determination unit configured to receive a first sampling clock signal output from the first channel card to determine whether the first sampling clock signal is normal, and to output a first detection signal for whether the first sampling clock signal is normal; A second clock signal determination unit receiving a second sampling clock signal output from the second channel card to determine whether it is normal and outputting a second detection signal for whether the second sampling clock signal is normal; And And a third clock signal determination unit configured to receive a third sampling clock signal output from the third channel card to determine whether the third sampling clock signal is normal, and to output a third detection signal for whether the third sampling clock signal is normal. Base station in wireless communication system. The method of claim 7, wherein The first clock signal determiner to the third clock signal determiner, each of the base station in the wireless communication system, characterized in that whether the sampling clock signal is normal by using a Digital Programming Phase-Locked Loop (DPPLL). delete A method of selecting a sampling clock signal in a wireless communication system, (a-1) receiving a sampling clock signal transmitted from two or more channel cards; (a-2) determining whether or not each sampling clock signal input from the channel card is normal; And (a-3) outputting one reference sampling clock signal selected by a preset reference among the normal sampling clock signals, When a sampling clock signal having a higher priority than the sampling clock signal output as the reference sampling clock signal is normally input, the sampling clock signal having a higher priority is output as a reference sampling clock signal. How to select a sampling clock signal. The method of claim 10, wherein step (a-3), In the wireless communication system, a sampling clock signal having a higher priority among the normal sampling clock signals is output as a reference sampling clock signal based on the priority given to the sampling clock signals transmitted from the two or more channel cards. How to select a sampling clock signal. delete The method according to claim 10 or 11, wherein The determination of whether the sampling clock signal is normal is performed by using a digital programming phase-locked loop (DPPLL) to determine whether the input signal transmitted from the channel card and the normal sampling clock signal match each other. How to select a clock signal. A method of selecting a sampling clock signal in a wireless communication system, (b-1) receiving a sampling clock signal of the first channel card to the third channel card to determine whether it is normal; (b-2) selecting a sampling clock signal output from the first channel card when the sampling clock signal of the first channel card is normal; (b-3) selecting a sampling clock signal output from the second channel card when the sampling clock signal of the first channel card is not normal and the sampling clock signal of the second channel card is normal; (b-4) selecting sampling clock signals of the third channel card when the sampling clock signals of the first channel card and the second channel card are not normal; And (b-5) outputting the selected sampling clock signal as a reference sampling clock signal, In the step (b-3), When the sampling clock signal of the first channel card is normally input, the sampling clock signal of the first channel card is selected instead of the sampling clock signal output from the second channel card. How to choose. delete The method of claim 14, wherein in step (b-4), In the wireless communication system, when the sampling clock signal of the first channel card or the second channel card is normally input, the channel card sampling clock signal having a higher priority is selected instead of the sampling clock signal output from the third channel card. Sampling clock signal selection method.

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