KR100779478B1 - Semiconductor device, radio terminal and radio communication unit - Google Patents

Abstract

A first analog circuit 53 adapted to first performance and a second analog circuit 55 for realizing a second performance higher than the first performance by cooperating with the first analog circuit, wherein the first performance is required. When the first analog circuit is operated, the power supply to the second analog circuit is cut off, and when the second performance is required, the first analog circuit and the second analog circuit are operated together so that the first analog circuit is operated. Sharing circuits allows the circuit characteristics to be properly switched according to the required performance, while suppressing the increase in circuit scale.

Description

Semiconductor device, wireless terminal device and wireless communication device {SEMICONDUCTOR DEVICE, RADIO TERMINAL AND RADIO COMMUNICATION UNIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a wireless terminal device, and a wireless communication device, and more particularly, to a semiconductor device, a wireless terminal device, and a wireless communication device that can switch circuit characteristics.

A conventional digital wireless terminal generally includes an RF unit 80, an analog front end (AFE) unit 90, and a digital base band (DBB) unit 100 as shown in FIG. The RF unit 80 includes an antenna 81, a transmission amplifier unit 82 including a mixer, a power amplifier, and the like, a reception amplifier unit 83, and a common circuit 84, respectively.

In addition, the AFE unit 90 for converting signals from analog to digital is composed of a receiving unit and a transmitting unit, and includes a receiving filter 91, a receiving ADC (analog-to-digital converter) 92, and a transmitting DAC ( Digital-to-analog converter) 93 and filter 94 for transmission. The DBB unit 100 that performs digital signal processing has a signal processing unit 101.

The analog signal received by the antenna 81 in the radio terminal shown in FIG. 8 is amplified by the receiving amplifier section 83, and then filtered by the receiving filter 91. In addition, the filtered analog signal is converted into a digital signal by the ADC 92 and supplied to the signal processing unit 101.

The digital signal to be transmitted from the signal processing unit 101 is converted into an analog signal by the DAC 93 and then filtered by the transmission filter 94. Furthermore, after predetermined processing such as amplification is performed in the transmission amplifier, it is transmitted through the antenna 81.

Here, when a wireless terminal corresponding to two radio systems is configured, it is common to configure the circuits shown in FIG. 8 corresponding to one radio system in parallel, as shown in FIG. 9. In addition, the same code | symbol is attached | subjected to the block etc. which have the same function as the block shown in FIG. In FIG. 9, the signal processing unit 101 connected to the RF-A 80, the AFE-A 90, and the AFE-A 90 corresponds to one radio system, and the RF-B 80, AFE-B The signal processing unit 101 connected to the 90 and the AFE-B 90 correspond to the other radio system.

Moreover, as a structure of the wireless terminal corresponding to a some radio system, switching a broadband filter and a low band filter according to a radio system (for example, refer Unexamined-Japanese-Patent No. 10-224243 (patent document 1)), Changing the bandwidth by changing the sampling frequency of the digital filter (see, for example, Japanese Patent Application Laid-Open No. 2002-500490 (Patent Document 2)) and changing the filter by software switching to change the bandwidth [eg, Japan Patent Publication No. 2000-13279 (Patent Document 3)].

However, when it is comprised as shown in FIG. 9, since the number of components which comprise a wireless terminal becomes very large, the area required for component mounting increases and it becomes difficult to miniaturize a wireless terminal. In addition, the cost (part cost, etc.) required for manufacturing also increases.

As a method of reducing the number of parts and miniaturization of the wireless terminal with respect to the configuration shown in FIG. 9, a configuration in which the AFE unit and the DBB unit are common to two wireless systems is considered. However, the characteristics required for different wireless systems (attenuation characteristics of the transmit / receive filter, the operating frequency and resolution of the ADC and DAC, etc.) are different. Therefore, when sharing the AFE unit, the filter, ADC and DAC that meet the highest specifications among the wireless systems are required. It is necessary to use.

For this reason, when the circuit is shared, the system operates with more than necessary performance depending on the wireless system that actually operates, and wastes power. In addition, the wireless system that selects the attenuation characteristics of the filter may be insufficient, and the digital system requires further digital filter processing, which wastes power.

[Patent Document 1] Japanese Unexamined Patent Application Publication No. 10-224243

[Patent Document 2] Japanese Patent Publication No. 2002-500490

[Patent Document 3] Japanese Unexamined Patent Publication No. 2000-13279

This invention is made | formed in view of such a situation, Comprising: It aims at being able to switch circuit characteristics suitably according to a communication environment, while suppressing the increase of a circuit scale.

The semiconductor device of the present invention has a first analog circuit whose circuit characteristics are set to the first performance, and a second analog circuit which realizes a second performance higher than the first performance by cooperating with the first analog circuit. When performance is required, the power supply to the second analog circuit is cut off.

According to the present invention, the first performance is realized by operating the first analog circuit and simultaneously cutting off the power supply to the second analog circuit, and operating the first analog circuit and the second analog circuit together to operate the first analog circuit. 2 performance is realized. Therefore, by sharing the first analog circuit, it is possible to appropriately switch the circuit characteristics according to the required performance while suppressing the increase in the circuit scale. In addition, the power consumption can be reduced by cutting off the power supply to the analog circuit which does not need to operate according to the required performance.

In addition, according to the wireless method, in the case of the first wireless method, the first analog circuit is operated and at the same time, the power supply to the second analog circuit is cut off. In the case of the second wireless method, the first analog circuit and the second are The analog circuits may be operated together. In this case, the circuit characteristics can be appropriately switched in accordance with the performance required by the radio system.

In addition, according to the quality of the received signal in the wireless communication, operating the first analog circuit and at the same time to cut off the power supply to the second analog circuit, and to operate the first analog circuit and the second analog circuit together You can also switch the state. In this case, the circuit characteristics can be switched appropriately to improve the quality of the received signal.

1 is a block diagram showing a configuration example of a wireless terminal device to which the semiconductor device according to the first embodiment of the present invention is applied.

2 illustrates an example of filter attenuation characteristics required in another wireless scheme.

3 is a block diagram illustrating a configuration example of a filter in the first embodiment.

4 conceptually illustrates the principle of operation of the filter shown in FIG.

5 is a block diagram illustrating a configuration example of an AD converter in the first embodiment.

6 is a block diagram illustrating a configuration example of a DA converter in the first embodiment.

FIG. 7 is a diagram illustrating an example of attenuation characteristics of a filter in the second embodiment. FIG.

8 is a block diagram showing a configuration of a conventional wireless terminal.

9 is a block diagram showing the configuration of a wireless terminal corresponding to two conventional radio systems.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described based on drawing.

(1st embodiment)

1 is a block diagram showing a configuration example of a wireless terminal device to which the semiconductor device according to the first embodiment of the present invention is applied. The radio terminal device in the first embodiment switches circuit characteristics in accordance with a radio system that operates in correspondence with a plurality of radio systems (to be described below as two).

As shown in FIG. 1, the radio terminal apparatus according to the first embodiment includes an RF (Radio Frequency) unit (RF-A) 10 of a first radio system and an RF unit (RF-B) of a second radio system. 20, an AFE (Analog Front End) section 30, a DBB (Digital Base Band) section 40, and switches SW1 and SW2.

The RF-A 10 includes an antenna 11, a mixer, a power amplifier, and the like, each of which has a transmission amplifier section 12 for amplifying signals and the like, a reception amplifier section 13, and a common circuit 14. The RF-B 20 is configured in the same manner as the RF-A 10 and includes an antenna 21, a transmission amplifier section 22, a reception amplifier section 23, and a common circuit 24. The RF-A 10 and RF-B 20 perform high frequency signal processing and the like.

The AFE unit 30 includes a receiving unit and a transmitting unit, and converts an input signal between analog signals and digital signals. The receiving unit includes a receiving filter 31 for filtering the analog signals input from the RF units 10 and 20, and an AD converter for converting the filtered analog signal into a digital signal (analog-digital converter, ADC) 32. In addition, the transmitting unit filters the DA signal (digital-analog converter, DAC) 33 for transmission that converts the digital signal input from the DBB unit 40 into an analog signal, and performs a filter process on the analog signal obtained by DA conversion. A transmission filter 34 is provided.

Here, although the details will be described later, the reception filter 31, the ADC 32, the DAC 33, and the transmission filter 34 are based on circuit characteristics [filters] based on the control signal CTL supplied from the DBB unit 40. Attenuation characteristics of the 31 and 34, resolution performance of the ADC 32 and the DAC 33, and the like.

The DBB unit 40 has a signal processing unit 41 and performs digital signal processing such as baseband signal processing. The signal processor 41 outputs a control signal CTL according to the selected wireless scheme. In addition, the signal processor 41 performs a predetermined digital signal processing using the input digital signal, or outputs a digital signal obtained by digital signal processing or the like.

Next, the operation of the radio terminal apparatus according to the first embodiment will be described.

First, the DBB 40 outputs a control signal CTL to the AFE unit 30 according to the selected wireless scheme. In addition, the DBB 40 controls the switches SW1 and SW2 to enable input / output of signals between the RF-A 10 and the AFE unit 30 when the first wireless scheme is selected. Similarly, when the second radio system is selected, the DBB 40 controls the switches SW1 and SW2 to enable input and output of signals between the RF-B 20 and the AFE unit 30.

In the following, the case where the first radio system is selected will be described as an example. However, in the case where the second radio system is selected, the RF-B 20 is used in the same manner.

The analog signal received by the antenna 11 is amplified by the receiving amplifier unit 13 and supplied to the receiving filter 31 through the switch SW1. The analog signal supplied to the reception filter 31 is filtered by the reception filter 31 and then converted into an digital signal by the ADC 32 and supplied to the signal processing unit 41.

In addition, the digital signal output from the signal processor 41 is supplied to the DAC 33. The digital signal supplied to the DAC 33 is converted from the digital signal to the analog signal by the DAC 33 and then filtered by the transmission filter 34. The filtered signal is supplied to the transmission amplifier 12 through the switch SW2, and is then transmitted through the antenna 11 after predetermined processing such as amplification is performed in the transmission amplifier 12.

Next, the filters 31 and 34, the ADC 32, and the DAC 33 included in the AFE unit 30 will be described in detail.

<Filters 31 and 34>

First, the filters 31 and 34 will be described.

In the two radio systems in this embodiment, it is assumed that the attenuation characteristics of the filter as shown in FIG. 2 are required. That is, in the first radio system, as shown by the solid line RA, a fifth-order filter (low pass filter) having a cutoff frequency Fc of 7 MHz is required, and in the second radio system, a dotted line is required. As indicated by (RB), a secondary filter (low pass filter) having a cutoff frequency of 2.5 MHz is required. 2, the horizontal axis represents frequency and the vertical axis represents attenuation characteristics.

In general, the higher order filter consumes more power than the lower order filter. In terms of reducing the power consumption, the secondary filter of the second radio system is excellent, but when the filter of the second radio system is used, a signal of a frequency required in the first radio system is blocked. On the other hand, when the fifth-order filter of the first radio system is used, extra power is consumed when the second radio system is selected.

Therefore, in this embodiment, as shown in FIG. 3, the filters 31 and 34 are comprised by the 2nd characteristic filter and the 3rd characteristic filter. When the first wireless scheme is selected, the second and third tertiary characteristic filters are controlled to be used together, and when the second wireless scheme is selected, only the second characteristic filter is controlled to be used.

Here, for example, if the input of the primary filter is Vin, the output Vout1 is

Vout1 = (1 / (sRC)) × Vin

Becomes In addition, when this output is input to the same primary filter, the output Vout2 is

Vout2 = (1 / (sRC)) × Vout1 = (1 / (sRC)) × (1 / (sRC)) × Vin

Thus, secondary characteristics can be obtained. In other words, the n-th order filter can be configured by connecting the first-order filters in series. Therefore, by using the secondary characteristic filter and the tertiary characteristic filter connected in series together, the filter of 2nd + 3rd = 5th order characteristic can be implement | achieved.

3 is a diagram illustrating a configuration example of the filter 31.

In FIG. 3, reference numeral 51 is an input node of the filter 31. Reference numeral 52 is a low specification side filter part, and has a cutoff frequency Fc adjusting circuit 54 for adjusting the cutoff frequency based on the secondary characteristic filter (analog filter) 53 and the control signal CTL. Reference numeral 55 denotes a tertiary characteristic filter (analog filter), and reference numeral 56 denotes a power supply control circuit for switching whether to supply power to the tertiary characteristic filter 55 in accordance with the control signal CTL.

In addition, SW3 is a switch controlled according to the control signal CTL, and is for selectively supplying the filter output of the secondary characteristic filter 53 to the tertiary characteristic filter 55 or the bypass line BL. . SW4 is a switch controlled according to the control signal CTL, and selectively outputs the filter output of the secondary characteristic filter 53 or the filter output of the tertiary characteristic filter 55 through the bypass line BL. It is for supplying to 57.

In addition, the secondary characteristic filter 53 may be configured by connecting two primary filters in series. The third characteristic filter 55 may be configured by connecting two primary filters in series, or may be configured by connecting the primary filter and the secondary filter in series. The secondary characteristic filter 53 and the tertiary characteristic filter 55 may be operational amplifier filters or may be Gm-C filters.

4 is a view for explaining the principle of operation of the filter shown in FIG. In addition, in order to simplify description, FIG. 4 does not consider the order of a filter.

In FIG. 4, the positive input of the differential amplifier AMP1 connected to the power supply VDD is connected to the other end of the variable resistor R1, one end of which is connected to the input terminal IN, and the plus output of the first output of the switch SWA. Connected to the terminal.

One end of the capacitor C1, one end of the variable resistor R2 and the first terminal of the switch SWC are connected to an interconnection point of the positive input of the differential amplifier AMP1 and the other end of the variable resistor R1. The other end of the capacitor C1 and the other end of the variable resistor R2 are connected to the interconnection point of the positive output of the differential amplifier AMP1 and the first terminal of the switch SWA.

As described above, the filter circuit of the previous stage is constituted by the differential amplifier AMP1, the capacitor C1, and the variable resistor R2, which are connected to the secondary characteristic filter 53 shown in FIG. Corresponding. Further, the cutoff frequency is adjusted by controlling the resistance of the variable resistor R2 in response to the variable resistor R2 corresponding to the cutoff frequency adjusting circuit 54.

In addition, the positive input of the differential amplifier AMP2 connected to the power supply VDD via the MOS transistor T1 (P channel type or N channel type), to which the control signal SC is supplied to the gate, is connected to the switch SWA. Is connected to the third terminal, and the positive output is connected to the third terminal of the switch SWB.

One end of the capacitor C2 and one end of the resistor R3 are connected to an interconnection point of the positive input of the differential amplifier AMP2 and the third terminal of the switch SWA, and the positive output of the differential amplifier AMP2 and the switch SWB. The other end of the capacitor C2 and the other end of the resistor R3 are connected to the interconnection point of the third terminal.

Here, as described above, the rear end filter circuit is constituted by the differential amplifier AMP2, the capacitor C2, and the resistor R3, which corresponds to the tertiary characteristic filter 55 shown in FIG. 3 and the transistor T1. ) Corresponds to the power supply control circuit 56.

The second terminal of the switch SWA is connected to one end of the bypass line BL, and the second terminal of the switch SWB is connected to the other end of the bypass line BL. The first terminal of the switch SWB is connected to the output terminal OUT. In addition, one end of the resistor R4 is connected to the second terminal of the switch SWC, and the other end thereof is connected to the first terminal of the switch SWB via the switch SWD.

4, only the positive input side and the positive output side circuits of the differential amplifiers AMP1 and AMP2 are shown, but the negative input side and the negative output side are similarly configured.

In the circuit shown in FIG. 4, when only the filter circuit of the preceding stage constituted by the differential amplifier AMP1, the capacitor C1 and the variable resistor R2 is operated, the switches SWA and SWB are connected to the first terminal and the second terminal. The terminals are connected, and the switches SWC and SWD are controlled to open. Accordingly, the signal input from the input terminal Vin is output from the output terminal OUT through the bypass line BL after filter processing is performed in the filter circuit of the previous stage.

At this time, the transistor T1 is turned off by the control signal SC. Accordingly, the rear filter circuit constituted by the differential amplifier AMP2, the capacitor C2, and the resistor R3 is not supplied with power, thereby preventing power consumption.

On the other hand, in the case of operating the filter circuit of the rear stage in addition to the filter circuit of the preceding stage, the switches SWA and SWB are connected so that the first terminal and the third terminal are connected, and the switches SWC and SWD are controlled to be closed. At this time, the transistor T1 is turned on by the control signal SC to supply power to the filter circuit of the subsequent stage. Accordingly, the signal input from the input terminal Vin is subjected to filter processing in the filter circuit of the preceding stage, and then further filtered in the filter circuit of the rear stage. The signal filtered by the filter circuit of the rear stage is output from the output terminal OUT and is fed back to the filter circuit of the preceding stage through the resistor R4.

3, the operation of the filter 31 shown in FIG. 3 will be described.

First, when the first radio system (the attenuation characteristic of the filter is the fifth order characteristic) is selected, based on the control signal CTL supplied from the signal processor 41, the output of the secondary characteristic filter 53 and the third characteristic The input of the filter 55 is connected via the switch SW3, and the output of the tertiary characteristic filter 55 and the output node 57 are connected via the switch SW4. In addition, the power supply control circuit 56 supplies power to the tertiary characteristic filter 55 according to the control signal CTL indicating that the first radio system is selected.

Accordingly, the signal input from the input node 51 is subjected to sequential filter processing by the secondary characteristic filter 53 and the tertiary characteristic filter 55, that is, the same filter processing as that of the fifth characteristic filter is performed and output. It is output from the node 57. At this time, the cutoff frequency is appropriately controlled by the cutoff frequency adjusting circuit 54.

On the other hand, when the second wireless method (the attenuation characteristic of the filter is the secondary characteristic) is selected, the output of the secondary characteristic filter 53 and the bypass line based on the control signal CTL supplied from the signal processor 41. One end of the BL is connected via the switch SW3, and the other end of the bypass line BL and the output node 57 are connected through the switch SW4. In addition, the power supply control circuit 56 cuts off the power supply to the tertiary characteristic filter 55 in accordance with the control signal CTL indicating that the second radio system is selected.

Accordingly, the signal input from the input node 51 is output from the output node 57 through the bypass line BL after the filter processing is performed by the secondary characteristic filter 53. Also at this time, the cutoff frequency is appropriately controlled by the cutoff frequency adjusting circuit 54.

As described above, both the secondary characteristic filter 53 and the tertiary characteristic filter 55 are operated when a filter having a high fifth order characteristic is required, and the secondary characteristic filter when a filter having a lower secondary characteristic is required. Only 53 is operated and the power supply to the tertiary characteristic filter 55 is cut off. Accordingly, by sharing the secondary characteristic filters 53 in two wireless systems, the increase in circuit scale can be suppressed, and the attenuation characteristics of the filters can be appropriately switched in accordance with the wireless systems. In addition, it is possible to prevent the waste of power by cutting off the power supply to the tertiary characteristic filter 55 according to the wireless method, thereby reducing the power consumption.

<ADC (32)>

Next, the ADC 32 will be described.

In the following description, it is assumed that the performance of 10 bits is required in the first radio system and the performance of 8 bits is required in the second radio system.

5 is a diagram illustrating a configuration example of the ADC 32 employing a pipeline system.

As shown in Fig. 5, the ADC 32 includes 1.5 bits of AD conversion circuit 60- _i (i is subscript, i = 1, 2, ..., 10) and AD conversion circuit 60- _i . Addition circuits 61- _j (j are subscripts) provided corresponding to (i = 2 to 9), respectively, and have j = 1, 2, ..., 9 and a power supply control circuit 62. FIG.

The AD conversion circuit 60- _i is cascaded, compares the reference voltage with the input input voltage, determines digital data (1 bit), outputs it to the corresponding addition circuit 61- _j , and the residuals. The signal is output to the AD conversion circuit 60- _i connected to the next stage. Adder circuit 61- _j is also cascaded, adds the digital data supplied from AD converter circuit 60- _i by appropriately bit shifting the digital data from adder circuit 61- _{j in the preceding stage} and adds the addition result. It outputs to the addition circuit 61- _j connected to the next stage. In addition, the power control circuit 62 switches whether or not the power to the AD conversion circuit _{(60-9, 60-10)} in response to a control signal (CTL) supplied.

Next, the operation of the ADC 32 will be described.

The first wireless system (10-bit) If selected, the power supply control circuit 62 includes a signal processing section 41 in accordance with a first wireless system and a control signal (CTL) indicating the selected effect supplied from the AD conversion circuit (60 _{- 9} , 60 _-10 ). That is, power is supplied to all AD conversion circuits _60-1 to _60-10 .

AD conversion circuits (60 _{- 1)} is compared to a voltage with a reference voltage of an input analog signal (AI) determining the value of the most significant bit (MSB) of the digital data and outputs it to the adder circuit _(61-1). Furthermore, AD conversion circuit _(60-1), and outputs a residual signal to the AD conversion circuit _(60-2).

Subsequently to the addition circuit, AD conversion circuit (60 _{- 2)} to determine the bit value of the two-digit second from the top side of the digital data by comparing the voltage with a reference voltage of the residual signal from the AD conversion circuit _(60-1) At the same time the residual signal to be output to the (61 _{- 1)} and outputs it to the AD converter circuit _(60-2). The addition circuit _(61-1) is an AD conversion circuit (60 _-1), the AD conversion circuit adds the output from the _(60-2) by adding the result of the operation circuit (61 _{- 2)} bit shift output and a result from the Output

Thereafter, in the same manner, the digital data value determination by the AD conversion circuit 60- _i and the addition operation by the addition circuit 61- _j are sequentially performed to the final stage. Accordingly, the input analog signal (AI) is converted into digital data of 10-bit value is output from the adder circuit _(61-9) as a digital signal (DO10).

On the other hand, when the second radio system (8 bits) is selected, the power supply control circuit 62 according to the control signal (CTL) indicating that the second radio system supplied from the signal processor 41 is selected. _-9 , 60 _-10 )

In the same manner as in the case where the above-described first radio system is selected, the digital data value is determined by the AD conversion circuits _60-1 to _60-8 and the addition calculation is performed by the addition circuits _61-1 to _61-7 . Is performed sequentially. Accordingly, the input analog signal (AI) is converted into digital data of 8-bit value is output from the adder circuit _(61-7) as a digital signal (DO8).

The As described above, a high decomposition performance (10 bits), all the AD conversion circuit (60 _-i) [corresponding AD converter circuit _(60-1 to _60-8) and connected in series thereto to the 8 bits when the required 2 when operating the AD conversion circuit _{(60-9, 60-10)} corresponding to the bits] and, require low decomposition performance (8 bits), the sikimyeo operating the AD conversion circuit (60 _-1 to 60 _-8) AD The power supply to the conversion circuits _60-9 and _60-10 is cut off. Accordingly, it is possible to suppress the AD conversion circuit _(60-1 to _60-8), the second increase in the circuit scale common to the two radio system that operates when the low-degradation performance is requested. In addition, it is possible to appropriately switch the decomposition performance according to the wireless method, and to reduce power consumption by preventing waste of power.

In Fig. 5, the ADC 32 is configured by using a 1.5-bit AD conversion circuit. However, the ADC 32 is not limited to the 1.5-bit AD conversion circuit, and is 2.5 bits depending on the intended use (power consumption, conversion time, etc.). May be configured using an AD conversion circuit or a 3.5-bit AD conversion circuit. In addition, the ADC 32 may be configured by mixing AD conversion circuits having different numbers of bits.

<DAC (33)>

Next, the DAC 33 will be described.

In the following description, it is assumed that 13 bits of performance are required in the first radio system and 11 bits of performance are required in the second radio system.

Fig. 6 is a diagram showing an example of the configuration of the DAC 33 of the current addition type.

As shown in Fig. 6, the DAC 33 is a current source 70- _k (k is a subscript, k = 1, 2, ..., 13) and two terminals provided corresponding to the current source 70- _k , respectively. The switch 71- _k , the I / V (current-voltage) conversion circuit 73, the gain control circuit 74, the input circuit 72, and the power supply control circuit 75 are provided.

The current sources 70- _k respectively supply currents of ^{I a} x 2- ^(k-1) . One terminal of the switches 71- _k is connected to the current source 70- _k , and the other terminal is commonly connected to the I / V conversion circuit 73. The I / V conversion circuit 73 converts the current supplied from the current source 70- _k through a switch 71- _k into a voltage and outputs it. The gain control of this I / V conversion circuit 73 is performed by the gain control circuit 74 in accordance with the control signal CTL.

The input circuit 72 performs open / close control of the switches 71- _k based on the input digital signal DI. For example, when the value of the least significant bit LSB of the input digital signal is " 1 &quot;, the switches _71-13 are closed, and when " O &quot;, the switches _71-13 are opened. Similarly, when the value of the 10th bit from the lower side of the input digital signal is " 1 &quot;, the switches _71-4 are closed, and when " O &quot;, the switches _71-4 are opened.

In addition, the power control circuit 75 switches whether or not the power to the current sources _{(70-1, 70-2)} supply. Specifically, when the first radio system (13 bits) is selected, the power supply control circuit 75 supplies the current source 70 in accordance with the control signal CTL indicating that the first radio system supplied from the signal processor 41 is selected. _-1 , 70 _-2 ). On the other hand, the second wireless system (11-bit) If selected, the power supply control circuit 62 cut off the power to the current sources _{(70-1, 70-2).}

By configuring as described above, the switches 71- _k are controlled to be opened and closed based on the input digital signal DI, so that a current corresponding to the digital signal DI is supplied to the I / V conversion circuit 73. Then, current-voltage conversion is performed in the I / V conversion circuit 73, and the analog signal AO of the voltage according to the value of the digital signal DI is output. Depending on this time, the selected wireless scheme to cut off the power supply to the current source _{(70-1, 70-2).}

This makes it possible to lower the performance (8 bits) inhibit the current source (70 _-3 to 70 _{-12) of} a two way radio interface to increase the circuit scale of the operating when this request. In addition, according to the radio system, it is possible to appropriately switch circuit characteristics, and to reduce power consumption by preventing waste of power.

As described above, according to the first embodiment, the filter 31, 34, ADC 32, and DAC 33 perform a part of the analog circuit to be operated when performing communication in the second radio system. By sharing with an analog circuit operated when performing a wireless communication, the circuit characteristics can be appropriately switched in accordance with the wireless system while suppressing an increase in the circuit area. For example, the wireless terminal device can be easily miniaturized. In addition, when performing communication in the first radio system, power consumption can be reduced by interrupting the power supply to the circuit portion to be operated only when performing communication in the second radio system.

In the above description, the wireless method is selected by the user. For example, the wireless method is automatically switched at the time of standby to confirm each communication environment. It is possible to switch automatically.

In the above description, the case of the two radio systems has been described as an example, but the present invention is not limited to the two radio systems, but can be applied even when the plurality of radio systems are supported.

(2nd embodiment)

Next, a second embodiment will be described.

The wireless terminal device to which the semiconductor device according to the second embodiment of the present invention is applied switches circuit characteristics in accordance with a communication environment (quality of a received signal or the like). In addition, since the whole structure of the radio terminal apparatus in 2nd Embodiment of this invention differs only in having one RF part, and is the same as that of the radio terminal apparatus in 1st Embodiment, description is abbreviate | omitted.

In the wireless terminal device, communication characteristics change according to the communication environment. For example, there are regions where the radio wave environment is relatively close to the base station, and on the other hand, regions where the radio wave environment is bad, such as an area far from the base station. In a region where the radio wave environment is poor, a desired signal level due to communication is lowered, and a portion of the noise in the received signal is larger than that in a region where the radio wave environment is good, thereby degrading the quality of the received signal. In some cases, it may cause a situation of channel disconnection.

Therefore, in the second embodiment of the present invention, the attenuation characteristic of the fourth-order characteristic filter as shown by, for example, the dotted line RB 'in FIG. 7 is required for the wireless terminal device, and 6 as the resolution of the ADC 32. If a bit is required, by a filter having a higher order attenuation characteristic than the fourth order (e.g., a filter of fifth order) adjusted so that the cutoff frequency Fc as indicated by the solid line RA 'in Fig. 7 is not changed in advance. The ADC 32 is configured by an ADC (e.g., an ADC having a resolution of 8 bits) having a resolution higher than 6 bits (more bits) while configuring the filter 31.

The filter 31 and the ADC 32 may be configured in the same manner as in the first embodiment described above. That is, the filter 31 may make it possible to connect the 4th characteristic filter and the 1st characteristic filter in series, and the ADC 32 may make it possible to connect the 6-bit AD conversion circuit and the 2-bit AD conversion circuit in series. .

In normal operation, the filter 31 operates the fourth-order characteristic filter, and the ADC 32 operates only the 6-bit AD conversion circuit. At this time, the primary filter corresponding to the fifth part of the filter 31 and the two-bit AD conversion circuit corresponding to the seventh and eighth bit parts of the ADC 32 prevent waste of power. The power supply is cut off for this purpose.

On the other hand, when the quality of the received signal is degraded due to deterioration of the communication environment or the like, the filter 31 operates the quaternary characteristic filter and the primary characteristic filter together. In other words, the filter 31 is used as a fifth-order filter so that the attenuation characteristic of the filter is sharp. In this way, the quality of the received signal can be improved by reducing noise by preventing interference by other signals, for example, signals of other users.

In addition, the ADC 32 operates all AD conversion circuits for 8 bits. As a result, the quality of the received signal can be improved by increasing the resolution of the ADC 32 and utilizing the information of the part which was normally discarded (in the present embodiment, the seventh and eighth bits).

Here, the degradation of the quality of the received signal can be detected by measuring the signal level of the received signal, bit error rate (BER) or signal to noise ratio (S / N ratio). The signal level of the received signal can be detected by the receive amplifier section of the RF section shown in FIG. 1, the BER can be detected by the DBB section having an error correction decoding function, and the S / N ratio can be detected by the RF section. Can be.

As described above, according to the second embodiment, the circuit characteristics are controlled by adaptively controlling the order of the filter 31 (the attenuation characteristic of the filter 31) and the resolution of the ADC 32 to the minimum necessary according to the quality of the received signal. By switching and improving the quality of a received signal, stable communication can be performed even in a bad communication environment. In addition, according to the quality of the received signal, power consumption can be reduced by cutting off the power supply to the circuit which does not need to operate in the filter 31 and the ADC 32. For example, in the case of a battery operated wireless terminal device, talk time or standby time can be increased.

In addition, the structure of the filter 31,34, ADC32, and DAC33 demonstrated in 1st and 2nd embodiment mentioned above is an example, and the orders of the filter 31,34, ADC32, and DAC The decomposition performance of (33) is arbitrary. These performance values may be appropriately determined according to the corresponding radio system, communication environment, or the like, and the filters 31, 34, ADC 32, and DAC 33 may be configured in the same manner as described above.

In addition, all the said embodiment only showed an example of embodiment in implementing this invention, and the technical scope of this invention should not be interpreted limitedly by these. That is, this invention can be implemented in various forms, without deviating from the technical idea or its main characteristic.

As described above, according to the present invention, a power supply is supplied to a second analog circuit which realizes a second performance higher than the first performance by operating a first analog circuit adapted to the first performance and cooperating with the first analog circuit. The first performance is realized by cutting off the circuit, and the second performance is realized by operating the first analog circuit and the second analog circuit together. Accordingly, by sharing the first analog circuit, the circuit characteristics can be appropriately switched in accordance with the required performance while suppressing an increase in the circuit scale, and the size can be easily reduced. In addition, power consumption can be reduced by cutting off the power supply to an analog circuit that does not need to be operated.

Claims (16)

A first analog circuit whose circuit characteristics are adapted to the first performance, A second analog circuit which realizes a second performance higher than the first performance by cooperating with the first analog circuit and cuts off power supply when the first performance is required. A semiconductor device comprising a. The power supply control circuit according to claim 1, wherein the power supply to the second analog circuit is cut off when the first performance is required, and the power supply is supplied to the second analog circuit when the second performance is required. The semiconductor device further comprises. The semiconductor device according to claim 1, wherein said first and second analog circuits are filters. delete delete The semiconductor device according to claim 1, wherein said first and second analog circuits are AD converters. delete The semiconductor device according to claim 1, wherein said first and second analog circuits are DA converters. delete 2. The apparatus of claim 1, wherein the first and second analog circuits comprise a filter, an AD converter, and a DA converter, The filter is composed of a first filter and a second filter which can be connected in series. The AD converter includes a first AD converter and a second AD converter connected in series, The DA converter includes a first DA converter and a second DA converter having common output connections. And the power supply to the second analog filter, the second AD converter, and the second DA converter is cut off when the first performance is required. A semiconductor device used for receiving both a signal of a first radio system requiring a first performance and a signal of a signal of a second radio system requiring a second performance higher than the first performance. A first analog circuit whose circuit characteristics are adapted to said first performance, A second analog circuit which realizes said second performance by cooperating with said first analog circuit, A power supply control circuit that cuts off power supply to the second analog circuit when receiving the first wireless signal, and supplies power to the second analog circuit when receiving the second wireless signal. A semiconductor device comprising a. delete A semiconductor device used for a receiving side in wireless communication, A first analog circuit having a first performance, A second analog circuit which realizes higher performance than the first performance by cooperating with the first analog circuit, A first state that supplies power to the first analog circuit and cuts off power to the second analog circuit in accordance with the quality of the received signal in the wireless communication; and the first analog circuit and the second analog circuit. Power supply control circuit which can switch second state supplying power to both sides A semiconductor device comprising a. delete A first analog circuit adapted to circuit characteristics and adapted for signal processing according to wireless communication; A second analog circuit which performs signal processing according to wireless communication at a second performance higher than the first performance by cooperating with the first analog circuit and cuts off power supply when the first performance is required Wireless terminal device comprising a. A radio communication device having a high frequency unit performing high frequency signal processing, an analog processing unit performing analog signal processing, and a baseband processing unit performing baseband signal processing, wherein the analog processing unit includes: A first analog circuit having circuit characteristics having a first performance, A second analog circuit which realizes a second performance higher than the first performance by cooperating with the first analog circuit and cuts off power supply when the first performance is required. Wireless communication device comprising a.

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