KR100779014B1 - Method of designing hardware based on a systemc - Google Patents

Abstract

The present invention shortens the development period by designing hardware based on the system, and separating the JPEG-2000 system designed by the C function into a software module and a hardware module, and forming a channel for communication between the software module and the hardware module. Step of applying a master library to a software module, applying a slave library to a hardware module, and designing and synthesizing a hardware module designed as a C function as a behavioral SystemC. Forming a possible hardware module, and compiling a synthesizable hardware module with a SystemC compiler. In this way, by reusing the JPEC-2000 coding system designed in C language, designing the hardware based on the system seed can shorten the product development time, and cosimulation is possible during the development through the integrated design of the hardware and software.

Software, hardware, cosimulation, synthesis, system

Description

Design method of hardware based on system Mr. {METHOD OF DESIGNING HARDWARE BASED ON A SYSTEMC}

1 is a flowchart of a JPEG-2000 encoding system designed by a software algorithm according to an embodiment of the present invention.

2 is a block diagram of a JPEG-2000 encoding system at an untime level according to an embodiment of the present invention.

3 is a block diagram of a system C model of a synthetic MQ coder according to one embodiment of the invention.

4 is a flowchart for verifying a JPEG-2000 encoding system according to an embodiment of the present invention.

The present invention relates to a method of designing hardware based on system seed, and more particularly, to a method of designing hardware in a JPEG-2000 encoding system.

JPEG-2000 is a next-generation still image standard that integrates various functions in the existing JPEG, and is standardized in particular by the International Telecommunication Union ITU-RSG8 and ISO, IEC, JTC1, SC29 and WG1. This gives a single unified code to various types of still images with different characteristics such as natural image, scientific image, medical image, remote sensing image, document image, and graphic image.

These JPEG-2000s include medical images, remote sensing, image storage, graphics and computer composite images, facsimile, printed and published images, laser printing, digital cameras, scanners and digital copiers, economic documents, security cameras, earth image processing, It can be used in various fields such as digital library of photographs and artworks, camera phones, and all related fields.

The JPEG-2000 encoding system is designed as a C-model by a software developer.

The JPEG-2000 encoding system performs a tiling operation of appropriately dividing an image using a programming language, and performs encoding on the divided image. Next, modeling is performed to design hardware (HW) of the encoding system of JPEC-2000.

The hardware developer then rewrites the VHDL or Verilog at the register transfer level (RTL) along the ASIC design flow based on the software system.

On the other hand, since the rewriting of the program for hardware design is performed by the designer's manual operation, it is easy to cause an error in the system.

In addition, co-simulation during development is difficult because software (SW) developers and hardware developers must develop systems with different levels of testbenches by developing in different languages. . Because of this, conventional system verification occurs after hardware development is completed.

Cosimulation is a synchronization of software simulation and hardware emulation, which aims to make the pure software simulation process and the pure emulation acceleration process independent of very large functional blocks.

If an error occurs during the co-simulation process, the hardware designer has to restart the hardware design from the beginning and the development period is long.

Therefore, the technical problem of the present invention is to shorten the development period by designing hardware based on the system.

A method of designing hardware based on the system of the present invention, comprising: separating a JPEG-2000 system designed with a C function into a software module and a hardware module, and forming a channel for communication between the software module and the hardware module. Applying a master library to the software module, applying a slave library to the hardware module, and designing the hardware module designed by the C function as a behavioral system C. Forming a synthesizable hardware module, and compiling the synthesizable hardware module with a system C compiler.

The channel may be based on SystemC, which is formed through a SystemC wrapper.

The system C wrapper may be formed by a full handshake method of the master and the slave libraries.

The software module may be based on a system that controls the operation of the hardware module through request and ack signals.

Signals transmitted and received between the software module and the hardware module may be defined and used in a class form of an object-oriented C language.

The synthesizable hardware module forming step may include dividing the hardware module designed as the C function into an independent module, a memory interface, and a memory, declaring a first port for data transfer between the independent module and the memory interface; Declaring a second port for data transfer between the memory interface and the memory.

The first port and the second port may be designated based on the channel.

Data transfer between the independent modules can be transferred by creating a third port using a binary variable.

When transferring data between the independent modules using global variables stored in the memory, data may be transferred by accessing the memory through the memory interface.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a method of designing hardware based on the system C according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4.

1 is a flowchart of a JPEG-2000 encoding system designed by a software algorithm according to an embodiment of the present invention, and FIG. 2 is a JPEG-2000 encoding system at an untime level according to an embodiment of the present invention. 3 is a block diagram of a system C model of an MQ coder synthesized at a bus accurate level according to an embodiment of the present invention, and FIG. 4 is an embodiment of the present invention. Is a flowchart for verifying a JPEG-2000 encoding system according to the present invention.

As shown in FIG. 1, a JPEG-2000 encoding system 90 designed as a C-model identifies an image of a clear model of a semiconductor circuit (S10), and image tiling that appropriately divides the image. tiling) (S20), digitize the divided image, add a header to each image packet (S30), and pass it to a discrete wavelet transform to transfer the image to time (t ) Generates a signal having locality with respect to the frequency f) (S40), and generates values of CX (context), D (decision), and probability table (Qe) through a block coding process. (S50), compresses the image data by passing the CX (context), D (decision) and probability table (Qe) values to the MQ coder (S60), and the compressed image data is passed to Tier2, one code After the block has been processed, the packet plus the data termination code. Generating a next (S70), the list image data to the bit (bit) unit is composed of (S80) of forming a C function, the image data bit stream (bit stream). Here, the compressed image data is represented by 0 or 1 and stored in units of 1 byte.

Then, to design hardware based on SystemC-model by reusing JPEG-2000 made by C-model, as shown in FIG. 2, the existing C-model is replaced with a hardware module (HWM). Divide into software modules (SWMs).

The hardware module (HWM) in the present invention includes an MQ coder (S60) written in C-model and compresses the image data, and the software module (SWM) in the JPEG-2000 encoding system created in C-model. C functions S20, S30, S40, S50, S70, and S80 except for the hardware module (HWM) portion are included.

The software module (SWM) and the hardware module (HWM) can then be simulated simultaneously.

The software module SW performs the tasks sequentially, while the hardware module HW processes all the modules included in the hardware at the same time.

Therefore, a SystemC wrapper is designed to generate channels ch1 and ch2 for communication between the software module SWM and the hardware module HWM. The master library is used for the software module (SWM) and the slave library is used for the hardware module (HWM) for the sequential processing of the JPEG-2000 encoding system. This is a method for hardware simulation of the part performed by the MQ coder, which is a hardware module (HWM), through a call to the C function. A signal requesting the operation of the hardware module (HW), which is a slave, is a software module (SW), which is a master. Data can be processed sequentially by controlling through (request signal, req) and acknowledgment signal (acck). For this reason, System Sea wrappers can be created using the full-handshake method of master and slave libraries.

Signals transmitted and received between the hardware module (HWM) and the software module (SWM) are defined in the form of a class of object-oriented C language.

Subsequently, whether communication between the software module (SWM) and the hardware module (HWM) is confirmed by performing a simulation at an untimed level.

Then, as shown in FIG. 3, the MQ coder 700 is designed at a bus accurate level by a system that can be applied to hardware by reusing the C language used to design the MQ coder. Form a synthesizeable MQ coder 700.

First, the C module of the MQ coder written in the C function is included in the MQ module 145, the memory interface 140, and the memory 150, 155, which the hardware module (HWM) includes. 160, 165).

The MQ module 145 includes the mqc_init_enc module 100 for initializing the MQ coder 700 internal variables, and the mqc_reset module for resetting the MQ coder 700 internal variables when a reset signal enters the MQ coder 700. (105), the mqc_encode module 110 for encoding the input data, the mqc_renorme module 115 for redefining and encoding the probability table (Qe) values, the mqc_setcurctx module 120 for encoding the data, and the encoded output by 1 byte. Mqc_byteout module 125 for processing, mqc_flush module 130 for generating a termination signal when the encoding operation for all data input to the MQ coder 700 is completed, and mqc_bytelength for calculating the length of encoded data Module 135.

The memory 150, 155, 160, 165 stores global variables necessary for designing the MQ coder 700, and the memory interface 140 stores the MQ module 145 and the memory 150, 155, 160, 165 for processing data. It sends data between) to the processing site.

Then, the first ports (P1, P2, P3, P4, P5, P6, P7, P8) for communication between the MQ module 145 and the memory interface 140, the memory interface 140 and the memory (150, 155) To generate second ports P9, P10, P11, and P12 for communication between. In this case, the first and second ports P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, and P12 are channels (ch1 and ch2) generated through the above-mentioned SystemC wrapper. Make it based on

Mqc_encode module 110, mqc_renorme module 115, mqc_encode module 110, mqc_setcurctx module 120, mqc_encode module 110, mqc_byteout module 125, mqc_renorme module 115, mqc_flush module 130, mqc_byteout 130 Data transfer between module 125 and mqc_flush module 130 is accomplished by creating third ports P13, P14, P15, P16, and P17 using binary variables. On the other hand, when data is transmitted using global variables stored in the memory 150, 155, 160, 165, the data is accessed through the memory interface 140 to the memory 150, 155, 160, 165. At this time, the mqc_encode module 110, the mqc_renorme module 115, the mqc_setcurctx module 120, the mqc_byteout module 125, and the mqc_flush module 130 accessing the memory 150, 155, 160, and 165 read memory data ( Design by considering the signals necessary to read.

As the MQ coder 700 designed by System C through this design method is designed by reusing the C language, a hardware developer uses a software system based on a software system as in the prior art, and registers a VHDL of RTL (register transfer level) from the beginning. Since development is not done manually by the designer with Verilog, development time can be shortened.

In addition, since the hardware module (HWM) and software module (SWM) are integrated design, co-simulation is possible even during development.

Then, as shown in FIG. 4, the MQ coder (S200) designed at the bus accumulator level (S215) is applied to the FPGA library (S215) by the system's compiler (S210). (S230), the .db / HDL synthesized MQ coder is simulated by the FPGA compiler (S235), and the netlist result (end netlist) (S240) obtained is a FPGA chip using a board such as iPROVE. The program of the FPGA chip and the software module (SW) is downloaded to the field programmable gate array chip (S250), and the program of the software module (SWM) input to the FPGA chip and the computer is transferred through a peripheral component interconnect (PCI), which is a bus system. This input computer communication can be executed to verify that the encoding result using the JPEG-2000 C-model and the encoding result using the synthesized MQ coder match.

Therefore, by designing hardware at the software algorithm level quickly and easily without redesigning at the RTL level, the hardware can be designed faster than the existing design.

According to the present invention, it is possible to reduce the time for product development by designing hardware based on the system seed by reusing the JPEC-2000 encoding system designed in the C language.

In addition, the integrated design of the hardware and software enables cosimulation during development.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims (9)

Separating the JPEG-2000 system designed with C function into software module and hardware module, Establishing a channel for communication of the software module and the hardware module, Applying a master library to the software module, Applying a slave library to the hardware module; Designing the hardware module designed with the C function as a behavioral system C to form a synthesizeable hardware module, and Compiling the synthesizable hardware module with a SystemC compiler, The channel is a hardware design method based on System C formed by the System C wrapper (SystemC wrapper). delete In claim 1, The system seed wrapper is based on a system seed formed by a full handshake method of the master and the slave library. In claim 1, System based on the software module controlling the operation of the hardware module through a request and ack signals. In claim 1, A system design method based on a system used to define and use the signals transmitted and received between the software module and the hardware module in the form of a class of object-oriented C language. In claim 1, The synthesizable hardware module forming step, Dividing the hardware module designed by the C function into an independent module, a memory interface, and a memory; Declaring a first port for data transfer between the independent module and the memory interface, Declaring a second port for data transfer between the memory interface and the memory Hardware design method based on the system Mr. including. In claim 6, And the first port and the second port are system based designations based on the channel. In claim 6, Data transfer between the independent modules is based on the system Mr. system for transferring by creating a third port using a binary (binary) variable. In claim 8,. The system design method based on the system for transferring data by accessing the memory through the memory interface when the data rule between the independent modules using the global variable stored in the memory.

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