KR100778876B1 - Device for Detecting Auto baudrate and Method for the same - Google Patents

Abstract

The present invention separately configures a counter for checking a transmission time of a start bit signal of a transmitted data and a subsequent 0 bit signal, and performs data transmission / reception using the transmission time of the two bit signals as a reference for auto baud rate. An automatic baud rate detection apparatus, comprising: a receiver for receiving an input signal, an edge detector for detecting edge generation for each bit signal of the input signal, a first counter for counting the number of start bit clocks of the input signal, and A second counter for counting a clock number of zero bits transmitted following the start bit, a first register for storing a start bit clock number of the first counter and a zero bit clock number of the second counter, and the first register A first comparator for comparing the number of start bit clocks and the number of 0 bit clocks stored in the second signal; A sampling unit for sampling consecutive zero bits and subsequent consecutive bits to have a rate, a second register for storing the sampled zero bits and subsequent consecutive bits, sampled bits and an input signal stored in the second register And a second comparator for outputting an end signal upon matching.

Data Terminal Equipment (DTE), Data Communication Equipment (DCE)

Description

Device for Detecting Auto baudrate and Method for the same

1 is a block diagram showing a general data transmission scheme

FIG. 2 is a timing diagram of a transmission / reception state for performing automatic baud of the conventional “A” character.

3 is a timing diagram showing a conventional automatic baud rate detection method

Figure 4 is a timing diagram for the transmission and reception state to perform automatic boarding of the "A" character of the present invention

5 is a flowchart illustrating an automatic baud rate detection method of the present invention.

6 is a block diagram showing an automatic baud rate detection apparatus of the present invention.

Explanation of symbols for the main parts of the drawings

START BIT: Start bit STOP BIT: Stop bit

CNT1: Start bit clock CNT2: 0 bit clock

(A): Input signal (e), (bar): Polling edge

(G): Rising edge (B), (H), (D): Logic "0" section

(D), (R): Logic "1" section

61 receiver 61 edge detector                 

63: first counter 64: second counter

65: first register 66: first comparator

67: sampling unit 68: second register

69: second comparison unit

The present invention relates to data transmission and reception, and separately configures a counter for checking a transmission time of a start bit signal of a data to be transmitted and a 0 bit signal subsequent to the transmission bit of the two bit signals. The present invention relates to an automatic baud rate detection device and a detection method for transmitting and receiving data.

Hereinafter, an automatic baud rate detection apparatus and a detection method according to the related art will be described with reference to the accompanying drawings.

1 is a block diagram showing a general data transmission scheme.

As shown in FIG. 1, data transmission is performed by configuring modems 2 and 3 between the transmitter 1 and the receiver 4, respectively, to adjust the communication speeds of each other.

At this time, baud rate must be synchronized between both ends of the transmission and reception for smooth communication. The user sets the same as either of the software-determined ones, or receives the input signal from the receiving end to automatically detect the baud rate.                         

On the other hand, baud rate is a unit of bps (bit per second) and indicates how many bits per second to transmit data. This value can be transmitted and received only when the sending device and the receiving device are set to the same value.

In current data communication systems, asynchronous serial digital data is generally generated in data terminal equipment, namely Data Terminal Equipment (DTE). DTE is a personal computer.

The DTEs are connected to the public telephone network and to each other, and each DTE is connected to the telephone network through DCE (Data Communication Equipment).

Typically, DCE is a modulator / demodulator device, i.e. a device commonly referred to as a modem.

The program that drives the DTE sets the rate of bits of digital data sent to the modem. The modem must be able to receive data or command signals from any bit rate DTE. Therefore, the modem should be able to automatically recognize and adapt the bit rate of the digital signal generated by the DTE.

The process of analyzing and determining the bit rate of the signal from the DTE to the modem is called autobauding. In terminology, automatic boarding is only performed when the modem is in normal mode. For those skilled in the art, it is obvious that when the modem is in normal mode, binary data input to the modem is translated into instructions for performing a certain function.                         

Most modern high performance modems come in the form of AT command sets. The AT command format is such that each command includes the letter "AT" at the beginning and ends with a carriage return.

If the test line in between is recognized by the modem as a valid command, the command is executed by the modem and a certain result code is returned.

If the instruction is unrecognized or invalid, it is ignored and a result code is returned to the DTE indicating that the instruction cannot be executed.

The modem uses the "AT" initial character signal to determine and analyze the bit rate that holds the input digital data.

Generally, in American Standard Code for Information Interchange (ASCII) code, the encoding of the character "A" into a binary bit signal is equivalent to 1000001 (hexadecimal 41), and "T" is equal to 1010100 (54 hexadecimal 54). As such, the ASCII code represented by 7 bits transmits a parity bit to the most significant bit of the 7 bits as a 1 byte signal during data transmission.

These parity bits include even parity and even parity. Even parity is an even number of " 1 " of transmitted signals, and odd parity is an odd number. At this time, the parity bit serves to verify a signal error.

UART (Universal Asynchronous Receiver Transmitter) method, on the other hand, is a low speed but simple method of communicating between devices. In other words, UART transmits only data without sending information about clock, and transmits one character at a time in ASCII code format.

FIG. 2 is a timing diagram of a transmission / reception state for performing automatic boarding of the conventional “A” character.

As shown in Fig. 2, the input signal (A) contains an AT command, and the baud rate is the start bit (START BIT) while the information about the character "A (BIT0 to BIT7: 01000001)" is transmitted from the interval (START BIT) (b). Is determined.

The START BIT starts from the falling edge (bar) and ends with the rising edge (sa).

At this time, the 0 bit (BIT0) section (D), which is the least significant bit of "A", starts at the rising edge (bar) and ends at the falling edge (E).

3 is a timing diagram illustrating a conventional automatic baud rate detection method.

As shown in FIG. 3, the edges of the sampling area (A) and the sampling area (B), that is, the number of interval clocks between the first edge generation point C and the second edge generation point D are counted and sampled. Thus, auto baudrate is detected for a one bit signal.

In the sampling areas of (A) and (B), an edge occurs between (E) and (F), and between (G) and (H), respectively.

However, the conventional automatic baud rate detection method has the following problems.

That is, in the conventional automatic baud rate detection, only the start bit is sampled to detect the baud rate. At this time, noise may be generated after the start bit is transmitted, and an error signal may be input to the transmitted signal itself.

In addition, when the start bit itself is an error signal, the baud rate detected by using the start bit as a sampling reference is an unreliable value.

In order to solve the above problems, the present invention separately configures a counter that checks the transmission time of the start bit signal of the data transmitted and the subsequent 0 bit signal and baudrates the transmission time of the two bit signals. It is an object of the present invention to provide an automatic baud rate detection apparatus and a detection method for transmitting and receiving data based on Auto Baudrate.

In order to achieve the above object, the present invention provides an automatic baud rate detection apparatus comprising: a receiver configured to receive an input signal, an edge detector configured to detect edge generation for each bit signal of the input signal, and a start bit clock number of the input signal; A first counter to store a second counter for counting the number of clocks of 0 bits transmitted following the start bit, a first counter for storing the start bit clock number of the first counter and the number of zero bit clocks of the second counter. A register, a first comparator for comparing the number of start bit clocks and a number of zero bit clocks stored in the first register, and a series of zero bits and subsequent consecutive bits to have the same baud rate as the baud rate of the start signal. A sampling section for sampling, a second register for storing the sampled zero bits and subsequent consecutive bits, and a sampling stored in the second register And a second comparator for outputting an end signal when the bit is matched with the input signal.

In addition, the automatic baud rate detection method of the present invention includes receiving an input signal, detecting a falling edge of a start bit, counting a clock number of the start bit, and measuring a rising edge of the start bit. Detecting and ending counting of a start bit; storing a clock number of the start bit in a first register; counting a clock number of 0 bits transmitted following the start bit signal; Sampling the zero bit signal when the number of clocks has a value 1/2 of the clock number of the start bit, detecting the falling edge of the zero bit, ending the count, and counting the number of clocks of the zero bit. Storing in the first register and checking whether the number of clocks of the start bit stored in the first register and the number of clocks of the 0 bit are the same and transmitting the data if not equal. Outputting a signal, sampling the 1- to 7-bit signal and the stop bit of the same baud rate when the clock numbers of the start bit and the 0 bit are the same, and the data consisting of the 0 to 7 bit. And outputting an end signal identical to the input signal.

Hereinafter, an automatic baud rate detection apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a timing diagram for a transmission and reception state of performing automatic boarding of an "A" character of the present invention.                     

As shown in Figure 4, the automatic baudrate of the present invention is determined by counting the transmission rate of the start bit (BIT) is the same as conventional, but counting the 0 bit (BIT0) of the data signal to be transmitted The number of clocks at this time is stored, and 0 bit (BIT0) is used as the reference for automatic baud rate detection together with the start bit.

At this time, the faster the clock is used, the more accurate the baud rate can be detected.

The clock number CNT1 of the START bit is counted from zero simultaneously with the first falling edge (bar). The count is stopped at the same time as the first rising edge.

The clock number CNT2 of the 0 bit BIT0 starts counting from the point at which the counting of the start bit START BIT stops, and the ending point of the 0 bit BIT0 counts at the falling edge. Stop it.

The data to be transmitted has the same structure as the input signal (i), i.e. the start bit (START BIT) of logic "0" and the stop bit (STOP BIT) in logic "1" state, with a zero of logic "1" in between. The data signal consists of a bit BIT0, 1 bit to 5 bits (BIT1 to BIT5) of logic "0", 6 bits (BIT6) of logic "1", and even parity 7 bits (BIT7) of logic "0" to 01000001. Transmits the ASCII "A" value.

At this time, START bit section (B), 0 bit (BIT0) signal section (D), 6 bit (BIT6) section (child), and 7 bit (BIT7) section (difference) all have the same number of clocks. The interval (a) of 1 to 5 bits (BIT1 to BIT5) is equal to five times the interval (d) of the 0 bit (BIT0).

That is, by counting the number of clocks in the start bit (START BIT) and 0 bit (BIT0) interval to detect the automatic baud rate and use this as a sampling reference so that subsequent bit signals have the same clock number as the detected clock number, That is, it transmits to have the same baud rate.

The clock number CNT1 of the start bit and the clock number CNT2 of 0 bits are the same value when the transmission data is normal. If they are different, it is determined that the values are distorted during transmission.

Thus, the case where the clock number CNT1 of the start bit and the clock number CNT2 of the 0 bit are the same is ideally when data is transferred. In this case, the baud rate can be known by the relationship between the count rate and the number of clocks.

In data communication, if the baud rate is known, correct data communication can be achieved by sampling and transmitting the input signal at the baud rate by receiving the input signal.

That is, when the input signal (a) is applied to the receiver, the baud rate is already detected by the number of clocks (CNT1, CNT2) in the sections (b) and (d). You can sample it.

This sampling method is performed as follows.

The clock count of 0 bits is stopped and 1 bit after a time corresponding to half the length of the clock bit (CNT1 or CNT2) of the start bit (START BIT) or 0 bit (BIT0) starting from the falling edge (e). Start sampling (BIT1).

At this time, the sampling is performed based on the clock number CNT 1 or CNT 2 of the start bit or the 0 bit BIT0 to have the same baud rate as the start bit or the 0 bit BIT0, and the logic " 0 " Get one bit (BIT1) of.

Next, after sampling the value of one bit (BIT1) in the interval 40, and again after the time corresponding to the clock number, the value of two bits (BIT2) is sampled in the interval 41 to obtain a logic "0" low value. .

Next, the value of 2 bits (BIT2) is sampled in the section 41, and the value of 3 bits (BIT3) is sampled in the section 42 after the time corresponding to the clock number again to obtain a logic "0" value.

Next, after sampling the value of 3 bits (BIT3) in the interval 42, the value of 4 bits (BIT4) is sampled again in the interval 43 after the time corresponding to the clock number to obtain a logic "0" value.

Next, the value of 4 bits (BIT4) is sampled in the section 43, and the value of 5 bits (BIT5) is sampled in the section 44 after the time corresponding to the clock number again to obtain a logic "0" value.

Next, after sampling the value of 5 bits (BIT5) in the interval 44, the value of 6 bits (BIT6) is sampled again in the interval 45 after the time corresponding to the clock number to obtain a logic "1" value.                     

Subsequently, after sampling the value of 6 bits (BIT6) in the interval 45 and again, the value of 7 bits (BIT7) is sampled in the interval 46 after the time corresponding to the number of clocks. even parity)

Finally, after sampling the 7 bits (BIT7), the STOP BIT value of logic "1" is transmitted to complete the data transfer of "A" value.

As expected, if the “A” value is normally received, the correct baud rate is detected, which means that the verification and verification steps have been completed through one byte of data as shown in (a).

5 is a flowchart illustrating an automatic baud rate detection method of the present invention.

As shown in FIG. 5, the automatic baud rate detection method is performed in the following manner.

First, an input signal INPUT to be transmitted to a transmitter is received through a modem (or a receiver) (501S).

The falling edge of the start bit START BIT of the input signal INPUT is detected through the edge detector 502S.

The clock number CNT1 of the start bit START BIT is counted (503S).

The rising edge, which is the end point of the START bit, is detected and the count of the start bit is terminated (504S).

The clock number CNT1 of the start bit is stored in the first register, and the clock number CNT2 of the 0 bit BIT0 transmitted following the start bit START BIT is counted (505S).                     

While increasing the number of clocks CNT2 to 0 bits BIT0 until the clock number CNT2 of the 0 bit BIT0 has a value 1/2 of the clock number CNT1 of the start bit START BIT. Counting continues, and when the number of clock bits CNT1 of the start bit START BIT is equal to 506S, sampling of the zero bit BIT0 is started (508S).

Counting is terminated by detecting the falling edge of bit 0 (BIT0), followed by counting of one bit (BIT1) (509S).

The clock number CNT2 of the zero bit BIT0 from which the counting is completed is stored in the first register (510S).

At this time, if the clock number CNT1 of the start bit START BIT stored in the first register and the clock number CNT2 of the 0 bit BIT0 are equal to each other (step 511S), the transmission stop signal is not equal. It outputs (522S).

When the clock number (CNT1 = CNT2) of the start bit (START BIT) and the 0 bit (BIT0) is the same, sampling the 1 to 7 bit signals (BIT1 to BIT7) and the stop bit (STOP BIT) of the same baud rate (513S, 514S).

When the data composed of the 0 to 7 bits (BIT0 to BIT7) is the same as the input signal "A", an end signal is output to confirm the detection (515S).

FIG. 6 is a block diagram illustrating a detection device implementing the automatic baud rate detection method of FIG. 5.

As shown in FIG. 6, the automatic baud rate detection apparatus includes a receiver 61 that receives an input signal, an edge detector 62 that detects edge generation for each bit signal of the input signal, and a start bit clock number of the input signal. A first counter 63 for counting, a second counter 64 for counting the number of clocks of 0 bits transmitted following the start bit, a number of start bit clocks for the first counter 63 and the second counter A first register (65) for storing the number of zero-bit clocks of (64), a first comparator (66) for comparing the number of start bit clocks and zero-bit clock numbers stored in the first register (65) A sampling unit 67 for sampling consecutive 0 bits and subsequent consecutive bits BIT0 to BIT7 to have the same baud rate as the baud rate of the start bit, and the sampled 0 and subsequent consecutive bits BIT0 to BIT7. ) A second register 68 for storing the value, and the second register 68 It is configured to include a register 68, a second comparison unit (69) for outputting a stop signal when the match stored in the sampled bit and the input signal in.

The input signal received by the receiver 61 is a binary signal and is composed of start bits, 0 to 7 bits, and stop bits.

The edge detector 62 detects both the falling edge and the rising edge.

The first comparator 66 compares the clock number CNT1 of the 0 bit BIT0 with the clock number CNT2 of the start bit START BIT, and verifies the initial failure of the data transmission.

The sampling unit 67 starts a sampling operation when the clock number CNT1 of the 0 bit BIT0 is 1/2 of the clock number CNT2 of the START bit. The clock number CNT2 of the 0 bit BIT0 obtained through the initial sampling of the sampling unit 67 is used as a reference for automatic baud rate detection along with the clock number CNT1 of the start bit START BIT.

The sampled zero bits and subsequent consecutive bits BIT0 to BIT7 stored in the second register 68 are the data to be transferred.

The start bit is characterized in that it operates on the falling edge and ends with the rising edge.

The 0 bit BIT0 operates on the rising edge and ends with the falling edge.

The second register 68 is configured as an 8-bit register to store 7 bits (BIT1 to BIT7) of data which are sequentially transmitted after the initial 0 bit (BIT0).

The second comparison section 69 is a comparison section that checks whether the 1 to 7 bits (BIT1 to BIT7) are equal to the clock number of the start bit (START BIT) or the 0 bit (BIT0), respectively.

The automatic baud rate detection apparatus and method according to the present invention has the following effects.

First, it is necessary to complement the part that communication was possible only when the baud rate is promised at a specific value between the two ends of the conventional transmission and reception. Can be implemented to

Second, an input signal of "AT" character is sent, received, and analyzed to inform the baud rate at the beginning of data communication, so that the baud rate can be determined, verified and verified.

Claims (11)

A receiver for receiving an input signal; An edge detector which detects edge generation for each bit signal of the input signal; A first counter for counting a start bit clock number of the input signal; A second counter for counting a clock number of 0 bits transmitted following the start bit; A first register for storing the start bit clock number of the first counter and the zero bit clock number of the second counter; A first comparison unit comparing the number of start bit clocks and the number of zero bit clocks stored in the first register; A sampling unit for sampling consecutive 0 bits and subsequent consecutive bits to have the same baud rate as the baud rate of the start bit; A second register for storing the sampled zero bits and subsequent consecutive bits; And a second comparator for outputting an end signal when the sampled bit stored in the second register and the input signal match each other. The apparatus of claim 1, wherein the input signal is a binary signal comprising a start bit, 0 to 7 bits, and a stop bit. The automatic baud rate detection apparatus of claim 1, wherein the edge detector detects both a falling edge and a rising edge. The automatic baud rate detection apparatus according to claim 1, wherein the first comparator verifies an initial failure of data transmission while comparing a clock number of 0 bits and a clock number of a start bit. The automatic baud rate detection apparatus of claim 1, wherein the sampling unit operates when the number of clocks of 0 bits is 1/2 of the number of start bit clocks. The automatic baud rate detection apparatus according to claim 1, wherein the clock number of 0 bits obtained through the initial sampling of the sampling unit is used as a reference for automatic baud rate detection together with the clock number of the start bit. 2. The automatic baud rate detection apparatus according to claim 1, wherein the sampled zero bits and subsequent consecutive bits (1 to 7 bits) stored in the second register are data to be transmitted. 2. The automatic baud rate detection apparatus of claim 1, wherein the start bit operates at a falling edge and ends at a rising edge. 2. The automatic baud rate detection apparatus of claim 1, wherein the 0 bit operates at the rising edge and terminates at the falling edge. 2. The automatic baud rate detection apparatus of claim 1, wherein the second register is configured of an 8-bit register to store 7 bits of data transmitted sequentially after an initial 0 bit. Receiving an input signal; Detecting a falling edge of a start bit of the input signal; Counting the number of clocks of the start bit; Detecting a rising edge of the start bit and ending counting of a start bit; Storing the clock number of the start bit in a first register and counting a clock number of 0 bits transmitted following the start bit signal; Sampling the zero bit signal when the number of clocks of the zero bit has a value of 1/2 of the number of clocks of the start bit; Detecting a falling edge of the 0 bit and ending counting; Storing the clock number of the 0 bit in the first register; Checking whether the number of clocks of the start bit stored in the first register and the number of clocks of the zero bit are the same and outputting a transmission stop signal if the number is not the same; Sampling a 1 to 7 bit signal and a stop bit of the same baud rate when the clock number of the start bit and the clock number of the 0 bit are the same; And outputting an end signal when the data consisting of the 0 to 7 bits is identical to the input signal.

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