KR100777703B1 - device for driving liquid crystal display and driving method therof - Google Patents

Abstract

The present invention relates to a driving device and a driving method of a liquid crystal display device.

In the present invention, a plurality of gate lines and data lines are formed in row and column directions, respectively, and a plurality of switching elements each having a switching element connected to the gate line and the data line in an area defined by the intersection of the gate line and the data line, respectively. A drive device for a liquid crystal display device comprising a liquid crystal panel in which pixels are formed; A gate driver configured to supply a gate driving voltage to drive the switching element to the gate line; A data driver which supplies a corresponding gray voltage to the data line according to the image data applied; And a timing controller for controlling the operations of the gate driver and the data driver, and providing image data to the data driver at a frame frequency higher than the frame frequency of the input image data so as to display an image.

According to the present invention, since the frame frequency displayed in the liquid crystal display device can be increased, the afterimage can be solved by shortening the voltage application time applied to the liquid crystal in the liquid crystal panel.

LCD, image signal processing, frame frequency

Description

Driving device and driving method of liquid crystal display device {device for driving liquid crystal display and driving method therof}

1 is an overall structural diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a diagram illustrating a detailed structure of a timing controller and a memory unit of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a frequency spectrum of a clock signal for inputting and outputting image data according to an embodiment of the present invention.

4 is a diagram illustrating a process of performing image data input / output in a memory of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a diagram illustrating a frequency spectrum of a clock signal for inputting and outputting image data in a liquid crystal display according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus and a driving method of a liquid crystal display (LCD), and more particularly, to processing and displaying image data provided from an image signal source in a liquid crystal display.                         

Recently, display devices are also required to be lighter and thinner in accordance with the light weight and thickness of personal computers and televisions, and according to such demands, flat displays such as liquid crystal displays (LCDs) instead of cathode ray tubes (CRTs) are required. Panel-type displays are being developed.

An LCD is a display device that obtains a desired image signal by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field. Such LCDs are typical of portable flat panel displays, and among them, TFT-LCD using a thin film transistor (TFT) as a switching element is mainly used.

In general, an LCD includes a plurality of gate lines that transmit scan signals and data lines that are formed to intersect the gate lines and transmit image data, and are formed in areas surrounded by the gate lines and the data lines, respectively. It includes a plurality of pixels in the form of a matrix connected through a data line and a switching element.

As a method of applying image data to each pixel in such an LCD, first, a timing controller receives image data from an image signal source (for example, a computer or a TV), and then scans the gate driving IC at a predetermined timing. Image data is output to a data driving IC while outputting a signal. The gate driving IC sequentially turns on the switching element connected to the gate line by applying a gate-on signal, which is a scanning signal, to the gate line, and at the same time, the data driving IC provides analog data corresponding to the image data in the pixel row corresponding to the gate line. A signal (more specifically, a gray voltage) is supplied to each data line. Then, the image signal supplied to the data line is applied to each pixel through the turned-on switching element. At this time, the gate-on signal is sequentially applied to all the gate lines during one frame period to apply the image data to all the pixel rows, thereby eventually displaying the image of one frame.

However, there is a problem in that unnecessary electromagnetic waves are generated at a specific frequency by the frame frequency in the image signal processing of the conventional LCD. Specifically, when the image data provided from the image signal source is converted into a digital signal and inputted to the driving IC, and then converted into an analog signal in the driving IC and applied to each pixel, from the image signal source The frame frequency of the image data is provided in a determined state, and the frame frequency is so stable that it emits unnecessary electromagnetic waves (EMI: Electro Magnetic Interference) at a specific frequency.

In addition, when the image signal source is a computer and the display resolution is very high, the frame frequency tends to be somewhat lowered. When the image data is applied to the liquid crystal panel while the frame frequency is reduced, the screen flicker, or flicker, may occur. There is a problem that occurs.

In addition, there is a problem that an afterimage, which is an inherent characteristic, exists in LCD image display, and this afterimage problem has been eliminated to some extent by the improvement of the material of the liquid crystal and the improvement of the cell structure, but has not reached a satisfactory level.

 Therefore, the technical problem to be solved by the present invention is to solve such a problem, and in the liquid crystal display device converts the frame frequency of the image data input from the image signal source to a higher frequency, and according to the converted frame frequency To provide a liquid crystal panel to prevent the generation of electromagnetic waves and flicker.

According to an aspect of the present invention, there is provided a driving apparatus of a liquid crystal display device, wherein a plurality of gate lines and data lines are formed in row and column directions, respectively, and are defined as intersections of the gate lines and data lines. A driving apparatus of a liquid crystal display comprising a liquid crystal panel having a plurality of pixels having switching elements connected to the gate line and the data line, respectively, comprising: a gate driving for driving the switching element with the gate line; A gate driver supplying a voltage; A data driver which supplies a corresponding gray voltage to the data line according to the image data applied; And a timing controller which controls the operations of the gate driver and the data driver, and provides the image data to the data driver at a frame frequency higher than the frame frequency of the input image data to display the image.

In addition, the apparatus further includes a memory unit in which image data provided from the outside is stored, and in this case, the timing controller modulates the first clock signal applied from the outside into a second clock signal of a higher frequency, and the first clock signal. Image data stored in the memory unit is stored based on the second clock signal, and the image data stored in the memory unit is output to the data driver based on the second clock signal.

The timing controller reads out image data corresponding to the next address where image data is last read in a previous frame among image data of one frame stored in the memory unit during an input frame in which the image data is input into the memory unit. If the image data of the last address of the current reading frame is read out during this process, the image data of the first address is read again.

Meanwhile, the memory unit may include first and second memories for storing image data; And a memory input / output unit configured to output image data to the first or second memory according to a signal applied from the timing controller, and to provide image data output from the second or first memory to the timing controller. Image data storing and reading operations of the second memory are alternately performed.

The timing controller may further include a frequency modulator for modulating the first clock signal into a second clock signal having a higher frequency; A memory timing controller for controlling image data input / output operations of the memory unit; And a driving IC controller configured to provide image data provided from the memory unit to the data driver in accordance with a driving clock signal synchronized with the second clock signal, and to drive the gate driver.

The memory timing controller may include an input / output controller that controls an operation of the memory input / output unit; A write signal generation unit generating a control signal for storing image data in the memory unit based on the first clock signal; A read signal generation unit generating a control signal for outputting image data stored in the memory unit based on the second clock signal; And an address generator for generating addresses of first and second memories for storing and outputting the image data.

In addition, a method of driving a liquid crystal display according to another aspect of the present invention includes a liquid crystal panel including a plurality of gate lines and data lines, and a plurality of pixels formed in an area where the gate lines and the data lines cross; A scan driver supplying a gate voltage to the gate line; A driving method of a liquid crystal display comprising a data driver for supplying a corresponding gray voltage to the data line according to an applied data signal, the method comprising: storing one frame of image data provided from an image signal source in a memory; While the image data of the one frame is stored in the memory, reading the image data stored in the memory for a previous frame at a frequency higher than a frequency for storing the image data in the memory; Supplying a gate driving signal to a gate line for driving the switching device; And supplying a gray voltage corresponding to the read image data to the data line while driving signals are respectively applied to the gate line.

The reading of the image data may include: image data corresponding to a next address of the image data last read from the previous frame among the image data of one frame stored in the memory unit during the input frame in which the image data is input into the memory. If the image data of the last address of the current reading frame is read while the reading is performed, the image data of the first address is read again.                     

Hereinafter, with reference to the drawings will be described an embodiment of the present invention;

1 illustrates an overall structure of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention performs an interface with an image signal source 1 and provides an interface 2 and an interface 2 for receiving image data. An A / D converter 3 for converting image data provided through the digital signal, a memory unit 4 for storing digitally converted image data, and a timing controller 5 for controlling input and output of image data to the memory unit 4 And a data driver 6, a scan driver 7, and a liquid crystal panel 8.

In the liquid crystal panel 8, a plurality of gate lines are formed to transmit the gate driving signal, and a plurality of data lines are formed to cross the gate line and to transmit a gray voltage representing an image signal. Pixels are formed in a matrix in each region where the gate line and one data line cross each other.

The data driver 6 is also called a source driver and serves to lower the voltage value transmitted to each pixel in the liquid crystal panel 8 by one line. More specifically, the data driver 3 stores digital data from the timing controller 5, which will be described later, in a shift register in the data driver, and then a signal (LOAD signal) instructing the liquid crystal panel 8 to lower the data. In this case, a voltage corresponding to each data is selected to transfer the voltage into the liquid crystal panel 8.

The scan driver 7 is also referred to as a gate driver, and serves to open a road so that data from the data driver 3 can be transferred to the pixel. Each pixel of the liquid crystal panel 8 is turned on or off by a TFT serving as a switch, which is turned on and off by applying a constant voltage (Von, Voff) to the gate.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention includes a Von Voff Vcom generating unit generating a Von voltage for turning on the gate of the TFT, a Voff voltage for turning off the gate, and a Vcom voltage as a reference for the data voltage difference in the TFT. The apparatus may further include a gray voltage generator that supplies a gray voltage to the data driver.

On the other hand, the timing controller 5 generates a digital signal for driving the data driver 6 and the scan driver 7, and specifically generates a signal entering the drivers 6 and 7 and adjusts the timing of the image data. , Clock adjustment, etc.

In particular, the timing controller 5 according to the embodiment of the present invention modulates the frame frequency of the image data provided from the image signal source 1 to a higher frequency, and is stored in the memory unit 4 according to the modulated frame frequency. Control output and display of image data.

2 shows the detailed structure of the timing control section and the memory section in which image data is stored.

As shown in FIG. 2, the memory unit 4, which stores the image data provided from the image signal source 1 and digitally converted, includes the first and second memories 42 and the timing controller 5. Multiplexer 43 for performing input (or " write ") of image data to first and second memories 41 and 42 under control, and from the first and second memories 41 and 42. A demultiplexer 44 that performs phase data output (or " read "). Here, the multiplexer 43 is 1 × 2 MUX, and the demultiplexer 44 is 2 × 1 DEMUX.

The timing controller 5 for controlling the image data input / output and the image data display operation of the memory unit 4 having such a structure includes a memory timing controller 51 for adjusting the image data input / output timing of the memory unit 4, and an image. A frequency modulator 52 for generating a clock signal for adjusting the input / output timing of data, and a driving IC controller for outputting image data to the data driver 6 and providing a gate drive signal to the scan driver 7, and the like; 53).

The memory timing controller 51 performs an MUX signal generator 512 for generating a signal MUX D for controlling operations of the multiplexer 43 and the demultiplexer 44, and performing input / output (write / read) of image data. An address generator 512 for generating addresses ADDR A and ADDR B of a memory for writing, a write signal generator 513 for generating signals WR A and WR B for performing image data writing, and reading of image data. Read signal generator 514 for generating signals RD A and RD B for performing.

The frequency modulator 52 for generating a clock signal for controlling the operation of the memory timing controller 51 is hundreds of times than the first clock signal based on a clock signal input from the outside (hereinafter, referred to as a "first clock signal"). A function generator 521 for generating a signal having a frequency of several to several thousand times lower frequency (a waveform such as a triangular wave or a sawtooth wave, a sine wave, etc.) and a higher phase having the same phase as that of the first clock signal based on a signal provided from the function generator 521. And a phase locked loop (PLL) 522 for generating a clock signal having a frequency (hereinafter referred to as a "second clock signal").

The frequency f _o of the second clock signal generated by the PLL 522 is as follows.

Here, f _i represents the frequency of the first clock signal, k represents the frequency multiplication ratio (for example, 1.5 to 2.5), and Δf represents the frequency fluctuation range.

로 나타낼 수 있으며, 이러한 제1 클락 신호를 변조 처리한 제2 클락 신호를 시간에 따른 주파수 함수로 나타내면 다음과 같이 나타낼 수 있다. The frequency modulator 52 modulates the input first clock signal time-varying and modulates the first clock signal into a second clock signal having a wide frequency bandwidth.

The second clock signal modulated by the first clock signal may be expressed as a function of frequency according to time.

Where f (t) represents the frequency modulation amplitude, A is the amplitude, s (t) is the modulated signal, {omega} _ {m} s (t) is the frequency shift, and {omega} _ {c} is the angular velocity. Represent each.

3 shows the power spectrums before and after frequency modulation of such first and second clock signals. As shown in FIG. 3, the peak value is output in a specific frequency band before the clock signal modulation, and the peak value is lowered as the frequency band in which the peak value is output after the modulation is widened. The integral value of the power of the first clock signal or the frequency of the energy is equal to the power integral of the second clock signal, and the peak value is reduced while only a signal having a very narrow frequency band is spread to a wider signal. will be.

As described above, in the exemplary embodiment of the present invention, the frequency of the clock signal is modulated so that the frame frequency of the image data provided to the liquid crystal panel is increased, thereby eliminating unnecessary frequencies and the like in a specific frequency band. In particular, in a LCD, a DC component is generated due to a kick-back phenomenon when driving a liquid crystal, and ionic impurities present in the liquid crystal material move toward the alignment layer, and ionic impurities reach the surface of the alignment layer. Is generated. However, if the frame frequency is sufficiently raised, the ionic impurities change direction whenever the polarity of the applied electric field is changed even in the presence of a direct current component, and the moving distance is shortened to prevent reaching the surface of the alignment layer so that no afterimage occurs. Therefore, in the embodiment of the present invention, the frame frequency is sufficiently raised to prevent afterimages from occurring.

Next, the operation of the liquid crystal display device according to the embodiment of the present invention having such a structure will be described in more detail.

When an analog video signal is input from the image signal source 1, the interface unit 2 outputs image data corresponding to this signal, a synchronization signal (vertical and horizontal synchronization signals), and a clock signal. The synchronization signal is input to the timing controller 5, the clock signal, that is, the first clock signal, is input to the timing controller 5 and the A / D converter 3, respectively, and the image data is input to the A / D converter 3. Is entered.                     

The A / D converter 3 converts the image data into a digital signal in real time in synchronization with the input first clock signal and outputs the digital signal. The timing controller 5 operates according to the first clock signal input to convert the image signal into a digital signal. Input / output of the image data to the memory unit 4 is controlled.

First, the timing controller 5 modulates the frequency of the input first clock signal and then generates a signal for controlling the image data input and output. As described above, the PLL 522 of the frequency modulator 5 modulates the frequency of the first clock signal input based on the signal provided from the function generator 521 to generate a second clock signal to generate a second clock signal. 51).

The memory timing controller 51 controls the multiplexer 43 according to the first clock signal so that the image data is stored in the first memory 41 or the second memory 42, or the demultiplexer 44 according to the second clock signal. ) To read the image data stored in the second memory 42 or the first memory 41. At this time, image data write and read operations to the first and second memories 42 are alternately performed.

4 illustrates a process of writing and reading image data into a memory according to an embodiment of the present invention. Hereinafter, for convenience of description, an image data input / output operation will be described using an LCD of a super extended graphics array (SXGA) 1280 × 1024 as an example.

When the high level mux signal MUX D is provided to the multiplexer 43 and the demultiplexer 44, respectively, from the MUX signal generator 511 of the memory timing controller 51, the multiplexer 43 is A / D. The image data input from the converter 3 is output to the first memory 41, and the demultiplexer 44 provides the image data applied through the input terminal connected to the second memory 42 to the driving IC controller 53. .

Specifically, the first memory 41 stores image data output from the multiplexer 43 in accordance with the control signal WDA provided from the address generator 512 and the write signal generator 513 at the corresponding address ADDR A. The second memory 42 reads the image data stored at the address ADDR B according to the control signal RDB provided from the address generator 512 and the read signal generator 514 and provides the demultiplexer 44 with the read data. do.

In the case of an LCD of SXGA (1280 × 1024), since one frame is composed of 1024 horizontal lines, in the present embodiment, 1024 horizontal lines of digital image data are stored in the first frame F1. 1 is stored in the memory 41. On the other hand, when the write operation of the first memory 41 is performed, as described above, the read operation of the second memory 42 should be performed, but as shown in FIG. The read operation is not performed because the stored image data is not valid data.

In the next frame, the write / read operations of the first memory 41 and the second memory 42 are changed. For example, when the low level mux signal is provided to the multiplexer 43 and the demultiplexer 44, respectively, the multiplexer 43 outputs the image data input from the A / D converter 3 to the second memory 42. The demultiplexer 44 provides the driver IC controller 53 with image data applied through an input terminal connected to the first memory 41.                     

The first memory 41 reads the image data stored at the address ADDR A according to the control signal RDA provided from the address generator 512 and the read signal generator 514 to provide it to the demultiplexer 44. The second memory 42 stores image data output from the multiplexer 43 in correspondence with the control signal WDB provided from the address generator 512 and the write signal generator 513 at the corresponding address ADDR B.

In this case, control signals for storing image data in the memory are generated according to the first clock signal, and control signals for reading image data stored in the memory are generated according to the second clock signal modulated by the frequency modulator 52. As described above, since the frequency of the second clock signal is higher than that of the first clock signal, the read operation of the image data is completed first before the write operation of the image data is completed.

For example, if the first clock signal is about 40% faster than the second clock signal, the SXGA LCD can read about 1462 horizontal lines of image data during one frame in which 1024 pieces of image data are stored. have.

For example, as shown in FIG. 4, while the 1024 pieces of image data corresponding to the second frame F2 are stored in the second memory 42, the previous frame, that is, the first frame, stored in the first memory 41 is stored. After all of the image data (1024 horizontal lines) of the burned frame F1 is read out, a part of the image data (about 438 horizontal lines) of the same frame F1 is further read. As a result, a total of 1462 horizontal lines of image data are read out and provided to the demultiplexer 44.

Next, the write / read operations of the first and second memories 41 and 42 are changed to perform a write operation in accordance with the first clock signal in the first memory 41 and a second clock signal in the second memory 42. A read operation is performed accordingly. Even in this case, since the frequency of the second clock signal is higher than the frequency of the first clock signal, as described above, the second frame is stored in the first memory 41 while one frame of image data (1024 horizontal lines) is stored. More than one frame of image data (1462 horizontal lines) is read from the memory 42.

At this time, the address generator 512 of the memory timing controller 5 reads from the image data of the current read frame F2 corresponding to the next line number of the horizontal line number last read out from the previous read frame F1. As a result, as shown in FIG. 4, the horizontal line number last read out from the previous frame F1 among the image data of the current read frame F2, i. After reading from the image data, the image data corresponding to No. 1024 of the current reading frame F2 is read out, and then image data corresponding to Nos. 1 to 876 of the current reading frame F2 are read out again, for a total of 1462 horizontal lines. Image data ((1024-438) + 876 = 1462) corresponding to the line amount is read.

In this way, the memory read operation reads from the next address data last read in the previous frame within the time limit for inputting one frame, and again if the image data of the last address of the frame is read before the reading is completed. Further reading is performed from the image data of the first address.

As a result, the number of frames to be output can be greatly increased than the frame rate to be input, thereby solving flicker that is likely to occur in the LCD.

As described above, the image data read out from the memory is provided to the data driver 6 through the driver IC controller 53, and the data driver 6 is supplied from the driver IC controller 53 to the data clock signal CLK3. In synchronization, the image data is converted into corresponding gray voltages, and then applied to the data lines of the liquid crystal panel 8 according to a load signal applied thereto, and the scan driver 7 outputs the gate clock output from the driver IC controller 53. In synchronization with the signal CLK4, a gate-on voltage serving as a scan signal is simultaneously applied to the gate line of the liquid crystal panel 8. Accordingly, the thin film transistor connected to the gate line to which the gate on voltage is applied is turned on, and the gray voltage supplied to the data line is transferred to the pixel electrode through the turned on thin film transistor to display a desired image.

In this case, image data of the same frame is displayed superimposed on the liquid crystal panel, but since the image data of the previous frame and the current frame displayed are almost the same, the user cannot recognize the image difference.

In addition, the clock signals CLK2 when reading image data from the memory and the clock signals CLK3 and CLK4 when the driving IC control unit 53 drives the respective driving units are the same, and therefore the clock signals provided from the timing control unit. Even if the frequency of is modulated, no problem occurs in the timing margin when data is transferred to the liquid crystal panel.

In FIG. 5, the frequency spectrum generated at the clock of each driving unit is shown when the clock signal is unmodulated with frequency and when the clock signal is modulated with frequency as in the embodiment of the present invention.                     

Referring to FIG. 5, in the embodiment of the present invention, the power value in the corresponding frequency band is reduced while the specific frequency band in which the power value is greater than or equal to the set value is widened, compared to the case in which the clock signal in which the frequency is not modulated is conventionally used. Unnecessary electromagnetic waves can be reduced.

The invention is susceptible to various modifications and implementations without departing from the scope of the following claims.

As described above, according to the present invention, since the frame frequency displayed in the liquid crystal display device can be increased, the afterimage can be solved by shortening the voltage application time applied to the liquid crystal in the liquid crystal panel.

In addition, since image display is performed at a frame frequency higher than that of humans, it is possible to solve flicker that is likely to occur in the LCD. Accordingly, since the charge retention capacitor in the liquid crystal cell can be made small due to the flicker generation, it is possible to manufacture high quality LCDs by improving the charge charge rate and aperture ratio.

Claims (8)

A plurality of gate lines and data lines are formed in the row and column directions, respectively, and a plurality of pixels having switching elements connected to the gate line and the data line are formed in an area defined by the intersection of the gate line and the data line, respectively. A drive device for a liquid crystal display device comprising a liquid crystal panel; A gate driver configured to supply a gate driving voltage to drive the switching element to the gate line; A data driver which supplies a corresponding gray voltage to the data line according to the image data applied; And A timing controller which controls the operation of the gate driver and the data driver and provides image data to the data driver by providing image data at a frame frequency higher than the frame frequency of the input image data. Including, The timing controller, During the input frame in which the image data is input into the memory unit, from the image data of one frame stored in the memory unit, the image data corresponding to the next address where the image data was last read out from the previous frame is read out, and the current read frame during the read operation is performed. And in the case where the image data of the last address is read out, the image data of the first address is read out again. The method of claim 1, Further comprising a memory unit for storing image data provided from the outside, The timing controller modulates a first clock signal applied from the outside into a second clock signal having a higher frequency, stores image data to the memory unit based on the first clock signal, and based on the second clock signal. And outputting the image data stored in the memory to the data driver. delete The method of claim 2, The memory unit First and second memories in which image data is stored; And a memory input / output unit configured to output image data to the first or second memory according to a signal applied from the timing controller, and to provide image data output from the second or first memory to a timing controller. And the image data storing and reading operations of the first and second memories are alternately performed. The method of claim 4, wherein The timing controller A frequency modulator for modulating the first clock signal into a second clock signal of higher frequency; A memory timing controller for controlling image data input / output operations of the memory unit; And A driving IC controller configured to provide image data provided from the memory unit to the data driver in accordance with a driving clock signal synchronized with the second clock signal, and to drive the gate driver; Driving device for a liquid crystal display comprising a. The method of claim 5, The memory timing controller, An input / output control unit controlling an operation of the memory input / output unit; A write signal generation unit generating a control signal for storing image data in the memory unit based on the first clock signal;  A read signal generation unit generating a control signal for outputting image data stored in the memory unit based on the second clock signal; And An address generator for generating addresses of first and second memories for storing and outputting the image data Driving device for a liquid crystal display comprising a. A liquid crystal panel including a plurality of gate lines and data lines, and a plurality of pixels formed in a region where the gate lines and data lines cross each other, and including a plurality of pixels each including a switching element; A scan driver supplying a gate voltage to the gate line; In the driving method of the liquid crystal display device including a data driver for supplying a corresponding gray voltage to the data line in accordance with the applied data signal, Storing one frame of image data provided from an image signal source in a memory; While the image data of the one frame is stored in the memory, reading the image data stored in the memory for a previous frame at a frequency higher than a frequency for storing the image data in the memory; Supplying a gate driving signal to a gate line for driving the switching device; And Supplying a gray scale voltage corresponding to the read image data to a data line while driving signals are respectively applied to the gate line Method of driving a liquid crystal display comprising a. The method of claim 7, wherein The reading of the image data may include: During the input frame in which the image data is input into the memory, from the image data of one frame stored in the memory section, the image data corresponding to the address after the last reading of the image data is read out from the previous frame, and during reading And when the image data of the last address is read, the image data of the first address is read again from the first address.

Images