KR100771140B1 - Operation determination device for controlling source voltage and circuit system including the same - Google Patents

Abstract

An operation discrimination device for controlling source voltage and a circuit system including the same are provided to perform efficient power consumption by providing the minimum source voltage for operating the circuit system and determine efficiently the minimum voltage for operating the circuit system by using a plurality of delay circuits. A first delay circuit(200) delays an input signal for a shorter time than delay of an operation circuit. A second delay circuit(202) delays the input signal for the same time as the operation circuit. A third delay circuit(204) delays the input signal for a longer time than the delay of the operation circuit. A reader(212) generates a source voltage control signal for controlling the source voltage based on an output signal of the first, second, and third delay circuit. A first, second, and third flip-flop(206-208) is respectively combined with the first, second, and third delay circuit, and respectively outputs an output signal corresponding to output of the first, second, and third delay circuit. The output signal of the first, second, and third flip-flop is inputted to the reader.

Description

[Operation Determination Device for Controlling Source Voltage and Circuit System Including the Same}

1 is a diagram illustrating a configuration of a circuit system to which an operation discriminator for power supply voltage control according to an exemplary embodiment of the present invention is applied.

Figure 2 is a block diagram showing the configuration of an operation discriminator according to an embodiment of the present invention.

3 is a detailed circuit diagram of an operation discriminator having a plurality of delay circuits according to an exemplary embodiment of the present invention.

4 is a flow chart showing the operation of the motion discriminator having the configuration of FIG. 3 in accordance with an embodiment of the present invention.

FIG. 5 is a flow chart showing the operation of the motion discriminator having the configuration of FIG. 3 according to another embodiment of the present invention. FIG.

The present invention relates to an operation determining apparatus for power supply voltage control and a circuit system including the same, and more particularly, to an apparatus for dynamically adjusting a power supply voltage of a circuit system and a system including the same.

Research on related technologies for minimizing power consumption while having high processing capacity for high performance CPUs and multimedia terminals has been actively conducted in various fields. In particular, the rapid expansion of the mobile environment has highlighted the importance of low-power design technology. The low power design techniques studied so far have been mainly focused on optimization techniques at the circuit design level and techniques for optimizing power consumption of storage, memory, and display with the help of the OS at the system level.

For low power design, it is required to accurately determine how much voltage is required for operation in a system consuming power, but conventional low power voltage control devices have a problem in that they cannot efficiently determine the minimum voltage required for system operation.

In the present invention, in order to solve the problems of the prior art as described above, the present invention includes an operation determination device for controlling the power supply voltage to provide efficient power consumption by providing only the minimum power supply voltage required for the operation of the circuit system and the same To propose a circuit system.

Another object of the present invention is to propose an operation determining apparatus for power supply voltage control and a circuit system including the same, which efficiently determine a minimum voltage required for operation of a circuit system using a plurality of delay circuits.

In order to achieve the above object, according to an aspect of the present invention, the operation determining device for generating a control signal for controlling the power supply voltage of the operation circuit, the input signal for a time shorter than the delay time of the operation circuit At least one first delay means configured to delay; Second delay means set to delay an input signal for the same delay time as said operation circuit; At least one third delay means configured to delay the input signal for a time longer than a delay time of the operation circuit; And reading means for generating a power supply voltage control signal for controlling the power supply voltage based on output signals of the first delay means, the second delay means and the third delay means.

The circuit operation determining apparatus includes: at least one first flip-flop coupled with the at least one first delay means; A second flip flop coupled with the second delay means; And at least one third flip-flop coupled with the at least one third delay means, wherein the first, second and third flip-flops are connected to the outputs of the first, second and third delay means. A corresponding output signal is output, and output signals of the first, second and third flip-flops are input to the reading means.

The first, second and third flip-flops output an output signal to a next clock cycle of a clock cycle corresponding to the input signal.

The reading means generates a power supply voltage control signal for raising a power supply voltage to the operation circuit if the output levels of the first flip-flop and the second flip-flop are not equal to the level of the input signal.

The reading means generates a power supply voltage control signal for lowering the power supply voltage to the operation circuit when the output level of the third flip-flop is not equal to the level of the input signal.

The input signal is equal to the level of the power supply voltage provided to the operation circuit, and further includes a fourth flip-flop for outputting the input signal, wherein the output signal of the fourth flip-flop is the first, second and Input to the third delay means.

According to another aspect of the present invention, a circuit system capable of controlling the power supply voltage, comprising: an operation circuit for performing a predetermined circuit operation; A voltage variable power supply configured to supply a power supply voltage to the operation circuit and to adjust a power supply voltage level in response to a power supply voltage control signal; A power source voltage control including an operation discriminator that determines the minimum voltage level at which the operation circuit is operable and generates and provides the power voltage control signal to the voltage variable power supply so that a power supply voltage is provided at the minimum voltage level at which the operation circuit is operated. A circuit system is provided.

According to another aspect of the present invention, a method for controlling a power supply voltage provided to a circuit system, comprising: delaying the input signal shorter than a delay time of the circuit system using the power supply voltage signal provided to the circuit system as an input signal. Step (a); (B) delaying the input signal by a time equal to a delay time of the circuit system using a power supply voltage signal provided to the circuit system as an input signal; (C) delaying the input signal longer than a delay time of the circuit system by using a power supply voltage signal provided to the circuit system as an input signal; And (d) generating a power supply voltage control signal for adjusting a power supply voltage provided to the circuit system based on the level of the delay signal output in steps (a), (b), and (c). A power supply voltage control method is provided.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the operation determination device for controlling the power supply voltage according to the present invention and a circuit system including the same.

1 is a diagram illustrating a circuit system to which an operation discriminator for controlling a power supply voltage according to an exemplary embodiment of the present invention is applied.

Referring to FIG. 1, a circuit system to which an operation discriminator according to an exemplary embodiment of the present invention is applied may include an operation circuit 100, an operation discriminator 102, and a voltage variable power supply 104.

The voltage variable power supply 104 functions to provide a power supply voltage to the operation circuit 100. The voltage variable power supply 104 adjusts the level of the output voltage provided to the operation circuit 100 in response to the voltage control signal provided from the operation discriminator 102.

The voltage control signal provided from the operation discriminator includes control information indicating a rise or fall of the voltage, and the voltage variable power supply 104 increases or decreases the voltage provided to the operation circuit according to the control information.

The operation circuit 100 receives power from the voltage variable power supply 104 and performs a preset operation. The operation circuit may be various, such as a semiconductor memory circuit, a semiconductor memory control circuit, a processor circuit.

The power consumed by the operation circuit 100 provided from the voltage variable power supply 104 is expressed by Equation 1 below.

In Equation 1 above, P is power consumption, C is the equivalent capacitance of the entire circuit, f is the operating frequency of the system, and V is the magnitude of the voltage provided from the voltage variable power supply.

To maximize power efficiency, it is desirable to consume the least amount of power within the limits of which the operating circuit can operate.

In a typical circuit system, the equivalent capacitance C of the entire circuit is fixed. In addition, the operating frequency f is fixed to perform the operation set in the operating circuit. Therefore, it is difficult to achieve power efficiency by changing the capacitance C and the operating frequency f.

In Equation 1, since the power consumption is proportional to the square of the power supply voltage V, to minimize the power consumption of the operation circuit 100, it is preferable to provide a minimum voltage at which the normal operation of the operation circuit 100 is guaranteed.

The operation discriminator 102 provides a power supply voltage control signal to the voltage variable power supply 104. As described above, the operation discriminator 102 generates and provides a power supply voltage control signal to the voltage variable power supply 104 such that only a minimum voltage at which the normal operation of the operation circuit 100 is guaranteed is provided.

The operation discriminator 102 determines the minimum power supply voltage at which the operation circuit 100 can operate normally. A detailed configuration in which the operation discriminator 102 determines the magnitude of the minimum power supply voltage at which the operation circuit 100 can operate normally will be described in detail with reference to the separate drawings.

The operation discriminator 102 controls a control signal to lower the output power voltage to the voltage variable power supply 104 when the power supply voltage provided from the voltage variable power supply 104 is greater than the minimum voltage required for operation of the operation circuit. To provide.

In addition, the operation discriminator 102 controls to increase the output voltage to the voltage variable power supply 104 when the power supply voltage provided from the voltage variable power supply 104 is smaller than the minimum voltage required for operation of the operation circuit. Provide a signal.

According to a preferred embodiment of the present invention, the operation determiner 102 determines the minimum voltage required for the operation circuit 100 by using the characteristic that the lower the power supply voltage, the greater the delay of the signal. When the voltage is lowered, the operation of the transistor is delayed, and the present invention takes advantage of this characteristic.

As described above, the operation discriminator 102 determines the minimum voltage required for the power supply of the operation circuit 100 and accordingly provides a control signal to the voltage variable power supply 104 to consume power in the operation circuit 100. The power consumed can be minimized.

2 is a block diagram illustrating a configuration of an operation discriminator according to an exemplary embodiment of the present invention.

2, an operation discriminator according to an exemplary embodiment of the present invention may include a first delay circuit 200, a second delay circuit 202, a third delay circuit 204, a first flip-flop 206, The second flip-flop 208, the third flip-flop 210, and the read circuit 212 may be included.

In FIG. 2, the first to third delay circuits 200, 202, and 204 serve to delay the input signal by a predetermined delay time.

The second delay circuit 202 is set to delay the input signal by a time equal to the delay time in the operation circuit 100. That is, the delay time of the second delay circuit 202 is implemented such that the delay is equal to the maximum delay value present between the flip-flops in the operation circuit.

The first delay circuit 200 is set to delay the input signal for a relatively short time than the second delay circuit. That is, the first delay circuit 200 delays the input signal for a time shorter than the delay time in the operation circuit 100.

The third delay circuit 204 is set to delay the input signal for a relatively longer time than the second delay circuit. That is, the third delay circuit 204 delays the input signal for a time longer than the delay time in the operation circuit 100.

The first flip-flop 206 receives the output signal of the first delay circuit 200 as an input and outputs the signal to the next cycle of the input signal clock cycle to the delay circuit. Each of the second flip flop 208 and the third flip flop 210 receives the outputs of the second delay circuit 202 and the third delay circuit 204 as inputs, and each of the input signal clock cycles to each delay circuit. Output the signal in the next cycle.

The read circuit 212 analyzes an output signal output from the first to third flip-flops 206, 208, and 210 to generate a power supply voltage control signal, and the generated power supply voltage control signal is a voltage variable power supply ( 104).

The read circuit 212 determines whether a signal output from the first to third flip-flops 206, 208, and 210 is the same as an input signal to generate a power supply voltage control signal.

For example, if the input signal is 1 and the first flip-flop 206 outputs 1 at the next clock of the input signal clock cycle, the read circuit 212 may not be able to drive the operating circuit. I don't think it's low enough. On the other hand, when the input signal is 1 and the first flip-flop 206 outputs 0 in the clock of the cycle following the input signal, the read circuit 212 determines that the power supply voltage is low and raises the power supply voltage. Generate a control signal.

Since the first delay circuit 200 delays the delay for a time shorter than a delay occurring in the operation circuit, if the output value of the first flip-flop 206 is different from the input signal, the operation circuit 100 may not operate normally. 212 generates a power supply voltage control signal for raising the power supply voltage.

If the input signal is 1 and the second flip-flop 208 outputs 1 at the next clock of the input signal clock cycle, the read circuit 212 is in a state in which the power supply voltage that is currently supplied is low enough to cause problems in driving the operating circuit. I do not think it is. On the other hand, when the input signal is 1 and the second flip-flop 208 outputs 0 in the clock of the cycle following the input signal, the read circuit 212 determines that the power supply voltage is low and raises the power supply voltage. Generate a signal.

Since the second delay circuit 202 delays the delay by the same time as the delay occurring in the operation circuit, if the output value of the second flip-flop 206 is different from the input signal, the operation circuit 100 cannot operate normally. 212 generates a power supply voltage control signal for raising the power supply voltage.

When the input signal is 1 and the third flip-flop 210 outputs 1 at the next clock of the input signal clock cycle, the read circuit 212 causes the power supply voltage supplied to be the minimum voltage required for the operation of the operation circuit 100. I judge it to be bigger. The third delay circuit 204 delays the signal by more than the delay time occurring in the operating circuit, so that when the third flip-flop 210 still outputs the same signal as the input signal, the operating circuit 100 can be operated even at a lower power supply voltage. Means that it can work normally. Therefore, when the input signal and the signal of the third flip-flop 210 are the same, the read circuit 212 generates a power supply voltage control signal for lowering the power supply voltage.

On the other hand, when the input signal is 1 and the third flip-flop 210 outputs 0 at the next clock of the input signal clock cycle, the read circuit 212 determines that the normal power supply voltage is being supplied.

That is, the present invention includes a plurality of delay circuits having different delay times, and then compares the input values with the output values of the delay circuits to provide a minimum power supply voltage necessary for driving the operation circuit 100. Create

2 illustrates a first delay circuit 200 having a shorter delay time than an operation circuit, and a third delay circuit 204 having a larger delay time than an operation circuit of a second delay circuit 202 having the same delay time as the operation circuit. Although the case is shown, it will be apparent to those skilled in the art that a larger number of delay circuits having different delay times may be provided for more detailed determination.

3 is a diagram illustrating a detailed circuit configuration of an operation discriminator having a plurality of delay circuits according to an exemplary embodiment of the present invention.

Referring to FIG. 3, an operation discriminator circuit according to an exemplary embodiment of the present invention may include a first flip-flop F0, a plurality of delay circuits P1, P2, P3, P4, P5, P6, and P7. A plurality of flip-flops (F1, F2, F3, F4, F5, F6, F7) coupled with each of the circuits and read circuits 212 coupled with the output of the flip-flop.

In FIG. 3, the first flip-flop F0 functions to control the output Q0 of the input signal for determining the operation. The first flip-flop F0 outputs an output signal Q0 corresponding to the input signal according to the values of the input SET signal and the RESET signal.

When 1 is input to SET and 0 is input to RESET, the first flip-flop F0 outputs 1 regardless of the value of the input signal.

In addition, when 1 is input to 0 RESET in the SET, the first flip-flop F0 outputs 0 regardless of the value of the input signal. That is, the first flip-flop F0 may output 0 or 1 regardless of the value of the input signal according to the SET and RESET signals. In particular, the first flip-flop F0 may output a desired output value by controlling the SET and RESET signals during initialization. .

In addition, when 0 is input to SET and 0 is input to RESET, the first flip-flop F0 outputs a signal having the same value as the input signal.

The system clock input to the flip flop of the operation discriminator is the same clock as the system clock of the operation circuit.

The first to seventh delay circuits P1, P2, P3, P4, P5, P6, and P7 are set to have different delay times. When the magnitude of the delay time is indicated by delay (Pn), the magnitude of the delay time of the first to seventh delay circuits is set as follows.

delay (P1) <delay (P2) <delay (P3) <delay (P4) <delay (P5) <delay (P6) <delay (P7)

Among the plurality of delay circuits, the delay time of the fourth delay circuit P4 is set to be the same delay time as the maximum delay time present between the flip-flops in the operation circuit. Therefore, the delay time of the first to third delay circuits P1, P2, and P3 is shorter than the maximum delay time of the operation circuit, and the delay times of the fourth to seventh delay circuits P5, P6, and P7. Is set longer than the maximum delay time of the operation circuit.

In the present invention, the operation is determined through the output of the flip-flops at the next clock cycle of the clock cycle to which the input signal is provided, assuming that the delay time of the seventh delay circuit having the largest delay time is set smaller than the clock cycle period. do.

The second flip-flop to the eighth flip-flop F1, F2, F3, F4, F5, F6, and F7, which are coupled to the plurality of delay circuits, respectively, are output signals of Q1 to Q7 in the next clock cycle of the clock cycle in which Q0 is output. Outputs When the second flip-flop to the eighth flip-flop generate an output signal, the values of SET and RESET are preferably set to 0 so that output signals Q1 to Q7 having the same value as the input signals D1 to D7 are output. Do.

As with the read circuit of FIG. 2, the read circuit 212 analyzes the magnitude of the output signal of the second to eighth flip-flops F1, F2, F3, F4, F5, F6, and F7 to supply a power supply voltage control signal. And provide the generated power supply voltage control signal to the voltage variable power supply 104.

The operation of the operation discriminator having the circuit configuration as described above will be described in more detail with reference to FIGS. 4 and 5 as follows.

4 is a flowchart illustrating an operation of an operation discriminator having the configuration of FIG. 3 according to an embodiment of the present invention.

Referring to FIG. 4, first, an initialization process of inputting 0 as the SET signal of the flip-flops F0, F1, F2, F3, F4, F5, F6, and F7 and inputting 1 as the RESET signal is performed (step 400). ). At this time, it is preferable that 0 is also input as D0. When 0 is input as the SET signal and 1 is input as the RESET signal, 0 is output regardless of the input signal. Therefore, Q0 which is the output of the first flip-flop F0 and Q1 which is the output of the second to eighth flip-flops Q7 is output as all zeros.

After the initialization step as in step 400, input 0 as the SET signal of the flip-flops F0, F1, F2, F3, F4, F5, F6, F7, input 0 as the RESET signal, and input 0 as the input signal. A deinitialization process is performed (step 402). When the SET signal is 0 and the RESET signal is 0, the flip-flop outputs the same value as the input signal, and the output Q0 of the first flip-flop F0 is maintained at 0.

After the deinitialization step, 1 is applied to the input signal D0 while both the SET signal and the RESET signal are kept at 0 (step 404).

After applying 1 to the input signal D0, the first to fourth delay circuits (P1, P2, P3, P4) set to have the same delay time as the operation circuit 100 or have a shorter delay time than the operation circuit. Whether the outputs Q1, Q2, Q3, and Q4 in the next clock cycle of the second to fifth flip-flops F1, F2, F3, and F4, respectively, combined with and output the same 1 as the input signal D0. Determine (step 406).

In the next clock cycle, if Q1 to Q4 are not equal to one equal to the input signal, the read circuit determines that not enough power supply voltage is provided and outputs a control signal that causes the power supply voltage to rise (step 408). If Q1 to Q4 are 1 equal to the input signal, the next step proceeds.

When the outputs Q1 to Q4 of the second flip-flop to the fifth flip-flop are 1 equal to the input signal, it is determined whether Q5 which is the output of the sixth flip-flop F5 is 0 (step 410). If Q5 is equal to 0 different from the input signal, it is determined that an appropriate voltage is provided for the operation of the operation circuit, and the flow proceeds to the next step. If Q5 is 1 equal to the input signal, it is determined that the power supply voltage is not the minimum voltage required for operation to generate a control signal for reducing the power supply voltage (step 412).

After performing a determination procedure on the output of the sixth flip-flop F5, it is determined whether Q6, which is the output of the seventh flip-flop F6, is 0 (step 414).

If Q6 is 0, it is determined that a voltage appropriate for the operation of the operation circuit is provided and the process proceeds to the next step. If Q6 is 1 equal to the input signal, it is determined that the power supply voltage is not the minimum voltage required for operation to generate a control signal for reducing the power supply voltage (step 412).

After the determination procedure for the output of the seventh flip-flop F6 is performed, it is determined whether Q7 which is the output of the eighth flip-flop F7 is 0 (step 416).

If Q7 is zero, the proper voltage is provided, so the supply voltage is maintained (step 418). When Q7 is 1, a control signal is generated to reduce the power supply voltage.

5 is a flowchart illustrating an operation of an operation discriminator having the configuration of FIG. 3 according to another embodiment of the present invention.

4 illustrates a case in which the input signals D0 and the output signals Q0 to Q7 are initialized to 0, and 1 is input to a subsequent input signal to compare the input signal with the output signal. Unlike FIG. 4, the input signals D0 and the output signals Q0 to Q7 may be initialized to 1, and 0 may be input as a subsequent input signal to compare the input signal with the output signal. FIG. 5 illustrates an operation in this case.

Since the procedure of FIG. 4 is the same as in FIG. 4 except that the initialization output value and the value of the input signal are changed, detailed description of FIG. 5 will be omitted.

As described above, according to the preferred embodiment of the present invention, it is possible to efficiently determine the minimum voltage required for the operation of the circuit system using a plurality of delay circuits, and only the minimum power supply voltage required for the operation of the circuit system. There is an advantage that can be provided to ensure efficient power consumption.

Claims (15)

An operation determination device for generating a control signal for controlling a power supply voltage of an operation circuit, At least one first delay means configured to delay the input signal for a time shorter than a delay time of the operation circuit; Second delay means set to delay an input signal for the same delay time as said operation circuit; At least one third delay means configured to delay the input signal for a time longer than a delay time of the operation circuit; And And reading means for generating a power supply voltage control signal for controlling said power supply voltage based on output signals of said first delay means, second delay means, and third delay means. The method of claim 1, At least one first flip-flop coupled with the at least one first delay means; A second flip flop coupled with the second delay means; And And at least one third flip-flop coupled with the at least one third delay means, wherein the first, second and third flip-flops are connected to the outputs of the first, second and third delay stages. Outputting a corresponding output signal, wherein output signals of said first, second and third flip-flops are input to said reading means. The method of claim 2, And the first, second and third flip-flops output an output signal to a next clock cycle of a clock cycle corresponding to the input signal. The method of claim 2, The reading means generates a power supply voltage control signal for raising a power supply voltage to the operation circuit if the output levels of the first flip-flop and the second flip-flop are not equal to the level of the input signal. Circuit operation determination device. The method of claim 2, And the reading means generates a power supply voltage control signal for lowering a power supply voltage to the operation circuit when the output level of the third flip-flop is not equal to the level of the input signal. . The method of claim 1, The input signal is equal to the level of the power supply voltage provided to the operation circuit, and further includes a fourth flip-flop for outputting the input signal, wherein the output signal of the fourth flip-flop is the first, second and The circuit operation discrimination apparatus input to the 3rd delay means. A circuit system capable of supply voltage control, An operation circuit for performing a preset circuit operation; A voltage variable power supply configured to supply a power supply voltage to the operation circuit and to adjust a power supply voltage level in response to a power supply voltage control signal; And an operation discriminator which determines the minimum voltage level at which the operation circuit is operable and generates the power voltage control signal to provide the voltage variable power supply so that a power supply voltage is provided at the minimum voltage level. Circuit system with voltage control. The method of claim 7, wherein And the operation discriminator includes a plurality of delay means and determines the minimum operable voltage level using a delay time variation characteristic according to a voltage level. The method of claim 8, The operation discriminator, At least one first delay means configured to delay the input signal for a time shorter than a delay time of the operation circuit; Second delay means set to delay an input signal for the same delay time as said operation circuit; At least one third delay means configured to delay the input signal for a time longer than a delay time of the operation circuit; And And a reading means for generating a power supply voltage control signal for controlling the power supply voltage based on the output signals of the first delay means, the second delay means and the third delay means. . Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9, At least one first flip-flop coupled with the at least one first delay means; A second flip flop coupled with the second delay means; And And at least one third flip-flop coupled with the at least one third delay means, wherein the first, second and third flip-flops correspond to the outputs of the first, second and third delay means. And an output signal of the first, second, and third flip-flops is input to the reading means. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, The reading means generates a power supply voltage control signal for raising a power supply voltage to the operation circuit if the output levels of the first flip-flop and the second flip-flop are not equal to the level of the input signal. A circuit system capable of controlling the power supply voltage. Claim 12 was abandoned upon payment of a registration fee. The method of claim 10, And the reading means generates a power supply voltage control signal for lowering the power supply voltage to the operation circuit if the output level of the third flip-flop is not equal to the level of the input signal. Possible circuit system. A method of controlling a power supply voltage provided to a circuit system, (A) delaying the input signal by using a power supply voltage signal provided to the circuit system as an input signal and shorter than a delay time of the circuit system; (B) delaying the input signal by a time equal to a delay time of the circuit system using a power supply voltage signal provided to the circuit system as an input signal; (C) delaying the input signal longer than a delay time of the circuit system by using a power supply voltage signal provided to the circuit system as an input signal; And (D) generating a power supply voltage control signal for adjusting a power supply voltage provided to the circuit system based on the level of the delay signal output in steps (a), (b), (c). A power supply voltage control method characterized by the above-mentioned. The method of claim 13, When the signal level delayed in step (a) and step (b) is different from the input signal level, a power supply voltage control signal is generated in step (d) to raise the power supply voltage. Control method. The method of claim 13, If the signal level delayed in the step (c) is the same as the input signal level, the power supply voltage control signal is generated in step (d) to raise the power supply voltage.

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