KR100761402B1 - Internal signal generator - Google Patents

Abstract

An internal signal generator is provided to reduce current consumption by controlling on/off of a plurality of flip flop circuits which shift an external signal in response to CAS latency. A plurality of flip flops(102) shifts an external signal in sequence. An enable signal generation part(101) generates enable signals for the flip flops respectively in response to CAS latency. An output part(103) outputs output signals of the flip flops driven in response to the enable signal as an internal signal in response to the CAS latency. The enable signal generation part includes a plurality of individual enable signal generation parts corresponding to the flip flops.

Description

Internal signal generator {INTERNAL SIGNAL GENERATOR}

1 and 2 illustrate an internal signal generator according to the prior art.

3 is a circuit diagram illustrating an internal circuit of the flip-flop of FIG. 1.

4 is a circuit diagram illustrating an internal signal generator according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating an embodiment of the flip-flop group of FIG. 4. FIG.

FIG. 6 is a circuit diagram illustrating an internal circuit of the flip flop of FIG. 5.

7 is a circuit diagram illustrating an embodiment of an enable signal generator of FIG. 4.

8 is a circuit diagram illustrating an embodiment of an output unit of FIG. 4.

9 is a circuit diagram illustrating an embodiment of an enable signal generator that responds to a cascade write latency.

Explanation of symbols on the main parts of the drawings

101: enable signal generator

102: flip flop group

103: output unit

The present invention relates to semiconductor design technology, and more particularly, to an internal signal generator of a semiconductor memory device.

The main issue in the recent semiconductor memory field is changing from integration to operating speed. As a result, high-speed synchronous memories such as synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), and RAMBUS DRAM form the mainstream of the mass production semiconductor memory market.

Synchronous memory refers to a memory that operates in synchronization with an external system clock. In the case of the SDRAM, one data input / output is performed every clock by synchronizing the input / output operation with the rising edge of the clock. In contrast, DDR SDRAM synchronizes input / output operations not only on the rising edge of the clock but also on the falling edge, enabling two data inputs / outputs every clock.

An AC index indicating the time taken for a command to be input from the DRAM to input / output valid data has a tAA characteristic. As an example of the read operation, tAA is a time taken when a read command is applied, that is, a time required to output the first valid data from the rising edge of the external clock. The smaller the value, the faster the operation. In general, DRAM products after SDRAM determine the CAS latency (CL), which is a kind of delay system that determines how many clocks after the command is applied.

If the tAA value is relatively large, the value of the cas latency CL is increased to provide a sufficient time delay until the data arrives so that valid data can be output. Conversely, if the tAA value is small, there is a greater possibility that the value of the clock latency may be smaller because valid data will arrive at the output faster. In other words, the decrease in the tAA value is closely related to the improvement in performance since the value of the tAA can be simultaneously reduced.

Meanwhile, DDR II SDRAM, the successor to DDR SDRAM, adopts Additive Latency (AL) as a standard. In a general case in which the additive latency AL is not defined, a read / write command is applied after RAS to CAS Delay (tRCD) when an active signal is applied. However, in case of the additive latency, the read / write command may be applied even before the minimum tRCD. For example, when the value of the additive latency is 2, the read / write command may be applied in advance two clock cycles before the original read / write command can be input. The adoption of this additive latency can increase the efficiency of the data bus.

1 and 2 illustrate an internal signal generator according to the prior art.

1 and 2, an internal signal generator may flip flip-flops F / F1 to F / F9 and flip-flop F / S to shift an external signal EXSIG in response to a clock signal ICLK6 (I). Transmission gates TG1 to TG7 outputting the output signals of F1 to F / F9 as internal signals INSIG in response to the cascade latency CL5 to 11 are provided.

As can be seen with reference to FIGS. 1 and 2, in the related art, a command, a bank address, and a column address transmitted from the outside are flip-flops F / F1 to F / F9. When delaying, all of the maximum number of flip-flops are shifted, and then the required one is selected in response to the cascade latency CL. That is, when the external signal EXSIG enters, the shift is made in response to the first clock signal in order.

For example, when the additive latency AL is the cascade latency CL-2, nine flip-flops F / F1 to F / F9 for shifting the external signal EXSIG are nine rising clock signals ICLK6. All work in response. Among these, the signal output from the third flip-flop F / F3 is output as the internal signal INSIG in response to the cascade latency CL0.

The external signal EXSIG may be a write command, a read command, a bank address, and a column address signal. The reset signal RST is a signal for setting initial values of the flip-flops F / F1 to F / F9.

The first clock signal ICLK6I and the second clock signal ICLK6 are internal clock signals and have the same phase, but the second clock signal ICLK6 is turned on only when the additive latency AL is not equal to zero. It is a signal.

Here, the switch SW1 for determining the connection between the first clock signal ICLK6I and the second clock signal ICLK6 is an option, and two switches having the same rising when the value of the additive latency AL are not 0 are used. One of the clock signals ICLK6I and ICLK6 is a switch SW1 to compensate for a defect. For example, when the second clock signal ICLK6 is not output, the switch SW1 is shorted to control the operation of the flip-flops F / F3 to F / F9 with the first clock signal ICLK6I.

In FIG. 2, output signals QR <1> and QR <2 of the first flip-flop F / F1 and the second flip-flop F / F2 among the output signals of the flip-flops F / F1 to F / F9. >) Is not output as the internal signal INSIG because the value of the additive latency AL is set to the cascade latency CL-2 according to the dial3 specification. This is a variable value. If the value of the additive latency AL is 0, the output signals QR <1: 9> of all the flip-flops F / F1 to F / F9 are set by the cascade latency CL. It may be selected and output as an internal signal INSIG.

In addition, the value of the cascade latency CL is a value previously set in the mode register set (MRS) unit. For example, if the value of the cas latency CL is set to 5, the logic level of CL5 is high, and the logic levels of the remaining CL6 to CL11 are low.

FIG. 3 is a circuit diagram illustrating an internal circuit of the flip flop of FIG. 1. In this case, for convenience of description, the third flip-flop F / F3 will be described as an example.

Referring to FIG. 3, an internal circuit of the third flip-flop F / F3 may include a first inverter INV3 that inverts the clock signal ICLK6 and a second inverter that inverts the output signal of the first inverter INV3. An input signal QD2 output from the second flip-flop F / F2 using the output signal of the INV4 and the first inverter INV3 and the output signal of the second inverter INV4 as gate inputs, respectively; Output signals of the first latch circuit 31 and the first inverter INV3 which latch the output signals of the first transmission gate TG8 and the first transmission gate TG8 and output them as the control signal QD3 of the subsequent flip-flop circuit. And an output signal of the second transmission gate TG9 and the second transmission gate TG9 which transmit the output signal of the first latch circuit 31 by using the output signal of the second inverter INV4 as the gate input. It is located at the input terminal of the second latch circuit 32 and the first latch circuit 31 for latching and outputting QR3 in response to the reset signal RST. The NMOS transistor N1 may reset the third flip-flop F / F3.

The internal circuit of the third flip-flop F / F3 is the same as the internal circuit of the other flip-flops F / F1 to F / F2 and F / F4 to F / F9. At this time, the last flip-flop (F / F9) does not output the transmission signal (QD).

Briefly, the first transmission gate TG8 and the second transmission gate TG9 are sequentially operated in response to the clock signal ICLK6 that is constantly toggled.

Therefore, the second transmission signal QD2 input is output by the third transmission signal QD3 after half a clock.

Then, the third transmission signal QD3 passes by half a clock and outputs the internal signal QR13.

Here, the signal input by the inverter constituting the latch circuits 31 and 32 is switched in accordance with the input voltage level of the inverter whenever passing through the latch circuits 31 and 32.

At this time, if it is assumed that the value of the cascade latency (CL) is set to 5-generally, the internal signal generator is operated based on the additive latency (AL) = cascade latency (CL). The operation of the flip-flops F / F5 to F / F9 below the fourth flip-flop F / F4 is a meaningless state in which current is wasted by switching operation of the latch circuit with respect to the input signal as described above. Problems arise.

This is a problem that occurs when the internal signal INSIG is output below the maximum number of flip-flops provided. In the same sense, this is a problem that occurs when outputting the internal signal INSIG generated by the additive latency AL smaller than the maximum additive latency AL.

In addition, since all addresses transmitted from the outside as well as the commands transmitted from the outside are generated as internal signals, a large amount of current can be wasted at once.

In addition, in the above description, the additive latency AL is mainly described. However, the light latency WL and the cascade light latency CWL have the same shape.

Therefore, a large amount of current is wasted when the external signal EXSIG is shifted to generate the internal signal INSIG.

The present invention has been proposed to solve the above problems of the prior art, an internal signal generator for reducing the current consumption by controlling the on / off of a plurality of flip-flop circuit for shifting the external signal in response to the cas latency Its purpose is to provide.

According to an aspect of the present invention for achieving the above technical problem, a plurality of flip-flops for sequentially shifting an external signal, the enable signal for generating an enable signal of each of the plurality of flip-flop in response to the cas latency An internal signal generator includes a generator and an output unit configured to output an output signal of the plurality of flip-flops driven in response to the enable signal as an internal signal in response to the cas latency.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

4 is a circuit diagram illustrating an internal signal generator according to an embodiment of the present invention.

Referring to FIG. 4, the internal signal generator enables to turn on / off the flip-flop selected by the cascade latency CL of the flip-flop group 102 and the flip-flop group 102 to shift the external signal EXSIG. The output signal of the signal generator 101 and the flip-flop group 102 may be implemented by the output unit 103 outputting the internal signal INSIG in response to the cascade latency CL.

Here, the enable signal generation unit 101 receives different cas latencies CL <0: n> as inputs, and includes a number of individual enable signal generation units corresponding to the flip-flops in the flip-flop group 102. .

In addition, the flip-flop group 102 is a plurality of flip-flops connected in a chain form. The flip-flop group 102 receives an output signal of a front flip-flop as an input and transfers its output signal as an input signal of a rear flip-flop. Shift to The clock signal ICLK6I, the reset signal RST for resetting each flip-flop, the output signal ENB <0: n> of the enable signal generator 101, and the external signal are used as control signals of each flip-flop. Input (EXSIG).

In addition, the output unit 103 inputs the cascade latency CL <0: n> having a different value from the output signal QR <0: n> of the flip-flop group 102. In this case, n is a natural number.

Next, an embodiment of each component will be described in detail.

5 is a block diagram illustrating an embodiment of the flip-flop group 102 of FIG. 4.

Referring to FIG. 5, the flip-flop group 102 may be implemented by nine flip-flop circuits F / F11 to F / F19 for sequentially shifting the external signal EXSIG.

Here, the first flip-flop (F / F11) and the second flip-flop (F / F12) is always turned on when generating the internal signal, the remaining flip-flop (F / F13 ~ F / F19) is the enable signal generator 101 Is turned on / off by the output signals ENB1 to ENB7.

Here, the two flip-flops (F / F11, F / F12) are always on is the basic specification of the dial 3, the additive latency (AL) and the light latency (WL) value is the cascade latency (CL) -2 default This is because

Accordingly, the on / off of the upper two flip-flops F / F11 and F / F12 circuit maintains the shifting operation of the basic two clocks by always connecting the power supply voltage VDD.

This is changeable as the additive latency (AL) and light latency (WL) values change. For example, when the additive latency AL and the write latency WL are 0, the on / off operation of all the flip-flops F / F11 to F / F19 is controlled.

Here, the switch SW2 for determining the connection between the first clock signal ICLK6I and the second clock signal ICLK6 is an option, and two switches having the same rising when the value of the additive latency AL are not 0 are used. One of the clock signals ICLK6I and ICLK6 is a switch SW1 to compensate for a defect. For example, when the second clock signal ICLK6 is not output, the switch SW2 is shorted to control the operations of the flip-flops F / F13 to F / F19 with the first clock signal ICLK6I.

Here, the internal circuits of the flip-flops F / F11 to F / F19 are as follows.

FIG. 6 is a circuit diagram illustrating an internal circuit of the flip-flops F / F11 to F / F19 of FIG. 5.

Referring to FIG. 6, the internal circuit of the flip-flop (one of F / F11 to F / F19) has a NAND for inputting a clock signal ICLK6 (I) and an enable signal ENB <1: 7> or VDD. Inverter INV59 that inverts the output signals of the gate NAND51 and NAND51, the output signal of the NAND51 and the output signal of the inverter INV59 are the gate inputs, respectively, to the external signal EXSIG or QD. A first transmission gate (TG51) for transmitting <1: 8> and a first signal for latching an output signal of the first transmission gate (TG51) and outputting the input signal (QD <1: 8>) of a subsequent flip-flop circuit. A second transmission gate TG52 which transfers the output signal of the first latch circuit 201 using the latch circuit 201, the output signal of the NAND gate NAND51 and the output signal of the inverter INV59 as their respective gate inputs, Inputs of the second latch circuit 202 and the first latch circuit 201 latching the output signal of the second transmission gate TG52 to output QR <11:19. Located in the end it can be implemented as a NMOS transistor (N51) for resetting the flip-flop in response to a reset signal (RST).

Referring to the third flip-flop (F / F13) as an example, a brief operation will be described below.

First, for example, when the first enable signal ENB1 is at a logic level high, toggling is maintained even when the toggling clock signal ICLK6 crosses the NAND gate NAND51. In response to this, the first transmission gate TG51 and the second transmission gate TG52 are sequentially operated.

Accordingly, the second transmission signal QD2 shifted by the external signal EXSIG is output as the third transmission signal QD3 after passing by half a clock.

Then, the third transmission signal QD3 passes by half a clock and outputs the internal signal QR13.

In another case, for example, when the first enable signal ENB1 is at a logic level low, when the toggling clock signal ICLK6 crosses the NAND gate NAND51, the logic is determined by the first enable signal ENB1. This is a single level signal that is level high.

Therefore, the first transmission gate TG51 does not operate, and only the second transmission gate TG52 operates.

Since the first transmission gate TG51 is not operated, the second transmission signal QD2 to which the external signal EXSIG is shifted is not transmitted to the first latch circuit 201. Accordingly, the output terminal of the first latch circuit 201 is in a floating state, and the second transmission gate TG52 which transfers the same is operated, and the output of the second latch circuit 202 is also in a floating state.

Here, since the first latch circuit 201 and the second latch circuit 202 do not perform a switching operation, the current consumption can be reduced.

FIG. 7 is a circuit diagram illustrating an embodiment of the enable signal generator 101 of FIG. 4.

Referring to FIG. 7, the enable signal generation unit 101 buffers the cas latency 11 (CL11) having a cas latency value of 11 (hereinafter referred to as cas latency X), where X represents a substantial cas latency value. And a first inverter INV51 and a second inverter INV52 outputting the first enable signal ENB9. The output signal of the first nor gate NOR51 and the first nor gate NOR51 that input the cas latency 11 CL11 and the cas latency 10 CL10 is inverted and output as the second enable signal ENB8. And a third inverter INV53. The third enable signal ENB7 is inverted by inverting the output signal of the second nor gate NOR52 and the second nor gate NOR52 that input the output signal of the third inverter INV53 and the cascade latency 9 CL9. A fourth inverter (INV54) output to the). In addition, the fourth enable signal ENB6 is inverted by inverting the output signal of the third inverter gate NOR53 and the third norgate NOR53 which input the output signal of the fourth inverter INV54 and the cascade latency 8 CL8. A fifth inverter (INV55) output to the) is included. In addition, the fifth enable signal ENB5 is inverted by inverting the output signal of the fourth nor gate NOR54 and the fourth norgate NOR54 that input the output signal of the fifth inverter INV55 and the cascade latency 7 CL7. The sixth inverter (INV56) output to the). The sixth enable signal ENB4 is inverted by inverting the output signals of the fifth nor gate NOR55 and the fifth norgate NOR55 which input the output signal of the sixth inverter INV56 and the cascade latency 6 CL6. The seventh inverter (INV57) output to the). The seventh enable signal ENB3 is inverted by inverting the output signal of the sixth north gate NOR56 and the sixth north gate NOR56 which input the output signal of the seventh inverter INV57 and the cascade latency 5 CL. A fourth inverter (INV54) output to the). Here, the cascade latency value is only a specification value according to the embodiment, and can be changed according to a setting.

The enable signal generation unit 101 configured as described above determines the activation or deactivation of the enable signals ENB3 to ENB9 according to the set cascade latency value. This is shown in the table below.

Table 1

CL6 CL5 CL4 CL3 CL2 CL1 CL0 ENB9 ENB8 ENB7 ENB6 ENB5 ENB4 ENB3 0 0 0 0 0 0 One 0 0 0 0 0 0 One 0 0 0 0 0 One 0 0 0 0 0 0 One One 0 0 0 0 One 0 0 0 0 0 0 One One One 0 0 0 One 0 0 0 0 0 0 One One One One 0 0 One 0 0 0 0 0 0 One One One One One 0 One 0 0 0 0 0 0 One One One One One One One 0 0 0 0 0 0 One One One One One One One

                          ※ 1 = logic level high, 0 = logic level low

As shown in Table 1 above, when a large number of flip-flops F / F11 to F / F19 should be operated due to a high cas latency value, many enable signals ENB3 to ENB9 are activated to correspond to the cascade latency. When the small values of the flip-flops F / F11 to F / F19 are to be operated due to the low values, the small enable signals ENB3 to ENB9 are activated to correspond thereto.

8 is a circuit diagram illustrating an embodiment of the output unit 103 of FIG. 4.

Referring to FIG. 8, the output unit 103 may include transmission gates TG53 to TG59 and a plurality of transmission gates provided in the number corresponding to the output signals QR <13:19> of the flip-flop group 102. Two inverters INV59 and INV60 are provided which buffer the output signals of TG53 to TG59 and output them as internal signals INSIG.

 At this time, the output signals QR11 and QR12 of the upper two flip-flops F / F11 and F / F12 of the flip-flop group 102 are not outputted because the value of the additive latency in this embodiment is the cas latency. This is because (CL) -2. That is, since two clocks are moved to the basis of the clock signal ICLK6, they do not need to be output.

If the value of the additive latency is 0, the output signals QR <11:19> of all the flip-flops F / F11 to F / F19 are output.

The plurality of transmission gates TG53 to TG59 operate according to the cascade latency values CL5 to CL11. That is, the signals QR13 to QR19 output from the flip-flop group 102 are selectively output by the cas latency value set in advance in the MRS (Mode Register Set).

The foregoing description focuses on the additive latency, but the light latency and the cascade light latency CWL have the same form. That is, the flip-flop of the flip-flop group is controlled on / off by the enable signal generated in response to the cascade latency value. Accordingly, the internal signal is inputted according to the set light latency value of the external signal inputted to the flip-flop group. To print.

As described above, the additive latency AL, the light latency WL, and the cascade light latency CWL have the same shape because three latencies are basically determined according to the cascade latency CL. In this case, the case of the CAS write latency CWL is a latency that replaces the CAS latency when the write operation is performed in the DRAM more advanced than the DI3. In this case, when the enable signal is generated, the enable signal generator 101 receives the caslight latency CWL as an input instead of the cascade latency CL to generate the enable signal ENB. This will be more apparent with reference to FIG. 9. In this case, it is preferable that the enable signals ENB3 to ENB6 generated are generated in a number corresponding to the number of flip-flops provided. That is, in FIG. 9, the circuit is suitable for an internal signal generator having four flip-flops.

In summary, the internal signal generator according to the present invention includes a plurality of flip-flops 102 and a cascade latency CL for sequentially shifting an external signal in response to an additive latency AL in order to reduce current consumption in generating an internal signal. Enable signal generator 101 for generating enable signal ENB of each of flip-flops 102 and output signals of the flip-flops as internal signals in response to cascade latency CL. An output unit 103 for outputting is provided.

Therefore, in the present invention, in contrast to the conventional case which causes a problem in that current consumption is increased due to unnecessary flip-flop driving when generating an internal signal, in the present invention, it is unnecessary by the enable signal ENB generated by the cascade latency CL. The conventional problem is solved by preventing the flip-flop from being driven. In this case, not only the additive latency AL, but also the light latency WL and the caslight light latency CWL may be generated through the internal signal generator of this type, and current consumption may be reduced.

Here, the substantial reduction in the current consumption is caused by the latch circuit in the flip-flop not switching.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, since the type and arrangement of the logic used in the above-described embodiment is implemented as an example in which both the input signal and the output signal are high active signals, the implementation of the logic may also change when the active polarity of the signal is changed. There is no such embodiment, because the number of cases is too large, and the change in the embodiment is a matter that can be easily technically inferred by those skilled in the art of the present invention belongs directly to each case I will not mention it.

As described above, the present invention prevents unnecessary flip-flops from being driven by the enable signal ENB generated by the cascade latency CL, which increases the current consumption due to unnecessary flip-flops when an internal signal is generated. Solve.

Therefore, an internal signal generation time that can reduce current consumption can be obtained, and an effect of reducing power consumption of a semiconductor memory device including the same can be obtained.

Claims (6)

A plurality of flip-flops for sequentially shifting external signals; An enable signal generator configured to generate an enable signal of each of the plurality of flip-flops in response to a cas latency; And An output unit for outputting the output signals of the plurality of flip-flops driven in response to the enable signal as internal signals in response to the cas latency Internal signal generator comprising a. The method of claim 1, The enable signal generator comprises a plurality of individual enable signal generators corresponding to the plurality of flip-flops. The method of claim 1, The plurality of flip-flops are connected in a chain form to take an output signal of the front flip-flop as an input, and transfer its output signal as an input signal of the rear flip-flop to shift the first external signal sequentially. Internal signal generator. The method of claim 3, The flip flop, A first NAND gate configured to receive a clock signal and the enable signal; A first inverter for inverting the output signal of the first NAND gate; A first transmission gate configured to transfer the external signal (or an output signal of a front flip-flop with an external signal shifted) by using the output signal of the first NAND gate and the output signal of the first inverter as a gate input; A first latch circuit for latching an output signal of the first transmission gate and outputting it as an input signal of a subsequent stage; A second transmission gate configured to transfer an output signal of the first latch circuit by using the output signal of the first NAND gate and the output signal of the first inverter as a gate input; And A second latch circuit for latching an output signal of the second transmission gate to output a shifting signal (a signal in which an external signal is shifted) Internal signal generator comprising a. The method of claim 2, And the individual enable signal generator is configured to input cas latency having different values. The method of claim 1, The output unit, And a plurality of transmission gates for transmitting output signals of the plurality of flip-flops with the cas inputs having different values as gate inputs.

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