KR100753504B1 - In-loop Deblocking Filter System and method for filterring data using the same - Google Patents

Abstract

An in-loop deblocking filter system of a video decoder and a filtering method thereof, comprising: an external memory to which pixel data is written, an internal buffer of a predetermined size to which previously filtered previous pixel data is written, and current pixel data to be filtered. An internal memory having a main memory having a predetermined predetermined size, reading the current pixel data to be filtered from the external memory, writing the current pixel data to be filtered to the main memory of the internal memory, and the current pixel data written to the main memory. A filter engine that performs filtering, writing previous pixel data of the filtered internal buffer and a portion of the current pixel data of the filtered main memory to the external memory, and writing the current pixel data of the remaining main memory to the internal buffer. It is configured to include.

Internal buffer, internal memory, external memory, main memory, pixel data

Description

In-loop Deblocking Filter System and method for filterring data using the same}

1 illustrates a general deblocking filtering method

2 is a diagram illustrating a pixel data configuration required for general filtering.

3 and 4 illustrate reading and writing of general pixel data.

5 illustrates a general block edge filtering method.

6 is a diagram illustrating the number of pixel data reads and writes for each block in the general filtering method.

7 shows a filter system and an interface scheme according to the invention.

8 illustrates reading and writing of pixel data according to the present invention.

9 illustrates a block edge filtering method according to the present invention.

10 is a diagram illustrating the number of pixel data reads and writes for each block in the filtering method according to the present invention.

Explanation of symbols for main parts of the drawings

1: external memory 2: SDRAM controller

3: Arbitrator 4: MAU

5: internal memory 6: filter engine

The present invention relates to an in-loop deblocking filter system, and more particularly, to an in-loop deblocking filter system of a video decoder and a filtering method thereof.

In general, advances in digital signal processing, storage media, and transmission methods have enabled various multimedia services including information such as still images and moving images from services limited to voice information, thereby providing an opportunity for users to access rich information. .

With these developments, various compression schemes for storing and transmitting huge amounts of video information have been studied. Especially, with the rapid spread of new communication channels such as mobile communication networks, video encoding schemes have improved compression efficiency compared to conventional compression methods. The necessity of the necessity and the necessity of the improved video standard to cope with the new communication environment such as the coexistence of various existing communication infrastructures emerged.

Following this trend, the ITU-T standardization body approved the standard named H.264 in May 2003, and in August, the standard named MPEG-4 Part 10 by ISO / IEC.

The H.264 standard offers high compression performance and improved motion prediction and compensation, inconsistent block transform, in-loop deblocking filter, improved entropy coding, and adaptability to various networks. While having the advantage of flexibility, the complexity of encoder and decoder is much higher than that of existing standards.

In particular, on the encoder side, much more parameters and coding modes have to be determined than on the existing standard. On the decoder side, the burden of computational amount due to in-loop deblocking filter or motion compensation in 1/4 pixel unit is much higher than the existing standard. Increased.

Therefore, in order for H.264 to be widely used in the real market, it is important to understand the principles and techniques of H.264 and to implement and apply the technology to efficiently implement the encoder and the decoder.

In particular, the in-loop deblocking filter, which is not included in the existing standard, is not only the largest amount of computation required among the H.264 video decoders, but also a very frequent memory transaction. As a result, not only does it require a large number of clock cycles when implemented in software on a conventional general purpose processor (DPP) or DSP, or in hardware, but also consumes a lot of power. It is well known as a required part.

Briefly, the deblocking filter algorithm required by the H.264 specification is as follows.

As shown in FIG. 1, the deblocking filter of H.264 performs separate filtering on luma and chroma based on one macroblock (MB) and blocks the boundaries of a picture. Conditional filtering is performed on all 4x4 block edges except edges of the macroblock corresponding to (Boundary) or the case where the filtering is intentionally disabled.

In order to filter, as shown in FIG. 1, the vertical edge filtering is performed from left to right in both luma and chroma (1) (3), and then horizontally progressed from top to bottom. Edge filtering (2) (4) is performed.

The memory usage required for filtering is shown in FIG. 2.

First, 16x16 pixel data (1) size memory is used for luma in the current macroblock (Current MB), and 8x8 pixel data (2) for chroma. Memory of size is required for Cb and Cr respectively.

For the left macroblock (Left MB) for vertical edge filtering, a 4x16 pixel data size (3) for Luma and a 2x8 pixel data size (4) for Chroma for Cb and Cr Each is required.

Also note that for horizontal edge filtering, Luma 16X4 pixel data size (5) and Chroma 8x2 pixel data size (6) for Upper MB are required for Cb and Cr, respectively. Can be.

As such, the pixel data required for filtering has to be read from the external memory into the internal memory and written from the internal memory to the external memory when the deblocking filter is implemented.

In addition, when filtering, it has to be read from the internal memory in order of edge filtering, filtered, and then stored again.

Therefore, access to external memory occurs frequently, and access to internal memory occurs frequently.

In addition, filtering requires a tremendous amount of computational work to add, subtract, multiply, and divide each pixel data.

Therefore, frequent access to external memory is the most influential factor in clock count and power consumption, and the number of accesses and access methods to internal memory are also important factors in determining system performance. Efforts to use are very important in implementing deblocking filters.

An object of the present invention is to provide an in-loop deblocking filter system of a video decoder having a high performance and a low power characteristic and a filtering method thereof by improving an access method for an external memory and a filtering method for an internal memory.

The in-loop deblocking filter system of the video decoder according to the present invention comprises an external memory to which pixel data is written, an internal buffer of a predetermined size to which previously filtered previous pixel data is written and a predetermined size to which the current pixel data to be filtered is written. Reading an internal memory having a main memory of < RTI ID = 0.0 > and < / RTI > Filtering data; writing previous pixel data of the filtered internal buffer and a portion of the current pixel data of the filtered main memory to the external memory; and writing current pixel data of the remaining main memory to the internal buffer. It is configured to include a filter engine to perform the writing step.

Here, in the case of Luma of the internal memory, the internal buffer is 4x20 size, the main memory is 16x20 size, and in the case of Chroma of the internal memory, the internal buffer is 2x10 size, and the main memory Is preferably an 8x10 size.

The internal buffer of the luma consists of a 4x16 left macroblock and a 4x4 left upper MB. The main memory of the luma is a 16x16 current macroblock and 16x4. It may consist of an upper macroblock.

In addition, the internal buffer of the chroma is composed of 2x8 left upper macroblocks and 2x2 left upper macroblocks, and the main memory of chroma is 8x8 current macroblocks. MB) and an 8 × 2 upper macro block (Upper MB).

An SDRAM controller, an arbiter, and a memory access unit (MAU) are configured between the external memory and the internal memory, and pixel data of the external memory and the internal memory are stored in the memory. It can be moved via the DRAM controller, the arbiter and the memory access unit.

A filtering method of an in-loop deblocking filter system of a video decoder according to the present invention includes reading current pixel data to be filtered from the external memory, and writing the read current pixel data to a main memory of the internal memory. Filtering current pixel data written to the main memory, writing previous pixel data of the filtered internal buffer and a portion of the current pixel data of the filtered main memory to the external memory; And writing current pixel data of a memory to the internal buffer.

Here, prior to the step of reading current pixel data to be filtered from the external memory, the step of requesting to read the pixel data of the external memory may be further performed, and before the step of filtering the current pixel data written to the main memory. In addition, the method may further include receiving a read completion signal of the current pixel data.

Further, before writing the previous pixel data of the filtered internal buffer and a part of the current pixel data of the filtered main memory to the external memory, a step of requesting to write the filtered pixel data to the external memory may be further performed. And after writing the current pixel data of the remaining main memory to the internal buffer, receiving a write completion signal of the filtered pixel data.

The filtering of the current pixel data written in the main memory may include sequentially performing vertical edge filtering from the pixel data of each block located in the first row of the main memory to the pixel data of each block located in the last column. performing vertical edge filtering, and sequentially horizontal edge filtering from pixel data of each block located in the first row of the main memory to pixel data of each block located in the last column. It is preferable to include the step of performing.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

The present invention proposes an effective implementation method for the external memory and the internal memory.

Accordingly, the present invention intends to perform an external memory access by using a buffer inside the filter as a method for reducing the number of clocks and reducing power consumption.

By utilizing the buffer inside the filter, the present invention allows all pixel data necessary for filtering to be read and written from the external memory using only one read transaction and one write transaction.

Through the use of the buffer inside the filter, the present invention can improve the data transfer speed by reducing the amount of data transferred for transactions during read and write transactions to the external memory as compared with the conventional method.

In the present invention, the block edge filtering order is changed and filtered to reduce the number of accesses to the internal memory.

3 is a diagram illustrating an in-loop deblocking filter system of a video decoder according to the present invention, and shows an example of an interface scheme between a deblocking filter and an external memory.

As shown in FIG. 3, the present invention is largely composed of an external memory 1, an internal memory 5, and a filter engine 6. As shown in FIG.

Here, the internal memory 5 has an internal buffer 5a of a predetermined size to which previously filtered previous pixel data has been written, and a main memory 5b of a predetermined size to which the current pixel data to be filtered is written.

In addition, an SDRAM controller 2, an arbiter 3, and a memory access unit (MAU) 4 are formed between the external memory 1 and the internal memory 5. The pixel data of the external memory 1 and the internal memory 5 may move through the SDRAM controller 2, the arbiter 3, and the memory access unit 4.

Meanwhile, in the luma of the internal memory 5 of the present invention, as shown in FIG. 8, the internal buffer 5a has a size of 4x20, the main memory 5b has a size of 16x20, and the chroma of the internal memory ( In the case of Chroma, the internal buffer 5a is 2x10 size, and the main memory 5b is 8x10 size.
In the present invention, the luma or luma area is an area allocated to process brightness values in the internal memory 5, and the chroma or chroma area is a color in the internal memory 5. It may be an area allocated for processing a value.

Here, the internal buffer 5a of the luma is composed of a 4x16 left upper macroblock (Left Upper MB) and a 4x4 left upper macroblock (Left Upper MB), and the main memory 5b of the luma is 16x16 present. It consists of a macroblock and a 16x4 upper macroblock.

The internal buffer 5a of Chroma is composed of 2x8 left macroblocks (Left Upper MB) and 2x2 left upper macroblocks (Left Upper MB), and the chroma main memory 5b is 8x8 present. It consists of a Macroblock (Current MB) and an 8x2 Upper Macroblock (Upper MB).

Thus, the filtering method of the present invention configured as follows.

First, the filter engine 6 requests the external memory 1 to read pixel data through the memory access unit 4, the arbiter 3, and the SDRAM controller 2.

Next, the pixel engine 6 reads the current pixel data to be filtered from the external memory 1, and as shown in Fig. 8, reads the read current pixel data into the main memory 5b of the internal memory 5 (dotted line). 8 areas marked with).

Then, the filter engine 6 receives the read completion signal of the current pixel data through the memory access unit 4, and then filters the current pixel data written in the main memory 5b.

Here, as shown in FIG. 9, the pixel engine 6 sequentially processes the pixel data of each block located in the first row of the main memory 5b to the pixel data of each block located in the last column. Perform vertical edge filtering, and sequentially perform horizontal edge filtering from pixel data of each block located in the first row of main memory to pixel data of each block located in the last column. Do this.

Subsequently, the filter engine 6 requests to write the filtered pixel data to the external memory 1, and as shown in FIG. 8, the previous pixel data of the filtered internal buffer 5a and the filtered main memory ( Part of the current pixel data (7 areas indicated by dotted lines) of 5b) is written to the external memory.

Then, the filter engine 6 writes the current pixel data of the remaining main memory 5b to the internal buffer 5a and receives a write completion signal of the filtered pixel data from the external memory 1, thereby completing the filtering process. do.

As such, as illustrated in FIG. 7, the filter engine 6 of the present invention requests a macroblock read request to read pixel data of a macroblock to be filtered from the external memory 1 to the internal memory 5. Do this.

By this request, the pixel data is internal from the external memory 1 via the SDRAM Controller 2, the Arbiter 3 and the Memory Access Unit (MAU) 4 interface. Read into memory (5).

When this series of reading transactions is completed, the memory access unit 4 sends a read completion signal to the filter engine indicating that the reading of the data is completed, and the filter engine 6 having received the signal is described above. Filtering begins by order.

When filtering is started after the data for filtering is completed in the internal memory, the filter engine 6 starts filtering through internal memory access, and after filtering is completed, the macroblock pixel data from which the filtering is completed is restored from the internal memory 5 again. Perform a macroblock write request to download to 1).

By this request, the pixel data is transferred from the internal memory 5 to the external memory 1 via an interface consisting of the memory access unit 4, the arbiter 3, and the SDRAM controller 2 as opposed to the read request. When the download is completed and the write completion signal is transmitted to the filter engine 6 when the download is completed, the filtering is completed in one macroblock.

As described above, the read or write transaction process for the external memory 1 requires a read or write request and a read or write completion process, which play a very important role in transferring data.

However, since this procedure is required by all the blocks to interface the external memory 1, the more blocks that require such a request exist in the system, the longer it takes to complete a transaction.

Therefore, assuming that the data to be transmitted is the same, an effort to reduce the number of transactions for reading or writing to the external memory 1 is a very important factor in implementing a high performance deblocking filter.

3 and 4 illustrate an example of a read or write transaction with an external memory which is most commonly used when implementing an in-loop deblocking filter.

First, to perform filtering on the current macroblock, the current macroblock (1) (2), the left macroblock (Left MB) (3) (4), and the upper macroblock as shown in FIG. Pixel data for (Upper MB) (5) (6) must be read or written from the external memory (1).

Such a read or write transaction may be implemented very differently depending on how the system is implemented. However, as shown in FIG. 3, the current macroblock (Current MB) and the current macroblock in the case of luma are shown as a method for reducing the number of transactions. Read and write the upper macroblock (Upper MB) for 16x20 at the same time, and then read or write the left macroblock (Left MB) for the current macroblock in 4x16 size separately, as shown in Figure 4 or the current macroblock and the current macro. The main method is to read or write the left macro block for the block simultaneously in 20x16 size, and then read or write the top macroblock for the current macroblock separately in 16x4 size later.

That is, it can be seen that at least two transactions must occur to complete one macroblock filtering.

However, the filtering method to be mentioned through the present invention is a method that can reduce the number of read or write transactions to the external memory (1) and reduce the data size for the transaction, the internal buffer (1) as shown in FIG. (2) was used. Looking at the biggest difference, it can be seen that in the case of Luma, 4x20 size internal buffer 1 is used, and in case of Chroma, 2x10 size internal buffer 2 is used for filtering. It can be seen that Luma 4x4 Left Upper MB (3) and Chroma 2x2 Left Upper MB (4) that were not in Figure 4 were used for filtering.

First, the most direct reason for using this buffer is as follows.

Due to the nature of filtering in the implementation of the deblocking filter, the four block pixels 5 and 6 of the right edge of the current macroblock are used as the left macroblock again when filtering the next macroblock.

Therefore, these four pixel data are used for the current macroblock filtering but also used simultaneously for the next macroblock filtering.

Therefore, this pixel data must be written once to the external memory when the current macroblock filtering is completed and then read again at the next macroblock processing. .

Therefore, in the present invention, the pixel data is temporarily stored in a buffer.

Secondly, a feature of the present invention is that the internal buffer is not used in size 4x16 but in size of 4x20. This is to reduce the conventional read or write transaction to external memory from two to one as shown in FIG. It is used by.

If a buffer of such a size is used, as shown in FIG. 8, in the case of a read transaction, when reading the 16x20 pixel data 8 consisting of the current macroblock and the upper macroblock of the current macroblock in the case of luma, In the case of chroma, the 8 × 10 pixel data 10 including the current macroblock and the upper macroblock of the current macroblock may be read as in the case of luma.

In the case of the write transaction of the present invention, a special read and write transaction is performed.

An example of Luma looks like this:

The existing write transaction method filters the data read through the read transaction and uses the data as it is in the write transaction.

However, the write transaction to be mentioned through the present invention combines 4x20 size pixel data in the internal buffer with pixel data composed of 12x20 size from the left of the pixel data of the current macroblock to create a new type of pixel data. It can be used in one transaction.

Therefore, compared with the conventional write transaction, the number of write transactions can be reduced to one time.

In addition, the proposed method through the present invention shows the amount of data transmitted between the external memory and the internal memory when performing a read or write transaction as compared with the conventional method, as shown in FIG. In the case of Chroma, it is possible to reduce the size by 2x8 pixel data size.

Therefore, the external memory access has the advantage of improving the transmission speed of the pixel data by the size of the reduced data.

As mentioned above, in the conventional filtering system, after the transfer of pixel data from the external memory to the internal memory is completed, the filtering of each block edge as shown in FIG. 5 is performed in order.

As described above, in the in-loop deblocking filter, vertical filtering in which the filtering order is performed from left to right is performed first, and then horizontal filtering is performed from top to bottom.

Therefore, the filtering is performed in the order numbered in Fig. 5 for luma and chroma (1) and (2), and each time edge filtering is performed, the pixel data for each block is read and written from the internal memory several times. It can be seen that it is repeated.

Therefore, in the existing filtering system, when the number of read and write repetitions for each block pixel data is counted, a result as shown in FIG. 6 may be obtained.

As can be seen in Figure 6, in the conventional filtering method, the left macroblock (Left MB) and the upper macroblock (Upper MB) are counted once for the read (R) and the write (W), and the current macroblock (Current MB) ) Can be counted four times (1) or three times (2) (3) and twice (4).

However, the present invention uses a filtering method as shown in FIG. 9 to reduce the number of read and write counts for the internal memory.

In this method, the edge filtering order is changed in the existing filtering method. When the edge filtering is performed in the order of the sequence listed in FIG. 9 (1) and (2), the number of reads or writes as shown in FIG. 10 can be obtained.

6 and 10, the number of reads and writes for each area is reduced by two for each of the nine blocks for the number of read and write areas for area (1), and for areas (2) and (3). It can be seen that the number of reads and writes decreased once for every six blocks.

Therefore, it can be seen that it has a feature of maintaining the pixel data dependency on the existing filtering method while reducing the number of reads or writes to the internal memory relatively more than the conventional filtering method.

As described above, the present invention can apply an efficient access method to the external memory and the internal memory when implementing the in-loop deblocking filter, thereby reducing the number of read or write transactions to the external memory and reducing the data size for the transaction. It is intended to provide a way to reduce the number of reads or writes for internal memory access.

In particular, since the part related to memory access is a very important factor in determining the performance and power consumption of the filter system, the filter implementation method proposed by the present invention has a very advantageous advantage in implementing a high performance low power filter.

The present invention provides a 4x20 size luma internal buffer and a 2x10 size chroma internal buffer to preserve the feature that the four block pixels on the right edge of the current macroblock are used as the left macroblock again when filtering the next macroblock. By using, the number of read and write transactions to external memory can be processed at once, and for read or write transactions for each macroblock, the data amount of 4x16 pixel data size for luma, In this case, by reducing the amount of data transfer by the 2x8 pixel data size, the transfer speed to the external memory can also be improved.

The present invention also converts and filters the conventional block edge filtering order to reduce the number of read and write counts for the internal memory.

This method changes the order of block edge filtering in particular, while maintaining the processing dependency on the existing pixel data, so that the same filtering as the existing method can be performed without any additional implementation procedure. Compared to the method, the method can significantly reduce the number of reads or writes to the internal memory, which is a very effective deblocking filter implementation method.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (11)

An external memory to which pixel data is written; An internal memory having an internal buffer of a predetermined size to which previously filtered previous pixel data has been written, and a main memory of the predetermined size to which the current pixel data to be filtered is written; And, Reading current pixel data to be filtered from the external memory, writing the current pixel data to be filtered to the main memory of the internal memory, filtering current pixel data written to the main memory, and filtering the And a filter engine for writing previous pixel data of an internal buffer and a portion of the current pixel data of the filtered main memory to the external memory, and writing the current pixel data of the remaining main memory to the internal buffer. An in-loop deblocking filter system of a video decoder. The internal buffer of claim 1, wherein the internal buffer has a size of 4 × 20, the main memory has a size of 16 × 20, and the internal buffer has a size of Chroma in the internal memory. 2x10 size and the main memory is 8x10 size in-loop deblocking filter system of the video decoder. The internal buffer of the luma region is configured of a 4x16 left upper macroblock and a 4x4 left upper macroblock. An in-loop deblocking filter system of a video decoder, characterized by consisting of a 16x16 current macroblock and a 16x4 upper macroblock. 3. The chroma buffer of claim 2, wherein the internal buffer of the chroma region comprises 2 × 8 left upper macroblocks and 2 × 2 left upper macroblocks. An in-loop deblocking filter system of a video decoder, comprising 8x8 current macroblocks (Current MB) and 8x2 upper macroblocks (Upper MB). The memory device of claim 1, wherein an SDRAM controller, an arbiter, and a memory access unit (MAU) are configured between the external memory and the internal memory. In-loop deblocking filter system of a video decoder, wherein the pixel data is moved through the SDRAM controller, the arbiter and a memory access unit. An in-loop deblocking filter system of a video decoder comprising an external memory with pixel data written therein, an internal memory with already filtered previous pixel data written therein and a main memory with current pixel data written filtered out. In the filtering method, Reading current pixel data to be filtered from the external memory; Writing the read current pixel data to a main memory of the internal memory; Filtering current pixel data written to the main memory; Writing previous pixel data of the filtered internal buffer and a portion of the current pixel data of the filtered main memory to the external memory; And writing the current pixel data of the remaining main memory to the internal buffer. 7. The in-loop deblocking filter of a video decoder according to claim 6, further comprising the step of requesting to read the pixel data of the external memory prior to reading the current pixel data to be filtered from the external memory. How to filter the system. 7. The in-loop deblocking of a video decoder of claim 6, further comprising receiving a read completion signal of the current pixel data before filtering the current pixel data written to the main memory. How to filter the filter system. The method of claim 6, wherein before the writing of the previous pixel data of the filtered internal buffer and a part of the current pixel data of the filtered main memory to the external memory, a write request is performed to the external memory. And further performing the steps of filtering the in-loop deblocking filter system of the video decoder. 7. The method of claim 6, further comprising receiving a write completion signal of the filtered pixel data after writing the current pixel data of the remaining main memory to the internal buffer. -Filtering method of the loop deblocking filter system. The method of claim 6, wherein the filtering of the current pixel data written to the main memory comprises: Performing vertical edge filtering sequentially from pixel data of each block located in the first row of the main memory to pixel data of each block located in the last column; And, And performing horizontal edge filtering sequentially from pixel data of each block located in the first row of the main memory to pixel data of each block located in the last column. The filtering method of the in-loop deblocking filter system of the video decoder.

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