KR100746856B1 - Multiplierless FIR Digital Filter and Method for Design thereof - Google Patents

Abstract

The present invention extracts information that can be filtered by addition and subtraction from an attribute of a given coefficient without using the multiplier calculation required for the number of taps of a design request in a finite impulse response (FIR) digital filter. The present invention relates to a FIR digital filter capable of performing a filter function through a small addition and subtraction circuit using extracted information, and a design method thereof.

In the multiplier-free FIR digital filter design method of the present invention, four tables are generated for extracting and storing information necessary for addition and subtraction with respect to coefficients of a design request, and the maximum value when the fractional part of the coefficients is taken and expressed as an integer. An addition table of 16 multiples, which is defined as the upper limit, is set, and an addition table for adding and storing data input in synchronization with the clock frequency in units of 16 sections is generated. By extracting the values added from the four tables and the addition table and correcting the error, a value corresponding to the multiplication is obtained, and the result is filtered by adding in the adder chain of the output stage, thereby effectively outputting the logic circuit of the multiplier FIR digital filter. Can be implemented.

FIR digital filter, multiplier, 16-fold boundary, 16-segment addition table, error correction

Description

Multiplierless FIR Digital Filter and Method for Design

1A is a general block diagram of a general FIR filter equation represented by a digital circuit using a multiplier.

FIG. 1B is a general block diagram when a FIR filter is configured by a conventional CSD (Canonical Signed Digit) format.

2 is a block diagram illustrating a structure of a multiplier-free FIR digital filter according to an embodiment of the present invention.

FIG. 3 is a block diagram when the FIR filter of FIG. 2 is extended to a plurality of FIR filters.

4 is a flowchart of extracting and subtracting information from coefficients given as design requests in a FIR filter according to the present invention and storing them in a table.

5 is a flowchart of generating an addition table based on coefficients of 16 sections in input data given by an FIR filter according to the present invention.

FIG. 6 is a flowchart of determining, calculating, and correcting an error by adding or subtracting a value in the addition table generated in FIG. 5 based on a value in the tables generated in FIG. 4.

<Description of Symbols for Main Parts of Drawings>

100, 200: FIR digital filter

110, 210: coefficient information extraction block

120, 230, 240, 250: Addition and subtraction circuit

220: additive subtraction circuit block

The present invention provides an orthogonal frequency-division multiplexing (OFDM), orthogonal frequency-division multiple access (OFDMA), and code division multiple access (CDMA) based communication schemes, which are recently used as the communication speed is increased and the traffic volume is increased. A multiplier-free FIR digital filter and its design method capable of designing a small hardware resource structure when implementing a FIR (Finite Impulse Response) digital filter required at a transmitting end or a receiving end of a base band of a mobile communication system It is about.

In a mobile communication system operated by a normal base station and a mobile terminal, a digital filter that filters baseband digital signals is called a PSF (Pulse Shaping Filter), and an IIR (Infinite Impulse Response) type that feeds an output to an input to a PSF. There is a filter of a finite impulse response (FIR) type that does not feed back a filter and an output as an input.

In the above-described digital filter, the signal is processed by multiplying the bit of the input data by the coefficient and the coefficient, so that a register for temporarily storing the data processed in each bit unit is required, and the number of representation bits of the coefficient is required. Alternatively, the larger the number of taps, the better the filter characteristics, while requiring more registers and logic circuits.

High speed linear phase FIR filters, which are widely used in mobile communication terminals, are usually designed to operate as digital circuits using CMOS technology. The design requirements of the FIR filter are given the number of bits of the input data, the number of taps, and the number of bits of the coefficients representing the size of each tap, and the hardware complexity of the FIR filter is determined in proportion to the size of each given request. In the FIR filter, the hardware size is determined and evaluated by the number of multipliers used for multiplying the input data with the coefficient of each tap determined rather than the number of bits of the input.

A traditional example of the simple construction of an FIR filter structure depending on mathematical equations is shown in FIG. 1A. As shown in FIG. 1A, the FIR filter 10 having a conventional multiplier receives the input data Di and shifts the input data Di every clock cycle using the shift register in the multiplier 12. The sum multiplied by the coefficient Coef given as an input is added through the adder chain 14 to produce a final result.

Meanwhile, various techniques and design methods using an adder / subtracter without using a multiplier have been proposed to compensate for the above-mentioned disadvantages. In the prior art, as shown in FIG. 1B, a method of converting a coefficient Di given as an input into a CSD (Canonic Signed Digit) format and filtering input data through an adder / subtracter using the converted value is typical. Most commonly known as. In this conventional method, a CSD code (1, 0, -1) having a minimum number of b'1 binary digits is obtained, and a maximum common element for CSE (Common Subexpression Elimination) is obtained. The filter is then implemented through the operation corresponding to the multiplication using the shift / adder 24 and the adder chain 26 from the result.

In the filter structure using the conventional CSD format, since the binary multiplier is an operation structure basically dependent on the configuration of the shift and the adder, it is an important design problem to find a way to reduce the number of possible additions. Since the early 1990s, many studies have been conducted on the CSD format, and the problem of obtaining the optimal Mindum Signed Digit (MSD) format is estimated to be NP-Complete. It is proposed. Nevertheless, in the conventional CSD filter, when the given coefficient is expressed in the CSD format, the number of b'1 is known to be about 1/3 to 1/2 on average, and the shift / adder, that is, multiplication substitute for multiplication, There is a limit to what is needed.

Accordingly, the present invention is to provide a design method for reducing the addition and subtraction of multiplication in a way that can overcome the limitations of the prior art.

The present invention analyzes the properties of a given coefficient and extracts information for designing only by addition and subtraction without performing a filtering operation by the multiplier required as many taps as the design request, and then uses the extracted information to add or decrease the number of taps. An object of the present invention is to provide a multiplier-free FIR digital filter implemented by an adder circuit and a design method thereof.

Another object of the present invention is to provide a multiplier-free FIR digital filter that can be used when a plurality of non-multiplying FIR digital filters are required to support multiple standards in one hardware.

According to an aspect of the present invention, a coefficient information extraction block for extracting and storing information capable of filtering operation by addition and subtraction from an attribute of coefficients given as an input; And an adder / subtracter circuit for performing a filtering operation and an error correction on the input data using information stored in the coefficient information extraction block.

Preferably, the multiplier-free FIR digital filter selects and stores eight or more coefficients by a comparison operation on coefficients of a design input to generate eight or more coefficient tables.

The multiplier-free FIR digital filter determines the magnitude of the input data with 9 by a comparison operation, and generates an addition table by storing the input data and the added value when it is smaller than 9.

According to another aspect of the present invention, when the same coefficient as the plurality of different input data is given, extracting and storing information capable of filtering operation by addition and subtraction from the attribute of the coefficient; Performing a filtering operation on the input data; And error-correcting the filtered calculated value using information stored in the coefficient information extraction block in common.

Hereinafter, with reference to the accompanying drawings will be described in detail so that those of ordinary skill in the art to practice the present invention.

2 is a block diagram illustrating a structure of a multiplier-free FIR digital filter according to an embodiment of the present invention.

2, the FIR filter 100 according to the present embodiment includes a coefficient information extraction block 110 and an additive subtraction circuit 120, and instead of a multiplier required by the number of taps of a design request, Extract information capable of filtering operation by addition and subtraction from the property of the coefficient Coef given as an input using the information extraction block 110 and perform a filtering function through the addition and subtraction circuit 120 using the extracted information. do.

The coefficient information extraction block 110 may perform one or more clock periods during the first clock of the filter or in a design condition with a high clock frequency or a large number of taps before performing the filtering operation on the input data Di in the addition and subtraction circuit 120. Perform preprocessing for filtering operations. To this end, the coefficient information extraction block 110 stores the coefficient table / first table (Toe) 112, which stores only coefficients having a value of 8 or more, and adjacent 16-fold coefficients between the coefficients given from the first table 112. Coefficient interval table / third table (Tai) for storing interval information between the 16-fold boundary table / second table (Tcb) 114 storing boundary information and the boundary value corresponding to each coefficient in the second table 114. 116), and an extraction index table / fourth table (Tsi) 118 for storing an index to be used for reading the addition and subtraction results from the 16-section addition table / addition table (Tas) 121 described later. The above-described coefficient information extraction block may be configured as a storage medium of a register or a memory element, and also includes information for controlling the operation of the filter.

The addition / subtraction circuit 120 includes a 16-section addition table / addition table (Tas) 121, an error correction table (Taa) 122, a multiplication result table / result table (Tae) 123, and an adder chain 124. It is provided. The addition table 121 is generated by setting an addition section of 16 multiples in which the maximum value when the fractional part of the coefficient is expressed as an integer as an upper limit and adding data input in synchronization with the clock frequency in units of 16 sections. The error correction table 122 extracts the values added from the three tables 112, 114, and 116 and the addition table 121 of the coefficient information extraction block 110 to obtain a value corresponding to the multiplication. Is generated. The result table 123 is generated to store values corrected by addition and subtraction in the extraction index table 118 and the error correction table 122. The adder chain 124 adds the non-multiplication result values stored in the result table 123 in a chain form in synchronism with a clock cycle, and outputs the addition result of the FIR filter as a result value.

The implementation of the circuit for the non-multiplicative FIR digital filter proposed in the present invention adopts a design method that represents a structure using a hardware design language such as a hardware description language (HDL), and the source code of the described design A method for generating an FIR filter circuit by an autosynthesis tool can be used. In the existing method of implementing a digital filter using HDL, a new code must be designed when a design demand such as the number of taps is changed. However, in the present invention, the number of taps is changed within a range in which a specification limit of a clock frequency is allowed. It is also possible to replace the design requirements only. The structure of the table used in the present invention can be implemented using a memory or a register storage medium such as RAM, ROM, etc. according to the intention of the digital circuit designer, and the representation of the index (value) is stored in the storage. It corresponds to the meaning of the address in the medium.

FIG. 3 is a block diagram illustrating a configuration in which the FIR filter of FIG. 2 is extended to a plurality of FIR filters.

Referring to FIG. 3, the FIR filter 200 according to the present embodiment includes a coefficient information extraction block 210 and an addition and subtraction circuit block 220 including a plurality of addition and subtraction circuits 230, 240, and 250. By using the coefficient information extraction block 210 to extract the information that can be filtered by addition and subtraction from the property of the coefficient (Coef) given as an input, multiple inputs using the respective addition and subtraction circuits (230, 240, 250) Performs a filtering function on the data. For reference, the configuration of the coefficient information extraction block 210 and the respective addition / subtraction circuits 230, 240, and 250 is substantially the same as the configuration of the coefficient information extraction block and the addition / subtraction circuit of the FIR filter with reference to FIG. 2.

The FIR filter according to the present embodiment may be used when a single chip supporting multiple communication schemes such as WLAN (802.11g) and WiMax (802.16-2004) needs to be designed. In this case, 3 * 2 (real and imaginary) = 6 when integrating other communication services such as 54 Mbps (802.11a), 11 Mbps (802.11b), WiMax in 802.11g, and the receiver also applies the FIR filter. In this case, 6 * 2 = 12 FIR filters are used, and when the multiplier is used, the hardware usage increases. Therefore, in the case where it is necessary to support multiple communication standards, if the extraction block of coefficient information is installed before starting the filtering operation by applying the structure according to the design method of the multiplier-free FIR digital filter of the present invention shown in FIG. The addition and subtraction circuits can be commonly used for multiple different input data D1, D2, ..., Dn, thereby enabling the implementation of smaller hardware. However, in the FIR filter according to the present invention, it is assumed that the same tap coefficient is used for multiple input data.

According to the present embodiment, unlike the conventional filter configuration in which the same filter is simply arranged and implemented, the configuration of the FIR filter of FIG. 2 is determined to simplify the addition or subtraction corresponding to the multiplication, and the more types of inputs, the smaller There is an advantage that the implementation effect in hardware is increased. In addition, the present invention can be easily changed in a short time when there is a specification change request in the design process of the FIR filter can implement a multiplier-free FIR filter. That is, according to the present invention, the degree of freedom in designing the FIR filter is greatly improved.

Hereinafter, a process of generating the aforementioned tables will be described in sequence with reference to FIGS. 4, 5, and 6 based on FIG. 2. In the following description, the filter characteristics vary depending on whether the total number of taps is odd or even due to the characteristics of the FIR filter.

4 is a flowchart of extracting and subtracting information from coefficients given as design requests in a FIR filter according to the present invention and storing them in a table.

의 특성으로부터 우함수인 경우 Chn=Cn/2개이고, 기함수인 경우 Chn=Cn/2+1개이며, Chn번째의 계수가 최대 계수값(Cmax)을 갖게 된다. 각 입력 계수 Coef(i)(i = 0, 1, 2,.., n-1, n = Chn)에 대하여 비교 연산(410)을 통해 8 이상의 값을 갖는 계수를 제1 테이블 Toe(j)(j = 0, 1, 2, .., s-1, s < n)에 저장한다(411). 상기 비교 연산(410)에서 계수 중에 음의 값을 갖는 계수는 2의 보수를 적용하여 양의 값을 갖는 비트로 변환한 값을 비교하고 있으며, 제1 테이블 Toe(j)의 모든 계수는 소수 부분의 비트들을 취하고 양의 값(양의 정수 또는 비트)으로 표현된다.As shown in Figs. 2 and 4, a coefficient table / first table (Toe) 112 is first generated for selecting eight or more coefficients Coef. When the total number of coefficients given by the design request is Cn, the n input coefficients Coef (i) 400 are synchronized. function

If the right function is Chn = Cn / 2, the odd function is Chn = Cn / 2 + 1, and the Chn-th coefficient has the maximum coefficient value Cmax. For each input coefficient Coef (i) (i = 0, 1, 2, .., n-1, n = Chn), a coefficient having a value of 8 or more is compared through a comparison operation 410 in the first table Toe (j). (j = 0, 1, 2, ..., s-1, s <n) is stored (411). In the comparison operation 410, a coefficient having a negative value among the coefficients is compared with a value converted to a bit having a positive value by applying two's complement, and all coefficients of the first table Toe (j) It takes bits and is represented by a positive value (positive integer or bit).

Secondly, a 16-fold boundary table / second table (Tcb) 114 having 16-fold interval information is generated. To this end, b 'is used for a value obtained by converting the lower 4-bit b'3b'2b'1b'0 to two's complement among the coefficients of the first table Toe (j) generated through the comparison operation 420. The value of 3 is taken as a sign. The value of b'2b'1b'0 stores the boundary information of the coefficient such that the value of Toe (j) is 16 times in the second table (423). In other words, in the comparison operation 420, when b'3 representing a sign is negative ('1'), the value 421 is obtained by subtracting the value of b'2b'1b'0 from the corresponding coefficient of Toe (j). Is stored in the second table Tcb (k), and when b'3 is positive ('0'), the coefficient s plus the value of b'2b'1b'0 is added to the second table Tcb (k). Save to (423). Here, all initial values of Tcb (k) are set to 16, k is an initial value of the number of coefficients larger than 8 and smaller than 32, and the total number of k is the number of coefficients having a value of 8 or more. 1 This is equal to the number of tables Toe (j). In the generation of the second table, as a result, values having coefficients greater than or equal to 32 are stored as targets, and the stored values are different from the filter output candidate values (including errors) stored in the 16-segment addition table / addition table (Tas) 121. When performing the correction, it is used as the boundary reference value of the addition table.

Third, a coefficient section table / third table (Tai) 116 having section information between the coefficients is generated. To this end, the comparison operation 430 compares the sizes of the previously generated values Tcb (k) and Tcb (k + 1) of the second table. When Tcb (k + 1) is large, obtain the difference (Tcb (k + 1)-Tcb (k)) and store the value of the upper bits except the lower 4-bits of the difference (dif) in the temporary array Dst (l). , Tai (l-1) plus Dst (l-1) is stored in Tai (l) (431, 433). When Tcb (k + 1) is small or equal in the comparison operation 430, since 2 does not need to apply a temporary array for the next step Tai (l + 1), simply add 2 to Tai (l-1). Store in Tai (l) (432, 433). Here, all initial values of the third table Tai (l) are set to 9, and the initial value of l and the total number of l are equal to the value Tcb (k) of the second table. All initial values of the third table Tai (l) are set to 9 because the 9th Tas (9) stores the value of the additive subtraction corresponding to the coefficient 16 in the addition table Tas described later. The third table is used as an index that reads values in the addition table when performing error correction from the addition table.

+8"을 초기값으로 하여 "1"씩 증가시킨 값을 제4 테이블 Tsi(m)에 저장하고(441, 443), 상기 비교 연산(410)에서 Coef(i)가 8과 같거나 작은 경우에는 그 계수 Coef(i)를 제4 테이블 Tsi(m)에 저장한다(442, 443). 제4 테이블의 값 Tsi(m)(m = 0, 1, 2,.., m-1, m =

+ 8 + Toe크기)는 가감산에 의해 오차보정을 수행하는 테이블(Taa) 내의 값을 읽어내는 인덱스로 사용된다. 도 4의 단계 441에서 Val을 계산할 때, 도 4에는 표기되어 있지 않으나, i = 16일 때는 현재의 Val 값에 "1"을 증가시키는 대신에 9를 저장한다. 이것은 제3 테이블(Tai)의 생성에서 기술한 바와 같이 제4 테이블(Tsi)의 특정 값 Tsi(9)에 16구간 가산 테이블(Tas)의 기준값을 16(주어진 계수 중에 16의 존재 여부에 관계없이 할당함)으로 정하고 있기 때문이다.Fourth, an extract index table / fourth table (Tsi) 118 having an index value for reading the additive subtraction result is generated. If the coefficient Coef (i) is greater than 8 in the same comparison operation 410 used when generating the first table 112, " Val =

In the case where Coef (i) is equal to or smaller than 8 in the comparison operation 410, a value incremented by "1" by +8 "as an initial value is stored in the fourth table Tsi (m) (441, 443). Stores the coefficient Coef (i) in the fourth table Tsi (m) (442, 443.) The value Tsi (m) of the fourth table (m = 0, 1, 2, .., m-1, m). =

+ 8 + Toe size) is used as an index that reads a value in a table Taa that performs error correction by addition and subtraction. When calculating Val in step 441 of FIG. 4, although not shown in FIG. 4, when i = 16, 9 is stored instead of increasing "1" to the current Val value. As described in the creation of the third table Tai, the reference value of the 16-segment addition table Tas is added to the specific value Tsi (9) of the fourth table Tsi by 16 (regardless of whether 16 is present in a given coefficient). (Assigned).

Hereinafter, an error correction generated by adding and subtracting an error using the addition table Tas generated by the addition of 16 sections and the three tables (Toe, Tcb, and Tai) generated above is performed. The table Taa is described.

5 is a flowchart of generating an addition table based on coefficients of 16 sections with respect to input data in the FIR filter according to the present invention.

+ 8"이며, 상기 비교 연산(501)에서 9 이하의 가산 결과값들은 입력으로 주어진 원래의 계수 자체를 연산한 결과값으로 사용되며, 또한 가산 테이블(Tas)에 대한 오차보정에서 보정 값으로 사용된다. 본 단계에서 생성한 16구간의 가산 테이블(Tas)은 i가 9보다 클 때는 16구간으로 나누어진 가산값을 가지고, 작을 때는 단순히 입력 데이터 크기인 간격의 가산값을 가지게 되며, i가 9일 때는 16구간의 기준이 되는 가산값을 가지게 된다.2 and 5, in order to generate an addition table Ta corresponding to a multiplication of an existing FIR filter multiplying coefficients, first, input values Di 500 of sequentially input data in synchronization with a clock frequency are used. When i (i = 0, 1, 2, .., n-1) is less than 9 in the comparison operation 501, the result of adding the input data Di to the addition table Tas (i-1) is added to the addition table Tas (i (502, 505), and in the comparison operation 501, if i is equal to 9, the result value obtained by adding its value to the addition table Tas (8) is stored in the addition table Tas (i = 9). 16) (503, 505), and in the comparison operation 501, if i is greater than 9, the result value obtained by adding the value of the addition table Tas (9) fixed with the coefficient 16 to the addition table Tas (i-1). Stored in addition table Tas (i) (504, 505). Where the size of i is "n =

+ 8 ", the addition result of 9 or less in the comparison operation 501 is used as a result of calculating the original coefficient itself given as an input, and also used as a correction value in error correction for the addition table Tas. In this step, the addition table (Tas) of 16 sections has an addition value divided into 16 sections when i is larger than 9, and when the i is smaller, it has an addition value of the interval, which is simply an input data size. In this case, it has an addition value that is a standard for 16 sections.

On the other hand, if the calculation of the adder chain is performed as it is with respect to the addition table Ta generated earlier, an error is included. Therefore, in the present invention, a value corrected by addition and subtraction with respect to the addition table Tas is stored and generated in the error correction table Taa, and the corrected values corresponding to the multiplication result of the existing filter are added to the last stage. The operation is performed through the chain 124.

FIG. 6 is a flowchart of determining whether to add or subtract values in the addition table generated in FIG. 5 based on the values in the tables generated in FIG. 4 and correct an error.

+8"에 "1"을 더한 값이 된다. 그리고, 앞서 생성한 제1, 제2 및 제3 테이블 Toe(j), Tcb(k), Tai(l)과 가산 테이블 Tas(i)의 인덱스 값 j, k, l과 i를 "0"으로 초기화(600)한 후 오차보정 과정을 수행한다.Before executing the error correction, first, the result values of the addition table Tas (i) are copied to the error correction table Taa (r). Here, the number of r is the sum of the number of Tas (i) and the number of Toe (j), and the initial value of r is the number of Tas (i).

+8 "plus" 1 ". The indexes of the first, second, and third tables Toe (j), Tcb (k), Tai (l), and addition table Tas (i) generated earlier are added. After the values j, k, l and i are initialized to “0” (600), an error correction process is performed.

Specifically, as shown in FIG. 6, the comparison operation 601 is used to compare the values of the first and second tables, Toe (j) and Tcb (k). As a result of the comparison operation 601, when Toe (j) is large, the difference dif between Toe (j) and Tcb (k) is obtained (602). If Toe (j) is not large, the difference dif between Tcb (k) and Toe (j) is obtained (605). A value 608 obtained by subtracting Tas (dif) having the difference dif obtained at 605 as an index is stored in the error correction table Taa (r) (609).

Next, in another comparison operation 603, if the difference dif obtained in the step 602 is greater than 8, Tcb (k) is obtained by subtracting the difference dif obtained in the step 602 as a new difference dif (604). , Error correction of Tas (Tai (l) +1) with Tai (l) +1 value minus Tas (dif) with new difference dif obtained in step 604 as the index 607. The data is stored in the table Taa (r) (609).

On the other hand, when the difference dif obtained in the step 602 in the comparison operation 603 is smaller than 8, the difference obtained in the step 602 to Tas (Tai (l)) having the value Tai (l) as an index. A value 606 obtained by adding Tas (dif) with dif as an index is stored in the error correction table Taa (r) (609).

The validity sufficient to perform the above error correction is that the Tas (dif) values according to the indices of the differences dif (602, 604, 605) for the error correction are the lower 3-bit values included in Tas (i) itself. This is because it is applied as an error correction value, and when the generated second table Tcb is obtained, the index of the nearest value among the values of the addition table Tas is obtained for each given coefficient. Also, the values represented by the lower 3-bits for error correction are added based on the boundary value of the second table Tcb (k) generated within 16 intervals, in contrast with the multiplication result value by the original coefficient given as an input. It is because it can contain all by and subtraction.

A multiplication result table (Tae) 123 is generated by extracting a value to be added in the adder chain from the error correction table Taa (r) 609 generated by correcting an error with respect to the addition table Ta. Here, the value to be added becomes a value corresponding to the output of the multiplier of FIG. 1A.

Specifically, the additive subtraction result value is read from the error correction table Taa (r) by each index of the fourth table Tsi (m) and stored in the multiplication result table Tae (t). Here, t is t = Chn (t = 1, 2, .., Chn-1), which is the value of the given number of input coefficients Chn. The generated result table (Tae) calculates only Chn = Cn / 2 from the symmetry of coefficients among the given number of coefficients Cn, and simply adds the above calculation result values in descending order or adds chains to the remaining Cn / 2. It is possible to adopt a structure that adds to Chn in the structure of, or a generally known method, and, among the values of the result table Tae, for the negative coefficients among the coefficients given at the time of generation of the first table Toe. Means for representing positive coefficients and means for inversely expressing the result values of the corresponding result table (Tae) with negative result values using two's complement are applied.

Finally, the result of the multiplication of the resultant result table Tae (t) is input to the circuit of the adder chain 124, added in synchronization with the clock cycle in the form of a chain, and Tae (Cn-1) + Tae of the last stage. (Cn) The addition result is output as a result of the FIR filter. The adder chain operation is applied to the logic circuit structure generally used, and the value Tae (t) of the result table is M (i) (t = i, i = 0, 1, 2,. It is the same input value as.

For 24 (Chn = Cn / 2) inputs given as 48-tap, 8-bit inputs, the results are applied according to each step above. The results are shown in Table 1.

Ord Coef Int Toe Tcb Tai Tsi Tas Taa Tae etc 0 00000000 0 12 16 9 0 0 0 0 Di = 3 One 11111111 -One 10 16 9 One 3 3 -3 2 11111110 -2 24 16 9 2 6 6 -6 3 00000000 0 20 16 9 0 9 9 0 4 00000100 4 36 32 10 4 12 12 12 5 00000110 6 80 80 13 6 15 15 18 6 00000101 5 116 112 15 5 18 18 15 7 00000000 0 127 128 16 0 21 21 0 8 11111010 -6 6 24 24 -18 9 11111000 -8 8 48 48 -24 10 11111001 -7 7 96 96 -21 11 00000000 0 0 144 144 0 12 00001000 8 8 192 192 24 13 00001100 12 17 240 240 36 14 00001010 10 18 288 288 30 15 00000000 0 0 336 336 0 16 11110000 -16 9 384 384 -48 17 11101000 -24 19 36 -72 18 11101100 -20 20 30 -60 19 00000000 0 0 72 0 20 00100100 36 21 60 108 21 01010000 80 22 108 240 22 01110100 116 23 240 348 23 01111111 127 24 348 381 24 381

Table 1 shows the results obtained by setting the input data value to "Di = 3" and applying to each of the above steps, and the result of the final result table Tae according to the present invention is the same as that of the Tae column of Table 1.

+8=16"개이고, 오차보정 테이블(Taa)에서는 인덱스 값을 구하는 8개의 감산(602, 604, 605), 가산의 오차보정(606)에서 8개, 및 감산의 오차보정(607, 608)에서 8개이다. 따라서, 본 발명에서는 모두 40개의 가감산기를 사용하므로 기존의 CSD 형식보다 적은 가감산으로 FIR 필터를 구현할 수 있다.As shown in Table 1, for the 48-tap 7-bit (the MSB that represents the sign out of 8-bits) coefficients, in the conventional CSD format, the coefficient symmetry and the number of coefficients having a "0" value. Except, about (48/2-6) x 2.5 = 45 adders and subtractors are needed. Where 2.5 is the mean value for the 7-bit coefficients. On the other hand, in the present invention, when the maximum value of the coefficient is 127 (7-bit), the adder in the addition table Tas is "

8 subtractions (602, 604, 605) for obtaining index values in the error correction table (Taa), 8 subtractions for the error correction (606) of addition, and error corrections (607, 608) for subtraction. Therefore, since the present invention uses all 40 adders and subtractors, the FIR filter can be implemented with less add / subtract than the conventional CSD format.

In the present invention, an adder based on four extra coefficients irrelevant to the input coefficients is used among the addition result values in the addition table, and four tables for extracting addition and subtraction information from the coefficients are generated when compared with the existing CSD format. It does not include the process of doing it in hardware. In other words, since these coefficients are not inputted by the given coefficients during the filter operation, the result of separately executing the coefficient information extraction block when using the HDL language is stored in the design_package file that defines the parameters of the logic design condition. This technique has the advantage that logic synthesis can be performed on the addition and subtraction circuits without generating unnecessary hardware.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. This is possible.

As described above, the multiplier-free FIR digital filter of the present invention and its design method have the following advantages.

First, in designing a digital filter, a multiplier with a high design complexity may not be used, and the number of additions or subtractions using the multiplier instead of the existing CSD format may be reduced.

Second, it is possible to simply and effectively extend the structure of the filter when supporting input data of multiple communication standards.

Third, it can contribute to miniaturization and low cost of devices such as a signal processing device and a modem chip having a baseband processing unit used in an OFDM, OFDMA, CDMA-based communication system.

Claims (19)

A coefficient information extraction block for extracting and storing information capable of filtering operation by addition and subtraction from attributes of coefficients given as an input; And And an adder / subtracter circuit for performing filtering operation and error correction on the input data using information stored in the coefficient information extraction block. 2. The multiplier FIR digital filter of claim 1, wherein the coefficient information extracting block selects and stores eight or more coefficients of the coefficients to generate eight or more coefficient tables. The method according to claim 2, wherein the coefficient information extraction block, for each coefficient in the coefficient table, takes the fourth bit among the lower 4-bits of the coefficient itself and adds or subtracts it through a preset comparison operation. Judging, And a 16-fold multiplier boundary table for subtracting or adding the remaining lower 3-bit values and storing the result as a 16-fold threshold. 4. The coefficient information extracting block of claim 3, wherein the coefficient information extracting block obtains a difference between two adjacent coefficients in the boundary table, stores upper bits except the lower 3-bits in a temporary array, and corresponds to the coefficient table. Add the value of the temporary array to the value, And a coefficient interval table for storing the added result value. The coefficient information extraction block according to claim 4, wherein the coefficient information extraction block determines the magnitude of the coefficient and eight, and the initial value "Val =" when the coefficient is larger than eight.

Generate an extraction index table which stores the coefficient when the result is increased by "1" to +8 "(where Cmax is the maximum coefficient value of the coefficient), or when the determination result is less than or equal to 8. Multiplier FIR digital filter. 6. The apparatus of claim 5, wherein the addition and subtraction circuit determines the magnitude of the input data and 9, and stores the result value of adding the input data to the value of the previous addition table index when the input data is less than 9. And a multiplier FIR digital filter for generating an addition table. 7. The method of claim 6, wherein when the input data equals 9, the addition and subtraction circuit adds values of the eighth addition table to each other and stores the result in the ninth addition table as 16 addition intervals. A multiplier FIR digital filter characterized in that. 8. The method of claim 6 or 7, wherein when the input data is greater than 9, a result value obtained by adding a value of the ninth addition table based on 16 intervals to a value of the previous addition table index. A multiplier-free FIR digital filter, characterized in that. 9. The method of claim 8, wherein the coefficient information extraction block and the addition and subtraction circuit determine the magnitude of the value of the coefficient table and the value of the boundary table corresponding thereto, and obtain a difference for error correction according to the determination result. Features a multiplier-free FIR digital filter. 10. The method according to claim 9, wherein the coefficient information extraction block and the addition and subtraction circuit, when the value of the coefficient table is equal to or smaller than the value of the boundary table, adds the value of the boundary table and the value from the corresponding value of the addition table. A multiplier-free FIR digital filter, comprising: generating an error correction table that stores a value obtained by subtracting a value of an addition table whose index is a difference from a value of a coefficient table. 11. The method of claim 10, wherein the coefficient information extraction block and the addition / subtraction circuit have a value of the coefficient table greater than a value of the boundary table, and a value obtained by subtracting the value of the boundary table from a value of the coefficient table is 8; And if larger, a value obtained by subtracting the difference between the value of the coefficient table and the value of the boundary table from the value of the boundary table as a new error correction difference. 12. The error correction table according to claim 11, wherein the coefficient information extraction block and the addition / subtraction circuit store an error correction table that stores a value obtained by subtracting a value of an addition table whose index is the difference of the new error correction from a corresponding value of the addition table. And a multiplier-free FIR digital filter. The coefficient information extraction block and the addition / subtraction circuit according to claim 12, wherein the value of the coefficient table is greater than the value of the boundary table, and the difference between the value of the boundary table from the value of the coefficient table is less than or equal to eight. And a multiplier for generating an error correction table that stores a value obtained by adding a value of an addition table whose index is the difference between the value of the boundary table and the value of the coefficient table from the corresponding value of the addition table. FIR digital filter. 14. The multiplication result table according to any one of claims 10 to 13, wherein a value of the error correction table is read as an index of the extraction index table, and a multiplication result table is generated which stores the read value. Multiplier FIR digital filter. The method of claim 1, A multiplier-free FIR digital filter in which a plurality of additive subtraction circuits form an additive subtraction circuit block to perform filtering operations and error correction on multiple input data. Extracting and storing information capable of filtering operation by addition and subtraction from an attribute of the coefficient when given a same coefficient as different multiple input data; Performing a filtering operation on the input data; And And correcting the filtered calculated value using information stored in the coefficient information extraction block. 17. The method of claim 16, wherein the performing a filtering operation on the input data comprises: setting an addition interval of 16 multiples in which a maximum value when the fractional part of the coefficient is expressed as an integer is set as an upper limit and synchronized with a clock frequency. And generating a 16-segment addition table for storing a value obtained by adding the input data in 16-segment units. 18. The method of claim 16 or 17, wherein extracting and storing the information comprises: Generating a coefficient table that stores only coefficients having a value of 8 or greater; Generating a 16-fold boundary table for storing adjacent 16-fold coefficient boundary information between given coefficients from the coefficient table; Generating a coefficient interval table for storing interval information between boundary values corresponding to each coefficient in the 16-fold boundary table; And And generating an extract index table for storing an index used to read an additive subtraction result from the 16-section addition table that performs the filtering operation. The method of claim 18, wherein the error correction step, Generating a result table storing an error correction result value by subtracting and subtracting a value stored in the 16-section addition table; And And adding the value stored in the result table through an adder chain circuit, and outputting the added result value.

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