KR100746290B1 - Temperature compensated on-chip resistor circuit, semiconductor device having the circuit and method for calibrating impedance of the semiconductor device - Google Patents

Abstract

A temperature compensated on-chip resistor circuit, a semiconductor device and a method for calibrating the impedance of the semiconductor device are provided to reduce the number of terminals by omitting additional ZQ terminals using the on-chip resistor circuit instead of an external resistor circuit. A semiconductor device includes an on-chip resistor circuit, a compensation circuit and an ODT(On Die Termination)/OCD(Off Chip Driver) calibrating circuit. The on-chip resistor circuit(270) is formed at an inner portion of the device. The compensation circuit(260) is used for compensating the on-chip resistor circuit for impedance according to the temperature measured from the device. The ODT/OCD calibrating circuit is used for calibrating the impedance of at least one out of an ODT circuit and an OCD circuit on the basis of the impedance of the temperature compensated on-chip resistor circuit.

Description

Temperature compensated on-chip resistor circuit, semiconductor device having the on-chip resistor circuit and impedance calibrating method of the semiconductor device, semiconductor device having the circuit and method for calibrating impedance of the semiconductor device}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a semiconductor device and an external resistor according to the prior art.

2 is a block diagram illustrating a semiconductor device according to example embodiments.

3 to 6 are graphs for explaining a method of compensating on chip resistance according to a process and a temperature change according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating the on-chip resistance compensation circuit illustrated in FIG. 2.

FIG. 8 is a block diagram illustrating an implementation example of the compensation coefficient calculator illustrated in FIG. 7.

9 is a flowchart illustrating a temperature compensation method of an on-chip resistor according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to correct an impedance of an on-die termination (ODT) or off-chip driver (OCD) circuit (hereinafter, an ODT / OCD circuit) of a semiconductor device. The present invention relates to a circuit and method for compensating on-chip reference resistance (internal resistance) used for calibration according to temperature, and an impedance calibration method of an ODT / OCD circuit using the same.

In most cases, semiconductor devices such as microcontrollers and semiconductor memory devices exchange data with other semiconductor devices through transmission lines. Accordingly, most semiconductor devices include an off chip driver (OCD) for outputting signals to the outside and an on die termination (ODT) circuit for preventing reflection of signals transmitted from the outside to the semiconductor device. In this case, in order to secure signal integrity, the impedance characteristics of the ODT / OCD circuit must be calibrated. The higher the system is operated, the greater the need for the calibration.

Most semiconductor devices according to the prior art have a separate ZQ terminal for calibrating the impedance characteristics of an internal off-chip driver (OCD) or on-die termination (ODT) circuit, and directly connect an external reference resistor. Impedance calibration is performed in proportion to the impedance of the external reference resistor.

1 is a block diagram illustrating a semiconductor device and an external resistor according to the prior art. Referring to FIG. 1, the semiconductor device 100 according to the related art includes an ODT / OCD calibration circuit 110, a plurality of ODT / OCD circuits 121 to 12n, a plurality of input / output terminals 141 to 14n, and a ZQ terminal. 130 is provided. The external resistor Rex is connected between the ZQ terminal 130 and the ground outside the semiconductor device.

The ODT / OCD calibration circuit 110 corrects the impedance characteristics of the internal ODT / OCD circuits 121 to 12n according to the magnitude of the impedance of the external resistor Rex. The ZQ terminal 130 is a terminal for connecting the external resistor Rex to the ODT / OCD calibration circuit 110 and is provided separately from the input / output terminals 141 to 14n.

Therefore, when performing impedance calibration using the ZQ terminal, a separate ZQ terminal is required, which increases the number of terminals (ie, the number of pins) of the semiconductor chip. In addition, due to the external resistance, in a memory module having a plurality of semiconductor memory devices, the number of external resistors mounted on the memory module increases, which leads to complicated wiring and is very inefficient in terms of cost and space utilization.

Therefore, in order to reduce the number of terminals of the semiconductor device and to increase efficiency in terms of wiring and cost, it is desirable to correct the impedance of the ODT / OCD circuit by using an internal resistor, that is, an on-chip resistor, instead of an external resistor. However, on-chip resistance is more vulnerable to process variation or temperature change than resistance outside the chip. The process change can be adjusted during the test of the semiconductor device in the process step, but the temperature change occurs during the operation of the semiconductor device, making it difficult to adjust in the test step of the semiconductor device.

Accordingly, it is an object of the present invention to provide a circuit and method for compensating the on-chip reference resistance with temperature such that the impedance of the on-chip reference resistance provided in the semiconductor device is substantially independent of temperature.

Another object of the present invention is to provide a semiconductor device having a circuit for compensating the on-chip reference resistance and a method for calibrating an impedance of an on die termination (ODT) or off-chip driver (OCD) circuit based on the on-chip reference resistance. It is.

In accordance with an aspect of the present invention, a semiconductor device includes an on-chip resistor circuit, a compensation circuit, and an ODT / OCD calibration circuit. The compensation circuit is a circuit for compensating the impedance of the on-chip resistance circuit according to the measured temperature of the semiconductor device, and using the first and second compensation coefficients that are respective compensation coefficients for the first and second temperatures. Compensation coefficient for the third temperature between the first temperature and the second temperature is calculated, and the impedance of the on-chip resistance circuit is compensated for using the compensation coefficient for the third temperature. The ODT / OCD calibration circuit corrects the impedance of at least one of an on-die termination circuit and an off-chip drive circuit based on the impedance of the temperature compensated on-chip resistance circuit.

According to an aspect of the present invention, there is provided a method for calibrating an impedance of a semiconductor device, the method comprising: (a) an on-chip resistor circuit and measuring the impedance of the on-chip resistor circuit to a measured temperature of the semiconductor device; And (b) calibrating the impedance of at least one of the on-die termination circuit and the off-chip driving circuit based on the impedance of the temperature compensated on-chip resistor circuit. .

In the step (a), measuring the impedance of the on-chip resistor circuit at the first and second temperatures, respectively, and calculating first and second compensation coefficients, which are respective compensation coefficients for the first and second temperatures. Determining, using the first and second temperatures and the first and second compensation coefficients, calculating a compensation coefficient for a third temperature between the first and second temperatures and the third temperature Compensating for the impedance of the on-chip resistor circuit based on a compensation factor for.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram illustrating a semiconductor device according to example embodiments.

Referring to FIG. 2, the semiconductor device 200 according to an exemplary embodiment may include an ODT / OCD calibration circuit 210, a plurality of ODT / OCD circuits 221 to 22n, and a plurality of input / output terminals 241 to 24n. ) And an on-chip resistance compensation circuit 250. The on chip resistance compensation circuit 250 includes a compensator 260 and an on chip resistor 270.

The ODT / OCD calibration circuit 210 corrects the impedance characteristics of the internal ODT / OCD circuits 221 to 22n according to the magnitude of the impedance of the on-chip resistor 270.

The on-chip resistor 270 is a resistor used as a reference for correcting the impedance of the ODT / OCD circuits 221 to 22n and is provided inside the chip. The on-chip resistor 270 may change in value depending on a process or temperature compared to a resistance outside the chip. The compensator 260 is a circuit that compensates the impedance (resistance value) of the on-chip resistor 270 according to temperature so that the impedance of the on-chip resistor 270 can have a substantially constant value regardless of temperature.

3 to 6 are graphs for explaining a method of compensating on chip resistance according to a temperature change according to an embodiment of the present invention.

First, FIG. 3 is a graph showing a change in on-chip resistance according to temperature for each semiconductor device. Referring to FIG. 3, as the temperature increases, the value of the on-chip resistance also increases. However, the rate of change with temperature may vary from semiconductor device to semiconductor device.

In FIG. 3, the first to third graphs 310, 320, and 330 show changes in on-chip resistance according to temperatures of the first to third semiconductor devices chip # 1, 2, and 3, respectively. As shown, the on-chip resistance 270 increases with temperature, but the rate of change may vary depending on the semiconductor chip.

The present invention compensates the resistance value of the on-chip resistance that varies with temperature to have a constant value (target value, 340) regardless of temperature.

As shown in FIG. 4, in order to compensate the on-chip resistance value 320 of a predetermined chip (here, the second semiconductor device) to a constant target value 340 (RT) regardless of temperature, an embodiment of the present invention It takes advantage of the characteristic that the internal chip resistance increases linearly with temperature. To do this, the resistance values RH and RC are measured during the chip test at high and low temperatures. That is, the resistance value Rh at the first temperature Th, which is a relatively high temperature (called the first measurement resistance) is measured, and the resistance value Rc at the second temperature Tc, which is a relatively low temperature, is measured. 2) called measurement resistance). Here, measurements are made at two different temperatures (Th, Tc), but measurements may be made at three or more temperatures, and measurements should be made at at least two temperatures.

When the first and second measurement resistances Rh and Rc are obtained at the first and second temperatures Th and Tc, as shown in FIG. 5, the target value RT is set to the first and second measurement resistances Rh. , Rc), which is the ratio divided by Rc), respectively. α and β are compensation coefficients at the first and second temperatures, respectively.

The compensation coefficient for any temperature between the first temperature Th and the second temperature Tc can be obtained by interpolating α and β. And the compensation resistance at any temperature between the first temperature and the second temperature can be obtained by multiplying the measured resistance value R0 and the compensation coefficient K at that temperature. This is represented by Equation 1 below.

RT = K × R0

Through the above process, the resistance value RT of the temperature-compensated on-chip resistor has a constant value regardless of temperature, as shown in FIG. 6. Thus, the measured value RO of the on-chip resistance changes with temperature, but by compensating it using the compensation coefficient K as a function of temperature, a constant on-chip resistance value RT is obtained.

FIG. 7 is a diagram illustrating the on-chip resistance compensation circuit illustrated in FIG. 2.

The on chip resistance compensation circuit 250 includes an on chip resistance circuit 270 and a compensation unit 260. The compensator 260 includes a fuse box 261, a compensation coefficient calculator 263, and a temperature sensor 265.

The on-chip resistor circuit 270 is provided with transistors N1, N2, N3,..., Nn and resistors 271-27n connected in series between a predetermined node 280 and a ground (or a predetermined power supply). A plurality (where n and n are two or more natural numbers) are provided. Each transistor N1, N2, N3, ..., Nn has a corresponding bit signal CS [1], of the n-bit control signal CS [1: n] output from the compensation coefficient calculator 263. By selectively turning on / off in response to CS [2], CS [3], ..., CS [n]), the corresponding resistive element of the first to nth resistive elements 271 to 27n is selectively selected. It connects to a predetermined node 280. Accordingly, each transistor N1, N2, N3, ..., Nn is an optional connection for selectively connecting a plurality of resistance elements 271 to 27n in parallel in response to the control signal CS [1: n]. Circuit. Temperature compensating of the on-chip resistor circuit 270 is achieved by forming parallel resistors between the resistor elements connected to the turned-on transistor.

As shown in Equation 1, R0, R0 / 2, R0 / 4, ..., R0 / (2 ^n- (2 ^n-) , respectively, to implement a temperature compensated resistor having K (compensation coefficient) times the measured resistance value. ¹ ) n to nth resistors 271 to 27n having an impedance of 1) may be implemented in parallel, and the first to nth resistors 271 to 27n may be selectively selected according to the compensation coefficient K. Connect to

The fuse box 261 is a circuit for storing the first and second compensation coefficients α and β. Although not shown in detail in FIG. 7, the fuse box 261 includes a plurality of fuses, and the plurality of fuses are selectively cut, thereby storing a predetermined value. Of course, other means than the fuse box 261 may be used to store the first and second compensation coefficients α and β.

The compensation coefficient calculation unit 263 performs interpolation using the first and second compensation coefficients α and β stored in the fuse box 261 and compensates the compensation coefficient according to the current temperature Tx inside the chip. Calculate (K). In order to measure the current temperature Tx inside the chip, a temperature sensor 265 is preferably provided inside the chip. Of course, information about the current temperature (Tx) may be input from the outside of the chip. The detailed operation of the compensation coefficient calculator 263 will be described with reference to FIG. 8.

FIG. 8 is a block diagram illustrating an embodiment of the compensation coefficient calculator 263 illustrated in FIG. 7. Referring to FIG. 8, the compensation coefficient calculator 263 includes a subtractor 810, a multiplier 820, an adder 830, and a control signal output unit 840.

The subtractor 810 obtains a difference between the current temperature Tx and the second temperature Tc measured by the temperature sensor. The multiplier 820 multiplies the output Tx-Tc and ((α-β) / (Th-Tc)) of the subtractor 810. The adder 830 adds the second compensation coefficient β to the output ((α-β) (Tx-Tc) / (Th-Tc)) of the multiplier 820 to compensate for the current temperature Tx (K). ) Is calculated. Therefore, the compensation coefficient K for the current temperature Tx can be obtained by the following equation (2).

K = β + (α-β) (Tx-Tc) / (Th-Tc)

As can be seen from Equation 2, the compensation coefficient calculator 263 shown in FIG. 7 calculates the compensation coefficient K with respect to the current temperature Tx by using a linear interpolation method. However, the method of calculating the compensation coefficient K is not limited to the linear interpolation method.

The values necessary for obtaining the compensation coefficient K, the second temperature Tc, the value of ((α-β) / (Th-Tc)), the second compensation coefficient β, and the like are calculated in advance and thus the fuse box 261. Is preferably stored in.

The control signal output unit 840 is a control signal for controlling each transistor N1, N2, N3,..., Nn of the on-chip resistance circuit 270 based on the calculated compensation coefficient K. CS [1: n]).

FIG. 9 is a flowchart illustrating a temperature compensation method of an on-chip resistor according to an embodiment of the present invention, and may be implemented by the on-chip resistance compensation circuit 260 according to an embodiment of the present invention shown in FIG. 7.

Referring to FIG. 9, first, a test is performed on a selected semiconductor device to measure on-chip resistance values at first and second temperatures Th and Tc, respectively (S910). The first and second compensation coefficients α and β are calculated and stored using the on-chip resistance values measured at the first and second temperatures Th and Tc (S920). Since the method of calculating the first and second compensation coefficients α and β has been described above, the description thereof will be omitted. The first and second compensation coefficients α and β may be stored using the above-described fuse box 261 or may be stored by another technique.

Next, the current temperature Tx is measured by the temperature sensor 265 (S930).

The compensation coefficient K for the current temperature Tx is obtained using the present temperature Tx, the first and second temperatures Th and Th, and the first and second compensation coefficients α and β (S940). . Since a detailed method of obtaining the compensation coefficient K has been described above, a description thereof will be omitted.

Based on the calculated current compensation coefficient K, the control signal CS [1: n] of the transistor for selectively connecting the resistance elements 271 to 27n in FIG. 7 is generated. Since the transistor is selectively turned on / off in response to the control signal CS [1: n], the temperature-compensated on-chip reference resistance value is determined by the resistors connected to the turned-on switch transistor (S960).

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true scope of protection of the present invention should be defined only by the appended claims.

As described above, according to the present invention, in order to calibrate the impedance of the on-die termination (ODT) or off-chip driver (OCD) circuit, by using the on-chip resistor provided in the chip rather than the external resistor provided on the outside of the chip. Since the semiconductor device does not have to have a separate ZQ terminal, the number of terminals is reduced. In addition, by not using an external resistor, wiring is simplified in a semiconductor device or a memory module having a plurality of semiconductor memory devices, and is very efficient in terms of cost and space utilization.

In addition, according to the present invention, the on-chip resistance is compensated to have a constant value irrespective of temperature, thereby preventing the temperature-dependent variation that the on-chip resistance may experience. Thus, the impedance of the ODT / OCD circuit can be accurately calibrated, thereby ensuring signal integrity.

Claims (15)

In a semiconductor device, An on-chip resistance circuit provided in the semiconductor device; A compensation circuit for compensating the impedance of the on-chip resistance circuit according to the measurement temperature of the semiconductor device; And And an ODT / OCD calibration circuit for calibrating the impedance of at least one of an on-die termination circuit and an off-chip driving circuit based on the impedance of the temperature compensated on-chip resistance circuit. . The method of claim 1, wherein the compensation circuit Compensation coefficients for the third temperature between the first temperature and the second temperature are calculated using the first and second compensation coefficients, which are respective compensation coefficients for the first and second temperatures, and for the third temperature. Compensating the impedance of the on-chip resistor circuit using a compensation coefficient. The circuit of claim 2, wherein the on-chip resistor circuit comprises: A number of resistance elements; And And a selective connection circuit for selectively connecting the plurality of resistance elements in parallel based on the compensation coefficient for the third temperature. The method of claim 3, wherein the compensation circuit A storage circuit for storing the first and second compensation coefficients; A compensation coefficient calculator configured to calculate a compensation coefficient for the third temperature by performing linear interpolation using the first and second compensation coefficients; And And a control signal output unit configured to generate a control signal for controlling the selective connection circuit based on the compensation coefficient for the third temperature. The method of claim 3, wherein the first and second compensation coefficients And is determined as a ratio between an impedance and a target impedance of the on-chip resistor circuit measured at the first and second temperatures. The method of claim 3, wherein the storage circuit And a plurality of fuses, said first and second compensation coefficients being stored by selective cutting of said plurality of fuses. The method of claim 3, wherein The semiconductor device further comprises a temperature sensor, And the third temperature is a temperature measured by the temperature sensor. In the impedance calibration method of a semiconductor memory device, (a) comprising an on-chip resistor circuit, compensating for the impedance of the on-chip resistor circuit according to the measured temperature of the semiconductor device; And (b) calibrating an impedance of at least one of an on-die termination circuit and an off-chip driving circuit based on the impedance of the temperature compensated on-chip resistance circuit. . The method of claim 8, wherein step (a) (a1) measuring impedances of the on-chip resistor circuits at first and second temperatures, respectively; (a2) determining first and second compensation coefficients which are respective compensation coefficients for the first and second temperatures; (a3) calculating a compensation coefficient for a third temperature between the first temperature and the second temperature using first and second temperatures and the first and second compensation coefficients; And (a4) compensating for the impedance of the on-chip resistance circuit based on the compensation coefficient for the third temperature. The method of claim 9, wherein step (a3) Obtaining the third temperature through temperature measurement by a temperature sensor; And And calculating a compensation coefficient for the third temperature through linear interpolation using the first and second compensation coefficients. The method of claim 9, wherein step (a2) And determining the first and second compensation coefficients by calculating a ratio between each impedance of the on-chip resistor circuit measured at the first and second temperatures and a target impedance. Calibration method. The method of claim 9, wherein step (a4) Selectively connecting a plurality of resistance elements in parallel based on the compensation coefficient for the third temperature. In a temperature compensated on-chip resistor circuit, A resistance circuit provided inside the semiconductor device; And Compensation circuit for compensating the impedance of the resistance circuit in accordance with the measured temperature of the semiconductor device, The compensation circuit Compensation coefficients for the third temperature between the first temperature and the second temperature are calculated using the first and second compensation coefficients, which are respective compensation coefficients for the first and second temperatures, and for the third temperature. Temperature compensated on-chip resistance circuit, characterized in that for compensating the impedance of the resistance circuit using a compensation coefficient. The method of claim 13, wherein the resistor circuit, A number of resistance elements; And And an optional connection circuit for selectively connecting the plurality of resistance elements in parallel based on the compensation coefficient for the third temperature. 15. The circuit of claim 14 wherein the compensation circuitry A storage circuit for storing the first and second compensation coefficients; A compensation coefficient calculator configured to calculate a compensation coefficient for the third temperature by performing linear interpolation using the first and second compensation coefficients; And And a control signal output unit for generating a control signal for controlling the selective connection circuit based on the compensation coefficient for the third temperature.

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