KR100738966B1 - Dll circuit and method for controlling the same - Google Patents

Abstract

A DLL circuit and a method for controlling the same are provided to generate a feedback clock by changing a phase of an internal clock selectively corresponding to a phase difference between a reference clock and a feedback clock. A DLL circuit includes a clock buffer(10), a delay unit(20), a phase conversion controller(70), a phase conversion unit(80), a delay compensation unit(40), a phase comparator(50), and a delay controller(60). The clock buffer(10) converts the amplitude of an external clock to generate a reference clock. The delay unit(20) push or pull delays the reference clock. The phase conversion controller(80) latches and drives a phase comparison signal, and outputs the phase comparison signal as a phase conversion control signal. The phase conversion unit(80) controls a phase of the delayed clock from the delay unit(20) according to the phase conversion control signal. The delay compensation unit(40) delays a clock from the phase conversion unit(80) to generate a feedback clock. The phase comparator(50) compares a phase of the feedback clock with the phase of the reference clock, and generates the phase comparison signal. The delay controller(60) generates and transfers the delay control signal to the delay unit(20).

Description

DLD circuit and control method {DLL Circuit and Method for Controlling the Same}

1 is a block diagram showing the configuration of a DLL circuit according to the prior art;

2A and 2B are graphs for explaining the operation of the DLL circuit shown in FIG. 1;

3 is a block diagram showing the configuration of a DLL circuit according to the present invention;

4 is an internal configuration diagram of the phase shift control means shown in FIG. 3;

5 is an internal configuration diagram of the phase shifting means shown in FIG. 3;

6A and 6B are graphs for explaining the operation of the DLL circuit shown in FIG.

<Description of the symbols for the main parts of the drawings>

10: clock buffer 20: delay means

30: data output buffer 40: delay compensation means

50: phase comparison means 60: delay control means

70: phase shift control means 80: phase shift means

The present invention relates to a DLL (Delay Locked Loop) circuit and a control method thereof, and more particularly, to a DLL circuit having a fast delay lock speed and sufficient area margin and a control method thereof.

Typically, DLL circuits are used to provide an internal clock that is time-phased relative to a reference clock obtained by converting an external clock. In general, an internal clock is generated to operate in synchronization with an external clock in a semiconductor memory device having a relatively high degree of integration, such as a synchronous DRAM (SDRAM).

In more detail, when an external clock input through the input pin is input to the clock input buffer, an internal clock is generated from the clock input buffer. The internal clock then controls the data output buffer to output data to the outside. At this time, the internal clock is delayed for a predetermined time from the external clock by the clock buffer, and output data from the data output buffer is also delayed for a predetermined time from the internal clock.

Therefore, there is a problem that the output data is output after a large time delay with respect to the external clock. In other words, there is a problem in that the time for outputting data after the external clock is applied, that is, the output data access time becomes long.

In order to solve this problem, by using the DLL circuit to make the phase of the internal clock ahead of the external clock a predetermined time, the output data can be output without delay with respect to the external clock. In other words, the DLL circuit receives an external clock and generates an internal clock that has a predetermined time phase, and the internal clock is used as a reference clock in an area such as a data output buffer.

Hereinafter, a DLL circuit according to the related art will be described with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a DLL circuit according to the prior art.

The illustrated DLL circuit 1 converts the amplitude of the external clock clk_ext to the clock buffer 10 for generating the reference clock clk_ref and the reference clock clk_ref in response to the input of the delay control signal dcl. Delay means 20 for generating a delay clock clk_dly by pushing or pulling the delay and transferring it to the data output buffer 30 for synchronizing with the data transmitted from the memory cell, the delay clock clk_dly Delay compensation means 40 for generating a feedback clock clk_fb by delaying the delay clock clk_dly to compensate for the delay time provided by the delay elements existing in the transmission path outside the semiconductor memory device of FIG. Phase comparison means 50 for generating a phase comparison signal pcm by comparing a phase of a reference clock clk_ref and the feedback clock clk_fb and the delay control signal dcl according to the control of the phase comparison signal pcm. By creating Consists of a delay control means (60) for transmitting the group delay means 20.

When the external clock clk_ext is transferred to the clock buffer 10 from the outside of the semiconductor integrated circuit to which the DLL circuit 1 belongs, the clock buffer 10 increases the external clock clk_ext having a small amplitude. The amplitude is converted into the reference clock clk_ref and transmitted to the delay means 20. Thereafter, the delay means 20 delays the reference clock clk_ref by a predetermined time and outputs the delayed clock clk_dly.

In the delay compensation means 40, delay values of delay elements existing in a path where the delay clock clk_dly output from the delay means 20 is output to the outside of the DLL circuit 1 are calculated. Therefore, the delay compensation means 40 generates the feedback clock clk_fb by giving the delay clock clk_dly a predetermined delay time for compensating the delay values of the delay elements. Thereafter, the phase comparison means 50 detects a phase difference between the feedback clock clk_fb and the reference clock clk_ref to generate the phase comparison signal pcm. The delay control means 60 generates the delay control signal dcl in response to the input of the phase comparison signal pcm. At this time, the delay control signal dcl indicates a push delay or a pull delay of the delay means 20. Thereafter, the delay means 20 gives a positive or negative delay time to the reference clock clk_ref according to the instruction of the delay control signal dcl.

2A and 2B are graphs for explaining the operation of the DLL circuit shown in FIG. 1, and FIG. 2A shows a case in which the phase of the feedback clock clk_fb precedes the phase of the reference clock clk_ref. The phase of the reference clock clk_ref precedes the phase of the feedback clock clk_fb.

In the figure, a clock is fixed in which the rising edge times of the reference clock clk_ref and the feedback clock clk_fb and the reference clock clk_ref and the feedback clock clk_fb coincide with each other.

First, as shown in FIG. 2A, when the phase of the feedback clock clk_fb precedes the phase of the reference clock clk_ref, the phase difference Trf between the reference clock clk_ref and the feedback clock clk_fb is the feedback clock. It is larger than the phase difference Tfl between clk_fb and the fixed clock. On the other hand, as shown in FIG. 2B, when the phase of the reference clock clk_ref precedes the phase of the feedback clock clk_fb, the phase difference Trf between the reference clock clk_ref and the feedback clock clk_fb is the feedback. It is smaller than the phase difference Tfl between the clock clk_fb and the fixed clock. At this time, the phase difference Tfl between the feedback clock clk_fb and the fixed clock refers to the amount of delay time that the delay means 20 should give to the reference clock clk_ref. Therefore, when the phase of the reference clock (clk_ref) is ahead of the phase of the feedback clock (clk_fb), the amount of delay time to be given to the reference clock (clk_ref) is relatively large, and thus the time required for delay lock operation is increased. It will be longer. In addition, a relatively large number of delay elements to be provided in the delay means 20 is required.

As described above, when the DLL circuit generates the fixed clock by matching the reference clock with the feedback clock, if the phase of the reference clock precedes the phase of the feedback clock, the delay time to be given to the feedback clock becomes longer. And in preparation for this case, the delay means of the DLL circuit had to be provided with more delay elements, thereby reducing the area margin.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a delay provided to fix a reference clock and a feedback clock by generating a feedback clock by selectively converting a phase of an internal clock corresponding to a phase difference between a reference clock and a feedback clock. SUMMARY OF THE INVENTION There is a technical problem to provide a DLL circuit and a method of controlling the same, which reduce time and increase the area margin by reducing the number of delay elements provided in the delay means.

According to an aspect of the present invention, a DLL circuit includes: phase shift control means for latching and driving a phase comparison signal in response to an input of a delay enable signal and outputting the phase comparison signal as a phase shift control signal; And phase shifting means for controlling the phase of the internal clock delayed by the delaying means to be transmitted to the delay compensating means according to the control of the phase shifting control signal.

In addition, the DLL circuit of the present invention comprises: phase shifting means for inverting or non-inverting driving an internal clock delayed by a delay means according to a phase comparison signal generated by a phase comparison operation between a reference clock and a feedback clock to transfer it to a delay compensation means; And phase shift control means for receiving the phase comparison signal from a phase comparison means, latching and driving the phase comparison signal, and transferring the phase comparison signal to the phase shifting means.

The control method of the DLL circuit of the present invention includes: a) latching and driving a phase comparison signal in response to a delay enable signal and outputting the phase comparison control signal; And b) controlling the phase of the internal clock delayed by the delay means according to the control of the phase shift control signal and transferring the phase to the delay compensation means.

In addition, the method of controlling a DLL circuit of the present invention includes the steps of: a) latching and driving a phase comparison signal generated by a phase comparison operation between a reference clock and a feedback clock; And b) inverting or non-inverting the internal clock delayed by the delay means according to the phase comparison signal transmitted from step a) and transferring the internal clock to the delay compensation means.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a block diagram showing the configuration of a DLL circuit according to the present invention.

As illustrated, the DLL circuit 100 converts an amplitude of an external clock clk_ext to generate a reference clock clk_ref and a clock buffer 10 corresponding to an input of a delay control signal dcl. By delaying or pushing delay (clk_ref) to generate a delay clock (clk_dly) and transmits to the data output buffer 30 to synchronize with the data transmitted from the memory cell, the delay enable signal (den) Phase shift control means 70 for latching and driving a phase comparison signal pcm in response to an input and outputting it as a phase shift control signal pcc, and the delay clock clk_dly under the control of the phase shift control signal pcc. Phase shifting means (80) for controlling the phase of the &lt; Desc / Clms Page number 5 &gt; and the phase shifting means (80) to compensate for the delay time given by the delay elements present in the transmission path outside the semiconductor integrated circuit of the delayed clock (clk_dly). ) A delay compensator 40 for delaying the clock output from the delay clock 40 to generate a feedback clock clk_fb, and generating a phase comparison signal pcm by comparing phases of the reference clock clk_ref and the feedback clock clk_fb. And a delay control means 60 for generating the delay control signal dcl in response to the input of the phase comparison means 50 and the phase comparison signal pcm and transmitting the delay control signal dcl to the delay means 20.

The delay enable signal den is a signal generated inside the delay control means 60 and used to activate the delay control means 60. In the initial stage of operation of the DLL circuit 100, the delay enable signal den is disabled, and accordingly, the delay control signal dcl is not generated. Delayed operation is not performed. However, when the delay enable signal den is enabled, the delay control signal dcl is generated to perform a delay operation on the reference clock clk_ref of the delay means 20.

When the external clock clk_ext is transferred to the clock buffer 10 from the outside of the semiconductor integrated circuit to which the DLL circuit 100 belongs, the clock buffer 10 increases the external clock clk_ext having a small amplitude. The amplitude is converted into the reference clock clk_ref and transmitted to the delay means 20. Thereafter, the delay means 20 delays the reference clock clk_ref by a predetermined time and outputs the delayed clock clk_dly.

In the delay compensation means 40, delay values of delay elements existing in a path through which the clock transmitted through the phase shift means 80 is output to the outside of the semiconductor memory device are calculated. Accordingly, the delay compensation means 40 generates the feedback clock clk_fb by giving a predetermined delay time for compensating the delay values of the delay elements to the clock transmitted through the phase shifting means 80. Thereafter, the phase comparison unit 50 detects a phase difference between the feedback clock clk_fb and the reference clock clk_ref to generate the phase comparison signal pcm. The delay control means 60 generates the delay control signal dcl in response to the input of the phase comparison signal pcm. At this time, the delay control signal dcl indicates a push delay or a pull delay of the delay means 20. Thereafter, the delay means 20 gives a positive or negative delay time to the reference clock clk_ref according to the instruction of the delay control signal dcl.

The phase comparison signal pcm is also transmitted to the phase shift control means 70. At this time, the phase comparison signal pcm contains information on which one of the reference clock clk_ref and the feedback clock clk_fb is advanced in its potential level. The phase shift control means 70 latches and drives the phase comparison signal pcm in response to the input of the delay enable signal den and outputs the phase shift control signal pcc.

Then, the phase shifting means 80 inverts the delay clock clk_dly upon receiving information from the phase shift control signal pcc that the phase of the reference clock clk_ref precedes the phase of the feedback clock clk_fb. Drive to the delay compensation means 40. On the contrary, when the phase shifting means 80 receives information from the phase shift control signal pcc that the phase of the feedback clock clk_fb precedes the phase of the reference clock clk_ref, the phase shifting means 80 receives the delay clock clk_dly. Non-inverted driving is delivered to the delay compensation means 40.

FIG. 4 is an internal configuration diagram of the phase shift control means shown in FIG. 3.

The phase shift control means 70 includes a first latch unit 710 for latching the phase comparison signal pcm in response to the input of the delay enable signal den, and an input of the delay enable signal den. In response to the input of the second latch unit 720 and the reset signal rst to latch the signal transmitted from the first latch unit 710 to initialize the output signal of the phase shift control means 70 It consists of an initialization unit 730.

Here, the first latch unit 710 may pass the first passgate PG1 and the first passgate PG1 through which the phase comparison signal pcm is passed under the control of the delay enable signal den. It includes first and second inverters (IV1, IV2) formed of a latch structure for the signal passed.

In addition, the second latch unit 720 may include a second pass gate PG2 and a second pass gate configured to pass a signal transmitted from the first latch unit 710 according to the control of the delay enable signal den. Third and fourth inverters IV3 and IV4 formed of a latch structure for the signal passing through PG2.

The initialization unit 730 may include a transistor TR for grounding the output signal of the second pass gate PG2 of the second latch unit 720 according to whether the reset signal rst is enabled. .

When the delay enable signal den input to the phase shift control means 70 configured as described above is disabled, the first pass gate PG1 of the first latch unit 710 is turned on. And the second pass gate PG2 of the second latch unit 720 is turned off so that the phase comparison signal is applied to the latch structures formed by the first and second inverters IV1 and IV2. (pcm) is stored.

However, when the delay enable signal den is enabled, the first pass gate PG1 of the first latch unit 710 is turned off and the second pass gate of the second latch unit 720 is turned on. PG2 is turned on to store a signal output from the first latch unit 710 in a latch structure formed by the third and fourth inverters IV3 and IV4.

As such, since the phase comparison signal pcm is a signal whose value continuously changes, the first and second latch units 710 operate under the control of the delay enable signal den. By generating the phase shift control signal pcm according to the value of the phase comparison signal pcm at the initial stage of the operation, the frequency shift of the phase shift means 80 is prevented by preventing the frequent level transition of the phase shift control signal pcm. This is to ensure that the operation is performed stably.

The initialization unit 730 is provided to initialize the phase shift control signal pcm to a high level signal according to the control of the reset signal rst during the initial operation of the DLL circuit 100. .

FIG. 5 is an internal configuration diagram of the phase shifting means shown in FIG. 3.

The illustrated phase shifting means 80 includes a non-inverting driver 810 and a phase shifting control signal pcm for non-inverting driving the delayed clock clk_dly under the control of the phase shift control signal pcm. The inverting driver 820 is configured to invert and output the delay clock clk_dly according to the control of.

Herein, the non-inverting driver 810 is configured to combine the first inverter chain IVC1 and the phase shift control signal pcm which are configured by a series connection combination of an even number of inverters for non-inverting the delay clock clk_dly. In accordance with the control is composed of a third pass gate (PG3) for passing the output signal of the first inverter chain (IVC1).

In addition, the inversion driver 820 is configured to control the phase shift control signal pcm and the second inverter chain IVC2 including a series connection combination of an odd number of inverters for inverting the delay clock clk_dly. And a fourth pass gate PG4 through which the output signal of the second inverter chain IVC2 is passed.

If the potential level of the phase shift control signal pcc is high, the third passgate PG3 of the non-inverting driver 810 is turned on and the fourth passgate PG4 of the inversion driver 820 is turned on. Is turned off so that the output signal of the phase shifting means 80 becomes a clock of the same type as the delay clock clk_dly. However, when the potential level of the phase shift control signal pcc is low, the third passgate PG3 of the non-inverting driver 810 is turned off and the fourth passgate PG4 of the inversion driver 820 is turned off. ) Is turned on so that the output signal of the phase shifting means 80 becomes a clock / clk_dly in which the delay clock clk_dly is inverted.

That is, when the phase of the feedback clock clk_fb precedes the phase of the reference clock clk_ref, the potentials of the phase comparison signal pcm and the phase shift control signal pcc become high levels, and thus the phase shift means 80 ) Is a clock having the same shape as the delay clock (clk_dly), and when the phase of the reference clock (clk_ref) precedes the phase of the feedback clock (clk_fb), the phase comparison signal (pmc) and the phase The potential of the conversion control signal pcc becomes low and the output signal of the phase shifting means 80 becomes a clock / clk_dly in which the delay clock clk_dly is inverted.

6A and 6B are graphs for explaining the operation of the DLL circuit shown in FIG.

In the figure, a clock is fixed in which the rising edge times of the reference clock clk_ref and the feedback clock clk_fb and the reference clock clk_ref and the feedback clock clk_fb coincide with each other.

First, as illustrated in FIG. 6A, when the phase of the feedback clock clk_fb precedes the phase of the reference clock clk_ref, the phase difference Trf between the reference clock clk_ref and the feedback clock clk_fb is determined by the feedback clock. It is larger than the phase difference Tfl between clk_fb and the fixed clock. On the other hand, as shown in FIG. 6B, when the phase of the reference clock clk_ref precedes the phase of the feedback clock clk_fb, the phase difference Trf between the reference clock clk_ref and the feedback clock clk_fb is the feedback. It is smaller than the phase difference Tfl between the clock clk_fb and the fixed clock. In this case, however, the phase shifting means 80 outputs a clock / clk_dly in which the delay clock clk_dly is inverted, and thus the phase difference Trf between the reference clock clk_ref and the inverted feedback clock / clk_fb. Is larger than the phase difference Tfl between the inverted feedback clock / clk_fb and the fixed clock.

As described above, the phase difference Tfl between the feedback clock clk_fb and the fixed clock refers to the amount of delay time that the delay means 20 should give to the reference clock clk_ref. In the related art, when the phase of the reference clock clk_ref precedes the phase of the feedback clock clk_fb, the amount of delay time that should be given to the reference clock clk_ref is relatively large. Since the inverted feedback clock (/ clk_fb) is used, the amount of delay time to be applied to the reference clock (clk_ref) is reduced in this case. Accordingly, the time taken for the delay fixing operation is reduced, and the number of delay elements to be provided in the delay means 20 can be reduced.

As described above, the DLL circuit of the present invention provides a delay time that should be given to the feedback clock even when the reference clock phase precedes the feedback clock phase when the reference clock is synchronized with the feedback clock to generate a fixed clock. Can be reduced. It is also possible to reduce the number of delay elements in the delay means of the DLL circuit, thereby increasing the area margin.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

In the above-described DLL circuit of the present invention and a method of controlling the same, a delay time is provided to fix the reference clock and the feedback clock by generating a feedback clock by selectively converting the phase of the internal clock corresponding to the phase difference between the reference clock and the feedback clock. And the area margin is increased by reducing the number of delay elements provided in the delay means.

Claims (31)

Phase shift control means for latching and driving a phase comparison signal in response to an input of a delay enable signal and outputting it as a phase shift control signal; And Phase shifting means for controlling the phase of the delayed clock delayed by the delaying means according to the control of the phase shifting control signal and transferring the phase to the delay compensation means; DLL circuit comprising a. The method of claim 1, The phase comparison signal includes information on a phase difference between a reference clock and a feedback clock, and the phase conversion unit selectively inverts and outputs the delay clock according to information transmitted by the phase comparison signal. DLL circuit. The method of claim 1, The phase shift control means, A first latch unit configured to latch the phase comparison signal in response to an input of the delay enable signal; A second latch unit for latching a signal transmitted from the first latch unit in response to an input of the delay enable signal; And An initialization unit for initializing an output signal in response to an input of a reset signal; DLL circuit comprising a. The method of claim 3, wherein The first latch unit, A passgate for passing the phase comparison signal according to the control of the delay enable signal; And First and second inverters each having a latch structure for a signal passing through the passgate; DLL circuit comprising a. The method of claim 3, wherein The second latch unit, A passgate configured to pass a signal transmitted from the second latch unit according to the control of the delay enable signal; And First and second inverters each having a latch structure for a signal passing through the passgate; DLL circuit comprising a. The method of claim 5, And the initialization unit includes a transistor configured to ground an output signal of the passgate of the second latch unit according to whether the reset signal is enabled. The method of claim 1, The phase conversion means, A non-inverting driver for non-inverting and driving the delayed clock according to the control of the phase shift control signal; And An inversion driver for inverting and driving the delayed clock according to the control of the phase shift control signal; DLL circuit comprising a. The method of claim 7, wherein The non-inverting drive unit, An inverter chain composed of a series connection combination of an even number of inverters for non-inverting driving the delay clock; And A passgate configured to pass an output signal of the inverter chain according to the control of the phase shift control signal; DLL circuit comprising a. The method of claim 7, wherein The inversion driving unit, An inverter chain composed of a series connection combination of odd inverters for inverting the delay clock; And A passgate configured to pass an output signal of the inverter chain according to the control of the phase shift control signal; DLL circuit comprising a. Phase shifting means for inverting or non-inverting driving the delayed clock delayed by the delaying means in accordance with the phase comparison signal generated by the phase comparison operation between the reference clock and the feedback clock and transferring the delayed clock to the delay compensation means; And Phase shift control means for receiving the phase comparison signal from a phase comparison means and latching and driving the phase comparison signal to transmit the phase comparison signal to the phase shifting means; DLL circuit comprising a. The method of claim 10, The phase comparison signal contains information about a phase difference between the reference clock and the feedback clock, and the phase shifting unit according to the information about the phase difference between the reference clock and the feedback clock transmitted by the phase comparison signal. And inverting the delayed clock selectively to output the delayed clock. The method of claim 10, The phase shift control means, A first latch unit configured to latch the phase comparison signal in response to an input of a delay enable signal; A second latch unit for latching a signal transmitted from the first latch unit in response to an input of the delay enable signal; And An initialization unit for initializing an output signal in response to an input of a reset signal; DLL circuit comprising a. The method of claim 12, The first latch unit, A passgate for passing the phase comparison signal according to the control of the delay enable signal; And First and second inverters each having a latch structure for a signal passing through the passgate; DLL circuit comprising a. The method of claim 12, The second latch unit, A passgate configured to pass a signal transmitted from the second latch unit according to the control of the delay enable signal; And First and second inverters each having a latch structure for a signal passing through the passgate; DLL circuit comprising a. The method of claim 14, And the initialization unit includes a transistor configured to ground an output signal of the pass gate of the second latch unit according to whether the reset signal is enabled. The method of claim 10, The phase conversion means, A non-inverting driver for non-inverting and driving the delayed clock according to the control of the phase shift control signal; And An inversion driver for inverting and driving the delayed clock according to the control of the phase shift control signal; DLL circuit comprising a. The method of claim 16, The non-inverting drive unit, An inverter chain composed of a series connection combination of an even number of inverters for non-inverting driving the delay clock; And A passgate configured to pass an output signal of the inverter chain according to the control of the phase shift control signal; DLL circuit comprising a. The method of claim 16, The inversion driving unit, An inverter chain composed of a series connection combination of odd inverters for inverting the delay clock; And A passgate configured to pass an output signal of the inverter chain according to the control of the phase shift control signal; DLL circuit comprising a. The method according to claim 2 or 10, And a clock buffer for converting an amplitude of an external clock to generate the reference clock. The method according to claim 2 or 10, And the delay means is configured to generate the delay clock by pushing or pulling the reference clock in response to an input of a delay control signal. The method according to claim 2 or 10, Delay compensation means for generating the feedback clock by delaying the clock output from the phase shifting means to compensate for the delay time given by the delay elements present in the transmission path to the outside of the semiconductor integrated circuit of the delay clock DLL circuit comprising: a. The method according to claim 1 or 10, And phase comparison means for comparing the phase of the reference clock and the feedback clock to generate the phase comparison signal. The method of claim 20, And a delay control means for generating and transmitting the delay control signal to the delay means in response to the input of the phase comparison signal. a) latching and driving a phase comparison signal in response to a delay enable signal and outputting the phase comparison control signal; And b) controlling the phase of the internal clock delayed by the delay means according to the control of the phase shift control signal and transferring the phase to the delay compensation means; Method of controlling a DLL circuit comprising a. The method of claim 24, The phase comparison signal includes information on a phase difference between a reference clock and a feedback clock, and the step b) includes selectively inverting and outputting the delay clock according to information transmitted by the phase comparison signal. DLL circuit control method. The method of claim 25, Step a) is a-1) latching the phase comparison signal in response to the input of the delay enable signal; And a-2) latching a signal transmitted from the step a-1) in response to the input of the delay enable signal; Method of controlling a DLL circuit comprising a. The method of claim 25, B), b-1) non-inverting and outputting the delay clock according to the control of the phase shift control signal; And b-2) inverting and driving the delayed clock according to the control of the phase shift control signal; Method of controlling a DLL circuit comprising a. a) latching and driving a phase comparison signal generated by a phase comparison operation between a reference clock and a feedback clock; And b) inverting or non-inverting the internal clock delayed by the delay means according to the phase comparison signal transmitted from the step a) and transferring the internal clock to the delay compensation means; Method of controlling a DLL circuit comprising a. The method of claim 28, The phase comparison signal contains information on the phase difference between the reference clock and the feedback clock, and step b) is based on the information on the phase difference between the reference clock and the feedback clock transmitted by the phase comparison signal. Selectively inverting the delay clock and outputting the delayed clock. The method of claim 29, Step a) is a-1) latching the phase comparison signal in response to an input of a delay enable signal; And a-2) latching a signal transmitted from the step a-1) in response to the input of the delay enable signal; Method of controlling a DLL circuit comprising a. The method of claim 29, B), b-1) non-inverting and outputting the delayed clock according to the control of the phase shift control signal; And b-2) inverting and driving the delayed clock according to the control of the phase shift control signal; Method of controlling a DLL circuit comprising a.

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