KR100738351B1 - PCI Express Packet Filter including Descrambling - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a PCI Express packet detection apparatus including a descrambling function.

2. The technical problem to be solved by the invention

An object of the present invention is to provide a PCI Express packet detection apparatus capable of detecting each packet for each layer including a descramble function at the packet receiving end of the PCI Express protocol.

3. Summary of Solution to Invention

The present invention provides a PCI Express packet detection apparatus comprising: physical layer packet detection means for detecting a physical layer packet from a PCI express packet received in parallel by 16 bits through a physical layer serializer / parallelizer; Descrambling means for descrambling PCI Express packets received in parallel by 16 bits through the physical layer serial / parallelizer; Data link layer packet detection means for detecting a data link layer packet from the packet output from the descrambling means; And transaction layer packet detection means for detecting a transaction layer packet in the packet output from the descrambling means.

4. Important uses of the invention

The invention is used in computing systems and the like.

PCI Express, Descrambler, Packet, Physical Layer, Datalink, Transaction

Description

PCI Express Packet Filter including descrambling function {PCI Express Packet Filter including Descrambling}

1 is a diagram illustrating an embodiment of a general PCI Express standard.

2 is a diagram illustrating an embodiment of the descrambler 210 of FIG. 1.

Figure 3 is a configuration diagram of an embodiment of a PCI Express packet detection apparatus according to the present invention.

4 is a diagram illustrating a method of applying a PCI express packet detection apparatus according to the present invention to a PCI express engine.

5 is a diagram illustrating an embodiment of a physical layer packet detector of a PCI express packet detection apparatus according to the present invention;

FIG. 6 is a diagram illustrating an embodiment of the scrambler of FIG. 4. FIG.

* Explanation of symbols for the main parts of the drawings

300: PCI express packet detection device 310: physical layer packet detector

320: data link layer packet detector 330: transaction layer packet detector

340: Descrambler

The present invention is a packet detection device used for a receiver of a PCI Express (hereinafter referred to as "PCI Express") 1x protocol, which is a next generation computer input / output (I / O) standard.

PCI Express consists of three layers: the physical layer, the data link layer, and the transaction layer. The types and types of packets handled by each layer are different.

The PCI Express protocol converts control and data characters in byte units of 8 bits into symbol units of 10 bits and transmits them at 2.5 Gbps high frequency.In the high frequency transmission, energy is concentrated on specific frequencies by repetitive patterns. Scrambling techniques are used to prevent the generation of electromagnetic interference (EMI) noise. Therefore, the descrambling function must be included in the packet detector.

The data bandwidth for a 2.5 Gbps signal can be designed as 8 bits in a 250 MHz design. However, a 125 MHz design is common when a circuit using a low speed device is used. Therefore, the PCI bandwidth should be designed based on 16 bits. Since the standard only proposes a descrambling method for 8-bit parallel processing, it is necessary to extend it for 16-bit parallel processing.

In the related art, a simple scrambler is used to store a buffer for checking packets in advance in order to process unscrambled packets used in the physical layer, and the circuit is duplicated by double checking the packets in the physical layer. There was a problem.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a PCI Express packet detection apparatus capable of detecting each packet for each layer including a descramble function at a packet receiving end of the PCI Express protocol.

Other objects and advantages of the present invention can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. Also, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

According to an aspect of the present invention, there is provided a PCI Express packet detecting apparatus comprising: physical layer packet detection means for detecting a physical layer packet from a PCI express packet received in parallel by 16 bits through a physical layer serializer / parallelizer; Descrambling means for descrambling PCI Express packets received in parallel by 16 bits through the physical layer serial / parallelizer; Data link layer packet detection means for detecting a data link layer packet from the packet output from the descrambling means; And transaction layer packet detection means for detecting a transaction layer packet in the packet output from the descrambling means.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating an embodiment of a general PCI Express specification, and is used in a PCI Express specification or a general design.

The PCI Express standard includes a physical layer serializer / parallelizer 100, a physical layer 110, a data link layer 120, and a transaction layer 130. In particular, the physical layer 110 includes a descrambler 111, a packet detector 112, a physical layer processing engine 113, a packet generator 114, and a scrambler 115.

In the figure, PCI Express packets received in parallel by 16 bits through the physical layer serializer / parallelizer 100 pass through the descrambler 111, and the packet passing through the descrambler 111 passes through the packet detector 112. The packet type input to the physical layer processing engine 113 through the physical layer processing engine 113 is replaced with a detection signal in the case of a packet used in the physical layer engine, and the other packets are descrambled. The data is input in the form of a packet and transferred to the data link layer 120.

Packets input to the data link layer 120 are packets processed by the data link layer 120 and packets processed by the transaction layer 130, and packets used by the data link layer 120 are the data link layer 120. Used in, the packet to be processed in the transaction layer 130 is transferred to the transaction layer 130 to be processed in the transaction layer 130.

FIG. 2 is a diagram illustrating an embodiment of the descrambler 210 of FIG. 1.

The descrambler 210 includes a packet buffer 211, a physical layer packet discriminator 212, and a descrambler engine 213.

Since the descrambler 210 requires an additional packet buffer 211 to detect a physical layer packet to which scramble is not applied, a delay time is generated, and the contents of the packet buffer 211 are physically A physical layer packet discriminator 212 is required to determine whether the layer packet is a layer packet.

When the PCI Express packet receiver passes through a physical layer deserializer, the 2.5 Gbps serial input signal is converted into a 16-bit parallel signal.

It is an object of the present invention to extract a packet used in each layer of PCI Express from the parallel-converted data into 16 bits, and since the scramble is not used in the case of the physical layer packet, the descrambler 210 passes through the packet detection. There is no need to do it.

In the packet transmitter, the transmission unit of the packet is 8-bit unit, which is converted into 10-bit symbol and transmitted. Therefore, the input signal cannot be regarded as being aligned in 16-bit unit. There is a need for a circuit capable of detecting packets.

Since the data link layer packet and the transaction layer packet are transmitted in scrambled form, the descrambler must be implemented in the packet detection apparatus, the existing 8 bits must be extended, and the packet must be detected regardless of alignment. In the final output stage, the circuit should be configured to output in the form of 16 bits.

3 is a block diagram of an embodiment of a PCI Express packet detection apparatus according to the present invention.

As shown in FIG. 3, the PCI express packet detecting apparatus according to the present invention first detects a physical layer packet from a PCI express packet received in parallel by 16 bits through a physical layer serializer / parallelizer 100. Descrambler 340 for descrambling PCI Express packets received in parallel by 16 bits through the detector 310, the physical layer serializer / parallelizer 100, and the data link layer in the packets output from the descrambler 340. A data link layer packet detector 320 for detecting a packet, and a transaction layer packet detector 330 for detecting a transaction layer packet in the packet output from the descrambler 340.

Since the physical layer packet is input in an unscrambled form, the physical layer packet detector 310 directly receives a signal that does not go through the descrambler 340, and the descrambler 340 receives the packet regardless of whether the physical layer packet is a physical layer packet. Since all of the descramblers are required, the descrambler 340 does not require the packet buffer 211 and the physical layer packet discriminator 212 shown in FIG. 2, and may be configured of only the descrambler engine 213.

4 is a diagram illustrating an embodiment of a method for applying a PCI express packet detection apparatus according to the present invention to a PCI express engine.

The packet to be used in the physical layer processing engine 430 and the packet to be used in the data link layer 440 and the packet to be used in the transaction layer 450 are classified in advance by use of the PCI Express packet detection apparatus according to the present invention. Since it is possible to design independently for each layer, and if such a structure is applied to the packet transmission side, packets that need to be transmitted by the physical layer processing engine 430 are not passed through the scrambler 470, and the data link layer ( Since the scrambler 470 is used only in the 440 and the transaction layer 450, the scrambler 470 needs only the scrambler engine without the physical layer packet discriminator 212 and the packet buffer 211 shown in FIG. 2.

However, the packet multiplexer 480 is required instead. In PCI Express, since the order in which the packets are generated in each layer is defined, the packet multiplexer 480 is only a complicated circuit.

Here, since the scrambling algorithm is the same as the descrambling algorithm, the descrambler 210 used in FIG. 2 is used as the scrambler 470.

FIG. 5 is a diagram illustrating an embodiment of a physical layer packet detector of a PCI Express packet detector according to the present invention, and illustrates a circuit for packet alignment used in the physical layer packet detector 310.

The physical layer packet detector 310 may be equally used in the data link layer packet detector 320 and the transaction layer packet detector 330 only by changing the packet start detection circuit 510.

If a packet start is detected in the lower 8-bit data 560, the packet start detection circuit 510 outputs an input of the upper 8-bit data 550 directly input, and the lower 8 bits in the packet start detection circuit 510. Similarly, the multiplexer 540 sends a control signal to directly output the lower 8-bit data 560 which is directly input, and when a packet start is detected from the upper 8-bit data 550, the packet start detection circuit 510 receives the upper 8 bits. The multiplexer 530 outputs an input of the directly input lower 8-bit data 560, and the lower 8-bit multiplexer 540 sends a control signal to output a value that has passed through the 8-bit flip-flop 520 so that the lower 8 is always the lower 8 The data output in bits indicates the beginning of the packet.

The polynomial of the Linear Feedback Shift Register (LFSR) of the PCI Express scrambler is hereinafter referred to as [Equation 1], and a circuit for scramble operation in units of bits is shown in FIG.

G (X) = X ¹⁶ + X ⁵ + X ⁴ + X ³ +1

FIG. 6 is a diagram illustrating an embodiment of the scrambler shown in FIG. 4 and illustrates a scrambler structure of LFSR and output data, which are performed in bit units.

As shown in FIG. 6, the registers of D0 to D15 displayed at the top are LFSRs, and the values of D7 to D0 displayed at the bottom represent descrambled data.

The LFSR has FFFF as an initial value, and the value is fed back and changed in accordance with the data clock cycle.

If a COM symbol is input to the LFSR, this value is re-initialized to FFFF. If a SKP symbol is input, the feedback and shift functions of the LFSR are stopped.

Since the operation of bit unit is operated at 2GHz, that is, "1-bit x 2GHz = 2Gbps", it is required to operate at 250MHz with "8bit x 250MHz = 2Gbps" in 8-bit unit, and "16bit x 125MHz in 16-bit unit". = 2Gbps "requires 125MHz operation. In addition, since 8-bit units are converted into 10-bit symbols, it is easy to design 8-bit symbols. However, when used in a low-speed device, it is not easy to have an operation speed of 250 MHz. In the present invention, a circuit for operating them at 125 MHz is designed. It was.

Since the symbol is originally in 8-bit units, there is no guarantee that it is aligned in 16-bit units. Therefore, there is a need for a circuit design that can correctly send LFSR and data output values for both unaligned and aligned cases.

In the present invention, a calculation formula is composed of COM, a general data symbol (referred to as Sym), and all combinations that may occur in SKP. Accordingly, the formula of LFSR is as follows.

When {SKP, COM}, {COM, SKP}, {COM, Sym}, {COM, COM} are input: LFSR is initialized to FFFF.

When {SYM, COM} is entered: LFSR is initialized to E817.

When {SYM, SKP}, {SKP, SYM} is entered

LFSR [0] = LFSR [8];

LFSR [1] = LFSR [9];

LFSR [2] = LFSR [10];

LFSR[ 8];LFSR [3] = LFSR [11]

LFSR [8];

LFSR[ 9]

LFSR[ 8];LFSR [4] = LFSR [12]

LFSR [9]

LFSR [8];

LFSR[10]

LFSR[ 9]

LFSR[ 8];LFSR [5] = LFSR [13]

LFSR [10]

LFSR [9]

LFSR [8];

LFSR[11]

LFSR[10]

LFSR[ 9];LFSR [6] = LFSR [14]

LFSR [11]

LFSR [10]

LFSR [9];

LFSR[12]

LFSR[11]

LFSR[10];LFSR [7] = LFSR [15]

LFSR [12]

LFSR [11]

LFSR [10];

LFSR[13]

LFSR[12]

LFSR[11];LFSR [8] = LFSR [0]

LFSR [13]

LFSR [12]

LFSR [11];

LFSR[14]

LFSR[13]

LFSR[12];LFSR [9] = LFSR [1]

LFSR [14]

LFSR [13]

LFSR [12];

LFSR[15]

LFSR[14]

LFSR[13];LFSR [10] = LFSR [2]

LFSR [15]

LFSR [14]

LFSR [13];

LFSR[15]

LFSR[14];LFSR [11] = LFSR [3]

LFSR [15]

LFSR [14];

LFSR[15];LFSR [12] = LFSR [4]

LFSR [15];

LFSR [13] = LFSR [5];

LFSR [14] = LFSR [6];

LFSR [15] = LFSR [7];

When {Sym, Sym} is entered

LFSR[13]

LFSR[12]

LFSR[11];LFSR [0] = LFSR [0]

LFSR [13]

LFSR [12]

LFSR [11];

LFSR[14]

LFSR[13]

LFSR[12];LFSR [1] = LFSR [1]

LFSR [14]

LFSR [13]

LFSR [12];

LFSR[15]

LFSR[14]

LFSR[13];LFSR [2] = LFSR [2]

LFSR [15]

LFSR [14]

LFSR [13];

LFSR[15]

LFSR[14]

LFSR[ 0]

LFSR[13]

LFSR[12]

LFSR[11];LFSR [3] = LFSR [3]

LFSR [15]

LFSR [14]

LFSR [0]

LFSR [13]

LFSR [12]

LFSR [11];

LFSR[ 2]

LFSR[15]

LFSR[14]

LFSR[13]

LFSR[ 1]

LFSR[14]

LFSR[13]

LFSR[12]

LFSR[ 0]

LFSR[13]

LFSR[12]

LFSR[11];LFSR [5] = LFSR [5]

LFSR [2]

LFSR [15]

LFSR [14]

LFSR [13]

LFSR [1]

LFSR [14]

LFSR [13]

LFSR [12]

LFSR [0]

LFSR [13]

LFSR [12]

LFSR [11];

LFSR[ 3]

LFSR[15]

LFSR[14]

LFSR[ 2]

LFSR[15]

LFSR[14]

LFSR[13]

LFSR[ 1]

LFSR[14]

LFSR[13]

LFSR[12];LFSR [6] = LFSR [6]

LFSR [3]

LFSR [15]

LFSR [14]

LFSR [2]

LFSR [15]

LFSR [14]

LFSR [13]

LFSR [1]

LFSR [14]

LFSR [13]

LFSR [12];

LFSR[ 4]

LFSR[15]

LFSR[ 3]

LFSR[15]

LFSR[14]

LFSR[ 2]

LFSR[15]

LFSR[14]

LFSR[13];LFSR [7] = LFSR [7]

LFSR [4]

LFSR [15]

LFSR [3]

LFSR [15]

LFSR [14]

LFSR [2]

LFSR [15]

LFSR [14]

LFSR [13];

LFSR[ 5]

LFSR[ 4]

LFSR[15]

LFSR[ 3]

LFSR[15]

LFSR[14];LFSR [8] = LFSR [8]

LFSR [5]

LFSR [4]

LFSR [15]

LFSR [3]

LFSR [15]

LFSR [14];

LFSR[ 6]

LFSR[ 5]

LFSR[ 4]

LFSR[15];LFSR [9] = LFSR [9]

LFSR [6]

LFSR [5]

LFSR [4]

LFSR [15];

LFSR[ 7]

LFSR[ 6]

LFSR[ 5];LFSR [10] = LFSR [10]

LFSR [7]

LFSR [6]

LFSR [5];

LFSR[ 8]

LFSR[ 7]

LFSR[ 6];LFSR [11] = LFSR [11]

LFSR [8]

LFSR [7]

LFSR [6];

LFSR[ 9]

LFSR[ 8]

LFSR[ 7];LFSR [12] = LFSR [12]

LFSR [9]

LFSR [8]

LFSR [7];

LFSR[10]

LFSR[ 9]

LFSR[ 8];LFSR [13] = LFSR [13]

LFSR [10]

LFSR [9]

LFSR [8];

LFSR[11]

LFSR[10]

LFSR[ 9];LFSR [14] = LFSR [14]

LFSR [11]

LFSR [10]

LFSR [9];

LFSR[12]

LFSR[11]

LFSR[10];LFSR [15] = LFSR [15]

LFSR [12]

LFSR [11]

LFSR [10];

The lower 8 bits of the data output value are output as they are when the lower 8 bits of the input data are the control characters.

LFSR[15];Output data [0] = input data [0]

LFSR [15];

LFSR[14];Output data [1] = input data [1]

LFSR [14];

LFSR[13];Output data [2] = input data [2]

LFSR [13];

LFSR[12];Output data [3] = input data [3]

LFSR [12];

LFSR[11];Output data [4] = input data [4]

LFSR [11];

LFSR[10];Output data [5] = input data [5]

LFSR [10];

LFSR[ 9];Output data [6] = input data [6]

LFSR [9];

LFSR[ 8];Output data [7] = input data [7]

LFSR [8];

If the upper 8 bits of the data output value, which is also input, is output as the control character,

If {Sym, COM} is entered,

Output data [8] = not input data [9];

Output data [9] = not input data [10];

Output data [10] = not input data [11];

Output data [11] = not input data [12];

Output data [12] = not input data [13];

Output data [13] = not input data [14];

Output data [14] = not input data [15];

Output data [15] = not input data [16];

If {Sym, SKP} is entered

LFSR[15];Output data [8] = input data [9]

LFSR [15];

LFSR[14];Output data [9] = input data [10]

LFSR [14];

LFSR[13];Output data [10] = input data [11]

LFSR [13];

LFSR[12];Output data [11] = input data [12]

LFSR [12];

LFSR[11];Output data [12] = input data [13]

LFSR [11];

LFSR[10];Output data [13] = input data [14]

LFSR [10];

LFSR[ 9];Output data [14] = input data [15]

LFSR [9];

LFSR[ 8];Output data [15] = input data [16]

LFSR [8];

When {Sym, Sym} is entered

LFSR[ 7];Output data [8] = input data [9]

LFSR [7];

LFSR[ 6];Output data [9] = input data [10]

LFSR [6];

LFSR[ 5];Output data [10] = input data [11]

LFSR [5];

LFSR[ 4]

LFSR[15];Output data [11] = input data [12]

LFSR [4]

LFSR [15];

LFSR[ 3]

LFSR[15]

LFSR[14];Output data [12] = input data [13]

LFSR [3]

LFSR [15]

LFSR [14];

LFSR[ 2]

LFSR[15]

LFSR[14]

LFSR[13];Output data [13] = input data [14]

LFSR [2]

LFSR [15]

LFSR [14]

LFSR [13];

LFSR[ 1]

LFSR[14]

LFSR[13]

LFSR[12];Output data [14] = input data [15]

LFSR [1]

LFSR [14]

LFSR [13]

LFSR [12];

LFSR[ 0]

LFSR[13]

LFSR[12]

LFSR[11];Output data [15] = input data [16]

LFSR [0]

LFSR [13]

LFSR [12]

LFSR [11];

As described above, the method of the present invention may be implemented as a program and stored in a recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, magneto-optical disk, etc.) in a computer-readable form. Since this process can be easily implemented by those skilled in the art will not be described in more detail.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by the drawing.

As described above, the present invention can classify packets for each layer in the PCI Express protocol, reduce unnecessary buffer usage by distributing packets for each layer, and use a 16-bit descrambler capable of low speed devices. Gbps can be implemented at 125MHz operating speed, and since the data sorter is included inside, the input data is output in the sorted form in the output form, so no separate sorter is required. In addition, if the result of the present invention is used, it is not necessary to duplicately inspect the packet, thereby reducing the waste of the circuit.

Claims (3)

In the PCI Express packet detection device, Physical layer packet detection means for detecting a physical layer packet from a PCI Express packet received in parallel by 16 bits through a physical layer serializer / parallelizer; Descrambling means for descrambling PCI Express packets received in parallel by 16 bits through the physical layer serial / parallelizer; Data link layer packet detection means for detecting a data link layer packet from the packet output from the descrambling means; And Transaction layer packet detection means for detecting a transaction layer packet from the packet output from the descrambling means PCI Express packet detection device comprising a. The method of claim 1, The physical layer packet detection means, When the packet start is detected in the lower 8-bit data, the packet start detection circuit outputs the input of the upper 8-bit data directly inputted by the upper 8-bit multiplexer, and the lower 8-bit multiplexer also directly outputs the lower 8-bit data directly input. When a packet start is detected in the upper 8-bit data, the upper 8-bit multiplexer directly outputs the input of the lower 8-bit data, and the lower 8-bit multiplexer outputs an 8-bit flip-flop. PCI Express packet detection device, characterized in that by sending a control signal to output a value passed through the data to always output the lower 8 bits indicating the beginning of the packet. The method according to claim 1 or 2, The descrambling means, PCI Express packet detection, using the same as the scrambler, and classifying the input data in the linear feedback shift register (LFSR) and the output data operation in the operation of the scrambler and calculating the bit unit operation in 16 bit units. Device.

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