KR100735848B1 - Level converting circuit efficiently increasing an amplitude of a small-amplitude signal - Google Patents

Abstract

The gate 9 of the N-channel drive transistor 6 driving the output node 2 is driven in accordance with the input signal IN through the capacitor 8. By outputting the voltage of the source node 4 of the drive transistor 6 as an output signal to the output node, the voltage of the low level of the input signal IN having voltages VDD and GND higher than this source node voltage (-VL). Level conversion can be performed. By reducing the number of steps of the level converting circuit, a level converting circuit capable of level converting an input signal having an arbitrary logic level is realized.

Amplitude, level shift, transistor, signal, semiconductor, gate, node

Description

LEVEL CONVERTING CIRCUIT EFFICIENTLY INCREASING AN AMPLITUDE OF A SMALL-AMPLITUDE SIGNAL}             

1 is a diagram showing the configuration of a level converting circuit according to Embodiment 1 of the present invention.

FIG. 2 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG.

3A and 3B show an alternative example of the resistance element shown in FIG. 1.

4A and 4B show still another alternative example of the resistance element shown in FIG. 1.

5 is a diagram schematically showing the configuration of the level conversion circuit according to the second embodiment of the present invention.

FIG. 6 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG.

Fig. 7 is a diagram showing the configuration of the level conversion circuit according to the third embodiment of the present invention.

8 is a diagram showing a modification of the third embodiment of the present invention.

FIG. 9 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG.

Fig. 10 is a diagram showing the configuration of the level conversion circuit according to the fourth embodiment of the present invention.

FIG. 11 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG.

12 is a diagram showing a modification of the fourth embodiment of the present invention.

Fig. 13 is a diagram showing the configuration of the level conversion circuit according to the fifth embodiment of the present invention.

FIG. 14 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG.

Fig. 15 is a diagram showing the configuration of main parts of the level conversion circuit according to the sixth embodiment of the present invention.

16 is a signal waveform diagram illustrating the operation of the circuit shown in FIG. 15.

17 is a diagram showing a modification of the sixth embodiment of the present invention.

Fig. 18 is a diagram showing the configuration of main parts of the level conversion circuit according to the seventh embodiment of the present invention.

Fig. 19 is a diagram showing the configuration of main parts of the level conversion circuit according to the eighth embodiment of the present invention.

20 is a signal waveform diagram illustrating the operation of the power-on reset circuit shown in FIG. 19.

FIG. 21 is a diagram schematically showing an example of the configuration of the power-on reset circuit shown in FIG. 19.

FIG. 22 is a signal waveform diagram illustrating the operation of the power-on reset circuit shown in FIG. 21.

* Explanation of symbols for main parts of drawings *

1: input node 2: output node

3: High side power node 4: Low side power node

5, 7: resistor element 8: capacitor element

6: MOS transistor 11: input node

12: Output node 13: High side power node

14: low power supply node 16: MOS transistor

15, 17: current driving device 18: capacitor

20: bootstrap load circuit 23: capacitor

22, 24: MOS transistor 30: Bootstrap type load circuit

33, 32: MOS transistor 33: capacitor

40: output drive circuit 41-43, 45, 46: MOS transistor

44: capacitive element 50: final output node

60: push pull stage 62: final output node

100: input conversion stage 110: push pull stage

120: Bootstrap type drive stage 130: Latios bootstrap type final output stage

160: final output node Q1-Q15: MOS transistor

CP1-CP3: Capacitive element 200: MOS transistor

210: resistance element 220: MOS transistor

230: power-on reset circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit for converting a signal amplitude, and more particularly, to a level conversion circuit using one type of insulated gate type field effect transistor.

In semiconductor devices, CMOS circuits composed of P-channel MOS transistors (insulated gate field effect transistors) and N-channel MOS transistors are widely used. In this CMOS circuit, from the characteristics of the threshold voltage of the MOS transistor, the P-channel MOS transistor is turned on at the time of H-level (logic high level) signal output, and the N-channel MOS is output at the time of L-level (logical low level) signal output. It is common to conduct a transistor. In the CMOS circuit, charge / discharge current flows when the output signal changes, but no current flows when the output signal stabilizes, thereby reducing power consumption.

In the semiconductor device, an internal voltage of a voltage level different from the power supply voltage and the ground voltage may be used in some cases. When the internal voltage is higher than the power supply voltage or lower than the ground voltage, a signal that is changed between the power supply voltage and the ground voltage is transmitted between the internal voltage and the ground voltage, or between the power supply voltage and the internal voltage or the first and second voltages. There is a need for a level conversion circuit for converting a signal that varies between internal voltages.

In the case where such a level conversion circuit is constituted by a CMOS circuit, it is necessary to use P and N channel MOS transistors, and the number of manufacturing steps increases, so that an example of configuring a level conversion circuit using one type of MOS transistor is disclosed in Japanese Patent Laid-Open. 2002-328643 is disclosed.

In the level conversion circuit shown in this prior document, a signal that is changed between the ground voltage and the power supply voltage VDD1 is converted into a signal that is changed between the internal voltage VDD2 that is higher than the ground voltage and the power supply voltage VDD1. In the level conversion circuit shown in this prior document, an input terminal composed of an N-channel MOS drive transistor connected in series with a diode-connected load element and receiving an input signal at a gate, and between an internal voltage supply node and a ground node. A push-pull output stage composed of N-channel MOS transistors connected in series, and a capacitive element connected between the output node of the push-pull output stage and the output node of the input stage. The gate of the high side MOS drive transistor of this output stage is coupled to the output node of the input stage, and the input signal is supplied to the gate of the low side MOS drive transistor of the output stage.

The capacitive element is used as the bootstrap capacity. Now consider a state where the input signal is at a low level, the drive transistor is turned off at the input terminal, and the low side drive transistor is turned off at the output terminal. In this state, when the voltage level of the output signal from the output terminal rises in response to the input signal, the gate voltage of the high-side MOS drive transistor of the output terminal is made higher than the internal voltage VDD2 by the bootstrap effect of the capacitor. Generates a signal at the level of VDD2.

When the input signal is at high level, the output signal is driven to the ground voltage level by the low side MOS drive transistor at the output terminal. At this time, the output signal of the input terminal becomes the low level of the voltage level determined by the on-resistance of the diode-connected load MOS transistor and the drive transistor, and the high side MOS drive transistor of the output terminal is turned off.

This prior document aims to reduce the number of steps by eliminating the step of forming the P-channel MOS transistor using only the N-channel MOS transistor in the level conversion circuit.

In the configuration of the level conversion circuit shown in this prior document, the gate of the high side MOS drive transistor at the output terminal is set to the floating state, the gate voltage level is raised by the bootstrap action of the capacitor, and the high level of the input signal is obtained. A signal having a high level voltage VDD2 higher than the voltage VDD1 is generated. The low level voltage of the input signal and the low level voltage of the output signal are both ground voltages. By supplying an input signal to the gate of the drive transistor of the input terminal and the gate of the low side MOS drive transistor of the output terminal in common, the level conversion of the high level voltage of the input signal can be performed.

However, when the N-channel MOS transistor is used, the low level voltage of the output signal cannot be lower than the ground voltage. When the low-side MOS transistor of the output stage is coupled to a negative voltage source instead of the ground node, a through-current flows through the output stage because the low-side MOS drive transistor of the output stage does not turn off even when the gate is grounded. The level of the high level voltage of the output signal decreases.

When a low level signal having a negative voltage level lower than this ground voltage is generated, the voltage polarity is reversed in the structure of this prior document, and a low level voltage of a negative voltage level can be generated by making the MOS transistor P channel. have. However, in this case, the high level voltage becomes the same power supply voltage level in the input signal and the output signal.

Therefore, in the case of the structure of this prior document, it is not possible to convert the low level voltage of the input signal to a voltage level lower than the low level voltage using only the N-channel MOS transistor. Similarly, only the P-channel MOS transistor can be used to generate an output signal having a high level voltage having a voltage level higher than that of the input signal.

In the case of the structure of this prior art document, the level conversion of both the high level voltage and the low level voltage of the input signal cannot be performed in a common circuit configuration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a level conversion circuit that can easily level convert a signal voltage of any logic level by using a single conductive MOS transistor.

Another object of the present invention is to provide a level converting circuit capable of converting a low level voltage to a lower voltage level using only an N-channel MOS transistor.

It is still another object of the present invention to provide a level converting circuit capable of converting a high level voltage to a voltage level higher than this using only a P-channel MOS transistor.

The level converting circuit according to the present invention has a first power supply and a second power supply, and input signals having an amplitude smaller than the voltage difference between the first and second power supplies are between voltage levels corresponding to the voltages of the first and second power supplies. A level converting circuit for converting a signal to be changed into a first MOS transistor coupled between an output node and a first power supply, and a first coupled MOS transistor coupled between a node receiving an input signal and a gate of the first MOS transistor. The first capacitor includes a first capacitor, a first current driver coupled between the gate of the first MOS transistor and the first power source, and a second current driver coupled between the second power source and the output node.

The gate potential of the first MOS transistor is changed to the amplitude of the input signal on the basis of the voltage level of the first power supply by the capacitive coupling or charge pump operation of the capacitor. Therefore, it is possible to reliably set the first MOS transistor in the conducting / non-conducting state according to the input signal, thereby converting the voltage level of the logic level corresponding to the first power supply voltage of the input signal to the first power supply voltage level.

For example, when the first MOS transistor is an N-channel MOS transistor and the first power supply voltage is a negative voltage, the gate of the first MOS transistor is changed between the negative voltage and a voltage higher than that. Therefore, when the input signal is high level, the first MOS transistor conducts and the output signal becomes the negative voltage level. When the input signal is low level, the gate potential of the first MOS transistor becomes the low level of the negative voltage level and is not conducted. In this state, the output signal can be set to a high level by the second current driving element.

In the case where the first MOS transistor is a P-channel MOS transistor, the gate potential of the first MOS transistor is changed between the first power supply voltage and a lower voltage level by the capacitive element, and according to the input signal, the first MOS transistor. Can be set to the conductive / non-conducting state. When the input signal is at the low level, the gate potential of the first MOS transistor is at the low level and becomes a conductive state, and a signal of the first power supply voltage level is generated as an output signal.

The above and other objects, features, aspects and advantages of the present invention will become apparent from the following detailed description of the invention which is understood in conjunction with the accompanying drawings.

[Examples of the Invention]

(Example 1)

Fig. 1 is a diagram showing the configuration of the level converting circuit according to the first embodiment of the present invention. The level converting circuit shown in FIG. 1 includes a signal IN having a high level of the voltage VDD and a low level of the reference voltage level GND, a constant voltage VH whose high level is higher than the voltage VDD, and a negative voltage -VL whose low level is lower than the reference voltage GND. Generate signal / OUT. The voltage VDD and the constant voltage VH may be the same voltage level, and the voltage VH may be a voltage level different from the voltage VDD. The reference voltage GND supplies the measurement reference level of each voltage and is usually a ground voltage level.

In Fig. 1, the level conversion circuit includes a resistance element 5 connected between the high side power supply node 3 and the output node 2, and N connected between the output node and the sub power supply node 4. The channel MOS transistor 6, the capacitor 8 connected between the signal input node 1 and the gate node 9 of the MOS transistor 6, the gate node 9 and the low side power supply node 4. The resistance element 7 is connected between them.

The high voltage power supply node 3 is supplied with the constant voltage VH, and the low power supply node 4 is supplied with the negative voltage -VL.

The resistance element 5 has a resistance value RL, and the resistance element 7 has a resistance value RG. These resistance elements 5 and 7 function as current drive elements. The capacitor 8 has a capacitor value Cc.

The input signal IN is changed between the voltage VDD and the reference voltage GND. On output node 2, output signal / OUT which inverts input signal IN is generated.

FIG. 2 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. Hereinafter, with reference to FIG. 2, the operation | movement of the level conversion circuit shown in FIG. 1 is demonstrated.

At time t0, the level converting circuit is in a steady state, and the input signal IN supplied to the input node 1 is referred to as the reference voltage GND level. At this time, the gate node 9 is maintained at the negative voltage -VL level by the resistance element 7, and the MOS transistor 6 has the same voltage between the gate and the source, and is in a non-conductive state. In this state, the output signal / OUT from the output node 2 is charged from the high side power supply node 3 via the resistance element 5 to be at the constant voltage VH level.

At time t1, when the input signal IN supplied to the input node 1 rises from the reference voltage GND to the voltage VDD level, this voltage change is transmitted to the gate node 9 through the capacitor 8. Since the gate node 9 has parasitic capacitances such as the gate capacitance of the MOS transistor 6 and the wiring capacitance of the gate node 9, these parasitic capacitances reduce the level of the voltage coupled to the gate node 9 by the capacitor 8. Let's do it. Here, it is assumed that the capacitance value Cc of the capacitor 8 is set sufficiently large with respect to such parasitic capacitance, and the potential change of the voltage VDD is transmitted to the gate node 9.

If the time constant determined by the product of the resistance value RG of the resistance element 7 and the capacitance value Cc of the capacitor 8 is set to be sufficiently larger than the period of the high level of the input signal IN, the voltage of the gate node 9 is negative. The voltage level rises from -VL by the voltage VDD and gradually decreases with the time constant determined by the resistor element 7 and the capacitor element 8.

At time t1, the voltage VDD is applied between the gate and the source of the MOS transistor 6 by the voltage rise of the gate node 9. If the threshold voltage of the MOS transistor is set to be sufficiently lower than this voltage VDD, the MOS transistor 6 is turned on, and the voltage level of the output node 2 drops to -VL + ΔVL1. Here, the voltage ΔVL1 is an output offset voltage determined by the ratio of the on resistances of the resistor 5 and the MOS transistor 6. Therefore, when the voltage level of the gate node 9 decreases due to the discharge by the resistive element 7, the on-resistance of the MOS transistor 6 increases, and this output offset voltage ΔVL1 also increases.

At time t2, when the input signal IN falls from the voltage VDD to the reference voltage GND, this voltage change is transmitted to the gate node 9 through the capacitor 8, and the voltage of the gate node 9 is equal to the voltage VDD. Lowers. At the time t2, if the voltage level of the gate node 9 is lowered by the voltage? VH due to the discharge through the resistance element 7 compared to the time t1, the voltage level of the gate node 9 is lower than the negative voltage -VL. It becomes a level. As a result, the MOS transistor 6 is brought into a non-conductive state, the output node 2 is charged by the resistance element 5, and the voltage level thereof becomes the constant voltage VH level again.

Here, the voltage level of the output node 2 rises from -VL + ΔVL2 to the constant voltage VH at time t2. The on-resistance of the MOS transistor 6 gradually increases as the gate potential decreases, This is because the output offset voltage level rises.

By setting the voltages ΔVH and ΔVL2 so that both the high level and the low level of the output signal / OUT from this output node 2 are outside the input logic threshold level of the circuit of the next stage, the voltage VDD and GND are changed between the voltages VDD and GND. The input signal IN can be converted into a signal which varies between the voltages VH and? VL2-VL.

At this time, the voltage ΔVH is determined by the capacitance value Cc of the capacitor 8, the resistance RG of the resistor 7 and the high level period of the input signal IN. The voltage VL2 is determined by the channel resistance when the gate-source voltage of the MOS transistor 6 is the voltage VDD-ΔVH, and the resistance value RL of the resistor 5. By setting these parameters suitably, voltage (DELTA) VH and (DELTA) VL2 can be made small enough.

(Change example 1)

FIG. 3A is a diagram showing a modification of the resistance element 5 shown in FIG. 1. In FIG. 3A, instead of the resistor 5, the constant current source 5a having the same current driving force as that of the resistor 5 is connected between the high side power supply node 3 and the output node 2. As shown in FIG.

3B is a diagram illustrating a modification of the resistance element 7. In the configuration shown in FIG. 3B, instead of the resistance element 7, the constant current source 7a having the same current driving force as that of the resistance element 7 is connected between the gate node 9 and the low side power supply node 4.

That is, in the structure shown in these FIGS. 3A and 3B, the resistance elements 5 and 7 are replaced with the constant current sources 5a and 7a in the level conversion circuit shown in FIG. In this case, the rising speed of the output signal / OUT can be accurately set by the drive current of the constant current source 5a. The low level of the output signal / OUT is determined according to the current supplied from the constant current source 5a and the on resistance of the MOS transistor 6. In addition, the discharge speed of the gate node 9 can be accurately set by this constant current source 7a, and the potential drop amount ΔVH of the gate node 9 can be sufficiently reduced by sufficiently reducing the driving current amount of the constant current source 7a.

(Change example 2)

FIG. 4A is a diagram showing still another modification of the resistance element 5 shown in FIG. 1. In Fig. 4A, instead of the resistor 5, both its drain and gate are coupled to the high side power supply node 3, so that an N-channel MOS transistor 5b operating in the resistance mode is used.

FIG. 4B is a diagram showing still another modification of the resistance element 7 shown in FIG. 1. In FIG. 4B, instead of the resistance element 7, a gate and a drain are connected to the gate node 9, and an N-channel MOS transistor 7b operating in the resistance mode is used.

These MOS transistors 5b and 7b operate in a saturation region and function as resistance elements by their on-resistance. By setting the current driving force of these MOS transistors 5b and 7b to the same extent as the driving currents of the resistance elements 5 and 7, respectively, it is possible to realize a current driving element with a limited driving current of the occupied area.

In addition, the MOS transistor 6 and these MOS transistors 5b and 7b can be manufactured by the same manufacturing process, and the number of manufacturing processes can be reduced.

As described above, according to the first embodiment of the present invention, the gate potential of the N-channel MOS drive transistor for driving the output signal at low level is changed by capacitive coupling according to the input signal, and the low level voltage of the input signal is changed. Can be converted to a voltage level lower than that.

(Example 2)

Fig. 5 is a diagram showing the configuration of the level conversion circuit according to the second embodiment of the present invention. In Fig. 5, the level converting circuit includes a P-channel MOS transistor 16 connected between the high side power supply node 13 and the output node 12, a current driving element 15 connected between the output node 12 and the low side power supply node 14, And a current driving element 17 connected between the high side power supply node 13 and the gate node 19 of the MOS transistor 16, and a capacitor 18 connected between the input node 11 and the gate node 19 which receive the input signal IN.

The input signal IN is changed between the voltage VDD and the reference voltage GND as in the first embodiment. The voltage VHG is supplied to the high side power supply node 13, and the voltage VLW is supplied to the low side power supply node 14. This high side power supply voltage VHG is higher than the high level voltage VDD of the input signal IN. The low side power supply voltage VLW may be a reference voltage GND or a voltage lower than that. The low side power supply voltage VLW may be a voltage higher than the reference voltage GND.

The current driving elements 15 and 17 are each composed of a resistance element, a constant current source, or a P-channel MOS transistor operating in a resistance mode.

FIG. 6 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. Hereinafter, with reference to FIG. 6, the operation | movement of the level conversion circuit shown in FIG. 5 is demonstrated.

Now, at time t10, the state where the input signal IN is at the voltage VDD level, the gate node 19 is at the voltage VHG level, and the output signal / OUT from the output node 12 are at the voltage VLW level.

At time t11, when the input signal IN drops from the voltage VDD to the reference voltage GND, the potential change of the input signal IN is transmitted to the gate node 19 through the capacitor 18, and the voltage level of the node 19 is changed from the voltage VHG to the voltage. Decreases to the level of VHG-VDD. The parasitic capacitance at gate node 19 is ignored. If the voltage VDD is at a voltage level sufficiently larger than the absolute value of the threshold voltage of the MOS transistor 16, the gate-source voltage of the MOS transistor 16 is lower than the threshold voltage, and the MOS transistor 16 conducts and the current flows to the output node 12. Is supplied, and the voltage level of the output signal / OUT increases.

The high level of this output signal / OUT is a voltage level lower than the output voltage VHG and the output offset voltage (DELTA) V2. The output offset voltage [Delta] V2 is determined by the on-resistance of the MOS transistor 16 and the amount of current or resistance of the current driving element 15 being driven. After the voltage level of the gate node 19 decreases by VDD due to the decrease of the input signal IN, current is supplied from the high-side power supply node 13 by the current driving element 17, and the voltage level rises. As the voltage level of the gate node 19 rises, the on-resistance of the MOS transistor 16 increases, and the voltage level of the output signal / OUT decreases. The potential change of the gate node 19 and the potential change of the output signal / OUT set the amount of drive current or resistance of the current driving elements 15 and 17 and the on-resistance of the MOS transistor to the extent that the L level period of the input signal IN is almost negligible. do. These conditions are the same as in the case of Example 1.

At time t12, the input signal IN rises from the reference voltage GND to the voltage VDD level. As the voltage of the input signal IN increases, the potential of the gate node 19 rises, and the voltage VDD rises from the voltage VHG-VDD + ΔV1. As the potential rise of the gate node 19 causes the MOS transistor 16 to become non-conductive, the output node 12 is discharged by the current driving element 15, and its voltage level drops to the low side power supply voltage VLW level. Here, before the time t12 falls, the on-resistance of the MOS transistor 16 increases with the potential rise of the gate node 19 due to the current from the current driving element 17, and the output signal / OUT reaches the voltage level of the voltage VHG-ΔV3. It is lowered.

In the case of using the level converting circuit shown in Fig. 5, the high level voltage VDD of the input signal IN can be raised to a voltage level corresponding to the voltage VHG higher than that, so that the high level voltage of the voltage VHG-ΔV3 (> VDD) is obtained. It can generate the output signal / OUT with In particular, if the output signal / OUT is sufficiently changed to the high side and the low side beyond the input logic threshold of the circuit next to the output node 12 of this level conversion circuit, the level conversion circuit shown in FIG. It can be used as a level conversion circuit.

As described above, according to the second embodiment of the present invention, the gate potential of the P-channel MOS transistor which drives the output signal to the high level is changed by capacitive coupling according to the input signal, and is higher than the high level voltage of the input signal. A signal having a high high level voltage can be generated using only the P-channel MOS transistor as the MOS transistor.

(Example 3)

Fig. 7 is a diagram showing the configuration of the level conversion circuit according to the third embodiment of the present invention. In the level conversion circuit shown in FIG. 7, a bootstrap type load circuit 20 is used instead of the resistance element 5 of the level conversion circuit shown in FIG. The bootstrap load circuit 20 includes an N-channel MOS transistor 21 connected between a high side power supply node 3 and an output node 2, a gate and a drain connected to a high side power supply node, and a source of the MOS transistor 21. And an N-channel MOS transistor 22 connected to the gate node 24, and a capacitor 23 connected between the output node 2 and the node 24.

The MOS transistor 22 charges the node 24 at the voltage level of the voltage VH-Vthn at the time of conduction. Here, Vthn represents the threshold voltage of the MOS transistor 22. The other configuration of the level conversion circuit shown in FIG. 7 is the same as that of the level conversion circuit shown in FIG. 1, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

In addition, the timing relationship between the input signal IN and the output signal / OUT of the level conversion circuit shown in FIG. 7 is the same as that shown in FIG.

In the level converting circuit shown in Fig. 7, when the input signal IN is at the high level of the voltage VDD level, the gate node 9 is at the level of the voltage VDD-VL, and the MOS transistor 6 conducts, and the output signal from the output node 2 is present. / OUT becomes the low level of the voltage level corresponding to the voltage -VL level.

At this time, in the bootstrap load circuit 20, the source node of the MOS transistor 21 becomes the output node 2. Even when the potential of the node 24 decreases due to the potential drop of the output node 2, the MOS transistor 22 remains on, and the MOS transistor 22 sets the gate potential of the MOS transistor 21 to the voltage VH-Vthn. Usually, since the voltage VH-Vthn-(-VL) is higher than the threshold voltage of the MOS transistor 21, the MOS transistor 21 is turned on, and the voltage level of the output signal / OUT is the current driving force of the MOS transistors 21 and 6 ( Voltage level determined by the on resistance). By making the current driving force (on resistance) of the MOS transistor 21 sufficiently smaller than the current driving force (or on resistance) of the MOS transistor 6, the output signal / OUT can be set to a voltage level sufficiently close to the voltage -VL.

When the input signal IN drops from the voltage VDD level to the reference voltage GND level, the voltage level of the gate node 9 decreases, and the MOS transistor 6 becomes in a non-conductive state. In this case, therefore, output node 2 is charged by MOS transistor 21, and its voltage level rises. When the voltage level of the output node 2 rises, this voltage rise is transmitted to the node 24 through the capacitor 23. When the voltage level at the node 24 is higher than the voltage VH-Vthn, the MOS transistor 22 is in a non-conductive state, and the node 24 is in a floating state. Therefore, as the output signal / OUT from this output node 2 rises, when the voltage level of the node 24 rises further from the voltage VH-Vthn and becomes higher than the voltage VH + Vthn, the MOS transistor 21 returns to this output node 2. , The voltage VH is supplied, and the voltage level of the output signal / OUT becomes the voltage VH level.

By the bootstrap action of the capacitor 23, the MOS transistor 21 can be brought into a deep on state at a high speed, and the output signal / OUT can be raised at a high speed as compared with a configuration using a resistor or the like.

In addition, when the output signal / OUT falls from the high level to the low level, the MOS transistor 22 is initially in a non-conductive state in the bootstrap type load circuit 20. The voltage level of the node 24 decreases, and at high speed, the voltage level of the node 24 falls to the voltage VH-Vthn level, and the current driving force of the MOS transistor 21 is sufficiently small (or the on-resistance is sufficiently small), At high speed, the output node 2 can be discharged by the MOS transistor 6.

Therefore, by using the bootstrap type load circuit 20 shown in FIG. 7, it is possible to realize a level conversion circuit capable of changing the output signal / OUT at high speed.

In particular, in the level converting circuit shown in FIG. 7, the rising speed of the output signal / OUT can be made faster than the configuration of the level converting circuit shown in FIG.

(Change example)

Fig. 8 is a diagram showing the configuration of a modification of the level conversion circuit according to the third embodiment of the present invention. The level converting circuit shown in FIG. 8 is equivalent to replacing the current drive element 15 of the level converting circuit shown in FIG. 5 with the bootstrap load circuit 30. The other configuration of the level conversion circuit shown in FIG. 8 is the same as that of the level conversion circuit shown in FIG. 5, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

The bootstrap load circuit 30 includes a P-channel MOS transistor 31 coupled between the output node 12 and the low side power supply node 14 and whose gate is connected to the node 34, and whose gate and drain are connected to the low side power supply node 14. A P-channel MOS transistor 32 whose source is connected to the node 34 and a capacitor 33 which is connected between the output node 12 and the node 34.

The MOS transistor 32 maintains the node 34 at the level of the voltage VLW + Vthp at the time of conduction. Here, Vthp represents the absolute value of the threshold voltage of the MOS transistor 32.

FIG. 9 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. The operation of the level conversion circuit shown in FIG. 8 is the same as that shown by the signal waveform in FIG. When the input signal IN decreases from the high level of the voltage VDD level to the low level of the voltage GND level, the voltage level of the node 19 decreases, the MOS transistor 16 conducts, and the output signal / OUT from the output node 12 becomes high. It becomes a level. When the output signal / OUT rises, even when the potential of the node 34 rises due to the capacitive coupling of the capacitor 33, the MOS transistor 32 is turned on, and the potentials of the nodes 3 and 4 are brought to the voltage level of the voltage VLW + Vthp. maintain. In accordance with the potential rise of the output node 12, the source of the MOS transistor 31 is the output node 12. Usually, since the voltage VH- (Vthp + VLW) is larger than the absolute value Vthp of the threshold voltage, the MOS transistor 31 is kept in the on state. The output signal / OUT becomes a voltage level determined by the current driving force (or on resistance) of the MOS transistors 16 and 31. By making the current driving force of the MOS transistor 31 sufficiently smaller than the current driving force of the MOS transistor 16, the output signal / OUT can be raised to the level of the voltage VH.

When the input signal IN rises from the reference voltage GND to the voltage VDD, the voltage level of the gate node 19 rises, and the MOS transistor 16 transitions to a non-conductive state. At this time, the output node 12 is discharged by the MOS transistor 31, and the voltage level thereof decreases. The voltage level drop of the output node 12 is transmitted to the node 34 by the capacitor 33. When the voltage level at this node 34 is lower than the voltage VLW + Vthp, the MOS transistor 32 is in a non-conductive state. Therefore, the node 34 is in a floating state, and due to the capacitive coupling of the capacitor 33, the voltage level of the node 34 is further lowered in accordance with the potential drop of the output node 12, and the MOS transistor 31 is in a deep on state. Therefore, when the MOS transistor 31 discharges the output node 12 with a large current driving force, and the potential of the node 34 falls below the voltage VLW-Vthp, the output signal / OUT is lowered to the low level voltage VLW (-VL) level.

The voltage change amount of the node 34 is set by the capacity division between the capacitance value of the capacitor 33 and the parasitic capacitance of the node 34. Therefore, by setting the capacitance value of the capacitor 33 sufficiently large, the voltage level of the node 34 is sufficiently changed in accordance with the output signal / OUT to switch the MOS transistor 31 between the deep on state and the shallow on state. The output signal / OUT from output node 12 can be changed.

That is, the level converting circuit shown in FIG. 8 has a high level voltage level converting function, and the output signal / OUT can be lowered more rapidly than in the case of using the current drive element shown in FIG. have.

As described above, according to the third embodiment of the present invention, a bootstrap type load circuit is used as a load element of the output node, so that the level-converted signal can be output at high speed.

(Example 4)

Fig. 10 is a diagram showing the configuration of the level conversion circuit according to the fourth embodiment of the present invention. In the configuration of the level conversion circuit shown in FIG. 10, an output auxiliary circuit 40 for generating a signal / OUT after level conversion to the final output node 50 is further provided in accordance with the signal generated in the output node 2. The part of the circuit which generates a signal to the output node 2 according to the input signal IN supplied to the input node 1 is the same as that of the level conversion circuit shown in FIG. 1, and the same reference numerals are attached to the corresponding parts. The detailed description is omitted.

The output auxiliary circuit 40 includes an N-channel MOS transistor 41 connected between the high side power supply node 3 and the final output node 50 and whose gate is connected to the node 45, and the gate and the drain are connected to the high side power supply node 3. An N-channel MOS transistor 42 connected to the source and connected to the node 45, an N-channel MOS transistor 43 connected between the high side power supply node 3 and the output node 2 and whose gate is connected to the node 45, and an output node 2 And an N-channel MOS transistor 46 connected between the last output node 50 and the low side power supply node 4, and whose gate is connected to the gate node 9, and the capacitor 44 connected between the node 45 and the node 45.

The configuration of the input stage for receiving the input signal IN of the level converting circuit shown in FIG. 10 and discharging output node 2 is the same as that of the level converting circuit shown in FIG. 1, and the same reference numerals are attached to corresponding parts. The detailed description is omitted.

FIG. 11 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. Hereinafter, with reference to FIG. 11, the operation | movement of the level conversion circuit shown in FIG. 10 is demonstrated.

The input signal IN supplied to the input node 1 is changed between the voltage VDD and the reference voltage GND. In response to this input signal IN, the gate node 9 changes its voltage level between the voltage -VL and the voltage VDD-VL. Here, the voltage change ΔV due to the discharge in the resistive element 7 is sufficiently small. In addition, the parasitic capacitance of the gate node 9 is sufficiently small compared to the capacitance value of the capacitor 8, and is negligible.

When the output node 2 is at the low level of the voltage -VL level, the node 45 is maintained at the level of the voltage VH-Vthn by the MOS transistor 42.

When the input signal IN rises from the reference voltage GND to the voltage VDD, the voltage level of the gate node 9 increases, the on-resistance of the MOS transistor 6 decreases, and the voltage level of the output node 2 decreases. In this state, the voltage level at the node 45 is maintained at the level of the voltage VH-Vthn by the MOS transistor 42. Therefore, the MOS transistor 41 is kept on, and the voltage level of the output node 2 is maintained at the voltage level determined by the current driving force (or on resistance) of the MOS transistors 43 and 6.

At this time, the MOS transistor 46 is also turned on so that the voltage level of the output signal / OUT from the final output node 50 is reduced. The low-level voltage of this output signal / OUT is determined by the current driving force (or on-resistance) of the MOS transistors 41 and 46 because the MOS transistor 41 is also in the on state. By making the current driving force of the MOS transistor 41 sufficiently smaller than the current driving force of the MOS transistor 46, or by making the on-resistance of the MOS transistor 41 sufficiently higher than the on-resistance of the MOS transistor 46, the low level voltage of the output signal / OUT can be made almost. Can be set to voltage -VL level.

When the input signal IN decreases from the voltage VDD to the reference voltage GND, the voltage level of the gate node 9 decreases, and the voltage between the gate and the source node of the MOS transistor 6 becomes equal to or less than the threshold voltage and is in a non-conductive state. Becomes Thus, output node 2 is charged by MOS transistor 43 and its voltage level rises. The voltage rise of this output node 2 is transmitted to the node 45 by the capacitor 44, the MOS transistor 42 is in a non-conductive state, and the voltage level of the node 45 further rises from the precharge voltage level. Therefore, the on-resistance of the MOS transistor 43 becomes small (current driving force becomes large), the voltage level of the output node 2 rises at high speed, and the voltage rise of the output node 2 is fed back to the node 45. As a result, the output node 2 is charged to the voltage VH level by the MOS transistor 43. The voltage level of this node 45 rises by VH + VL-ΔV from the precharge voltage VH-Vthn. As a result of the voltage rise at the node 45, the MOS transistor 41 is also brought into the same deep on state, and the output node 50 is charged at a high speed to raise the output signal / OUT to the voltage VH level. At this time, similar to the MOS transistor 6, the MOS transistor 46 has a gate-source voltage of less than or equal to the threshold voltage and is in a non-conductive state.

Here, the conduction state and the non-conduction state represent a state of interrupting current / driving current.

Even if the level conversion circuit shown in Fig. 10 is used, a signal that is changed between the voltage VDD and the reference voltage GND can be converted into a signal that is changed between the voltage VH and the voltage -VL (+ ΔV). In particular, since the output node 50 is charged using the MOS transistor 41, even when a capacitive load is connected to the output node 50, the voltage level of the node 45 is increased at high speed without being affected by the capacitive load. The voltage VH + VL-ΔV can be raised, and the output signal / OUT can be raised from the low level voltage to the high level voltage at a higher speed than the circuit shown in FIG. In addition, even when the output signal / OUT falls, the potential of the node 45 can be restored from the high voltage level to the level of the precharge voltage VH-Vthn without being affected by the capacitive load, thereby reducing the current driving force of the MOS transistor 41. At high speed, the output signal / OUT can be lowered from the high level to the low level.

(Change example)

Fig. 12 is a diagram showing a modification of the level conversion circuit according to the fourth embodiment of the present invention. In the level conversion circuit shown in FIG. 12, in the level conversion circuit shown in FIG. 8, the push pull stage 60 for driving the final output node 62 is provided in accordance with the voltage of the gate node 19 and the voltage of the node 34. As shown in FIG. The other configuration of the level conversion circuit shown in FIG. 12 is the same as that of the level conversion circuit shown in FIG. 8, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

The push-pull stage 60 is connected between the high-side power supply node 13 and the final output node 62, and between the final output node 62 and the low-side power supply node 14, and the P-channel MOS transistor 65 whose gate is connected to the node 19. And a P-channel MOS transistor 66 that is connected and whose gate is connected to a node 34.

In the configuration of the level conversion circuit shown in FIG. 12, the capacitor 33 of the bootstrap type load circuit 30 is separated from the final output node 62. As shown in FIG. Therefore, the bootstrap effect of the capacitor 33 can be sufficiently large without being affected by the capacitive load of the final output node 62, so that the output signal / OUT can be generated at high speed. The operation waveform of the level conversion circuit shown in FIG. 12 is the same as the operation waveform shown in FIG. The output signal / OUT can be rapidly lowered from the voltage VHG to the voltage VLW (= -VL) (ignoring factors such as parasitic capacitance).

As described above, according to the fourth embodiment of the present invention, the bootstrap type load circuit is insulated from the final output node, and the final output node is driven by the push-pull stage, so that the output signal can be changed at high speed.

(Example 5)

Fig. 13 is a diagram showing the configuration of the level conversion circuit according to the fifth embodiment of the present invention. In Fig. 13, the level converting circuit includes an input terminal 100 for converting an input signal IN supplied to the input node 1 into a signal which is changed between voltages VH and -VL and outputting it to the node A, and the input terminal 100. The push-pull stage 110 for driving the node B according to the complementary signal from the bootstrap, the bootstrap type driving stage 120 for driving the node C according to the output signal of the push-pull stage 110, and the output signal of the input terminal 100. And a final driving stage 130 for driving the output node 150 according to the output signal of the push-pull stage 110 and the output signal of the bootstrap type driving stage 120 and the final output signal OUT.

The input terminal 100 has the same configuration as that of the level converting circuit shown in FIG. 7, and has a capacitor 8 for transmitting the input signal IN to the gate node 9, and a resistor 7 connected between the gate node 9 and the low side power supply line 104. And an N-channel MOS transistor 6 for selectively conducting in accordance with the voltage level of the gate node 9 and driving the node A at a voltage level corresponding to the voltage -VL level on the low-side power supply line 104 and the high-side power supply line. N-channel MOS transistor Q1 connected between 102 and node A, N-channel MOS transistor Q2 which transfers voltage VH-Vthn to the gate of MOS transistor Q1 when conducting, and between gate of node MOS transistor Q1 and node A. And a capacitor CP1 connected thereto.

The operation of the input terminal 100 is the same as that of the level conversion circuit shown in Fig. 7, and the input signal IN which is changed between the voltages VDD and GND is changed between the voltages corresponding to the voltages VH and the voltage -VL. The signal is converted to a signal and output to node A.

At this time, in the following description, the circuits are ignored, ignoring the influence of the parasitic capacitance of the internal node, the discharge by the resistance element 7, and the current level (or on-resistance) of the MOS transistor on the voltage level of the output signal and the internal signal. Is operated like a receiver circuit, and the output signal of each stage is said to change between the voltages VH and -VL. It is also assumed that Q15 from MOS transistors 6 and Q1 have a threshold voltage Vthn.

The push-pull stage 110 supplies an N-channel MOS transistor Q3 for supplying current from the high-side power supply line 102 to the node B according to the signal of the node A, and a current from the node B to the low-side power supply line 104 according to the signal of the gate node 9. N-channel MOS transistor Q4 to be supplied is included.

In this push-pull stage 110, when the input signal IN rises from the low level to the high level, the MOS transistor Q4 is turned on and the voltage level of the node B is lowered. At this time, when the voltage level of the output node A of the input terminal 100 decreases and the voltage difference between the nodes A and B becomes less than Vthn, the MOS transistor Q3 is in a non-conductive state, and the node B falls to the low side power supply voltage -VL. . On the other hand, when the voltage level of the input signal IN decreases, the voltage level of the gate node 9 decreases, and the MOS transistor Q4 is brought into a non-conducting state. The node A rises to the voltage VH level by the MOS transistor Q1, and therefore the node B is charged to the voltage VH-Vthn level by this MOS transistor Q3.

In this push-pull stage 110, after the gate potential of the MOS transistor Q4 is changed, the gate potential of the MOS transistor Q3 is changed. Therefore, at the time of charging the node B, the MOS transistor Q3 conducts after the MOS transistor Q4 is brought into a non-conducting state, so that a through current hardly occurs. On the other hand, when the node B is discharged, the MOS transistor Q3 transitions to a non-conductive state after the MOS transistor Q4 is brought into a conductive state. The gate potential of this MOS transistor Q3 is -VL + ΔV in consideration of the offset voltage. Therefore, when the voltage ΔV (output offset voltage at the input terminal 100) is sufficiently smaller than the threshold voltage Vthn of the MOS transistor Q3, the MOS transistor Q3 can be surely set to the off state. Therefore, in this push-pull stage 110, the through current only flows at the time of discharge of the node B, and only the current (direct current) is consumed in a period where the switching period is very short.

The bootstrap type drive stage 120 includes an N-channel MOS transistor Q7 for driving node C to a low side power supply voltage -VL level according to a signal on the output node B of the push-pull stage 110, a high side power supply line 102 and a node. N-channel MOS transistor Q5 connected between C, the capacitor CP2 connected between the gate of MOS transistor Q5 and node C, and the N-channel MOS which charges the gate of MOS transistor Q5 with voltage VH-Vthn at the time of conduction. Contains transistor Q6.

The operation of the bootstrap type drive stage 120 is substantially the same as that of the input stage 100. When the voltage level of the output node B of the push-pull stage 110 rises, the MOS transistor Q7 is turned on, and the node C is at the low side power supply voltage -VL level (a voltage level determined by the on-resistance or current driving force of the MOS transistors Q5 and Q7). Driven by). When the voltage level of the output node B of the push-pull stage 110 decreases, the MOS transistor Q7 becomes non-conductive. In this case, the node C is charged by the MOS transistor Q5, so that the gate potential is further increased by the bootstrap action of the capacitor CP2, and the node C is driven to the voltage VH level. Therefore, the node C is changed between the voltage VH and the voltage -VL.

The receiver-type bootstrap output drive stage 130 includes an N-channel MOS transistor Q8 that charges node D with current from the high-side power supply line 102 according to the signal of the output node A of the input terminal 100 and the final output node 150. The N-channel MOS transistor Q12 discharges current from the node D to the low-side power supply line 104 in accordance with the output signal OUT, and the node D is energized when the voltage level is high. An N-channel MOS transistor Q13 discharged at a level, a capacitor CP3 connected between the node E and a node F, an N-channel MOS transistor Q14 that discharges the node F in response to a signal on the output node B of the push-pull stage 110, and a boot The N-channel MOS transistor Q10 which charges the node F from the high side power supply line 102 in accordance with the signal from the output node C of the strap type driving stage 120 is connected between the high side power supply line 102 and the node E. N-channel MOS transistor Q9 connected to node F, N-channel MOS transistor Q11 for supplying current from high-side power supply line 102 to output node 150 in accordance with the signal voltage of node F, and output node B of push-pull stage 110. And an N-channel MOS transistor Q15 that selectively conducts and, upon conduction, drives the final output node 150 to a voltage -VL level in accordance with the signal at < RTI ID = 0.0 >

In the legacy output bootstrap type final output drive stage 130, the path of current flows from the high-side power line 102 to the low-side power line 104 by using a delay of signal change as described in detail below. And the current consumption is reduced. In addition, the output signal OUT, which is changed between the voltages VH and -VL, is generated precisely by the receiver type bootstrap type output drive stage 130.

FIG. 14 is a signal waveform diagram showing the operation of the level conversion circuit shown in FIG. The operation of the level converting circuit shown in FIG. 13 will be described below with reference to FIG. 14.

When the input signal IN supplied to the input node 1 rises from the reference voltage GND to the high level voltage VDD, the MOS transistor 6 is turned on at the input terminal 100, and the node A is almost low-side power from the high-side power supply voltage VH. The voltage drops to a voltage level close to -VL. Here, it is assumed that the current driving force or the on resistance of the MOS transistors Q1 and 6 is adjusted, and the output offset voltage of the input terminal 100 can be almost ignored.

In the push-pull stage 110, as the voltage level of the gate node 9 of the input terminal 100 rises, the MOS transistor Q4 conducts, discharges the node B, and lowers the voltage level. Subsequently, when the voltage level of the output node A of the input terminal 100 drops to the low side power supply voltage -VL level, the gate-source voltage of the MOS transistor Q3 becomes less than the threshold voltage, and becomes non-conductive state. Therefore, the node B is discharged to the low side power supply voltage -VL level by the MOS transistor Q4.

In the bootstrap type drive stage 120, as the voltage level of the node B decreases, the MOS transistor Q7 transitions into a non-conductive state, the node C is charged by the MOS transistor Q5, and the bootstrap action of the capacitor CP2 is applied. The node C is charged to the high side power supply voltage VH level. At this time, since the node B is discharged to the low side power supply voltage -VL level, the MOS transistor Q7 is maintained in a non-conductive state.

The following operation is performed in the recipe output bootstrap type 130. First, the output signal OUT is at a low level of the low side power supply voltage -VL level, and the MOS transistor Q12 is in a non-conductive state. In addition, the voltage level of the output node A of the input terminal 100 is the low side power supply voltage -VL level, and the MOS transistor Q8 is also in a non-conductive state. In the first cycle, the node D is at the voltage VH-Vthn level in accordance with the low-level input signal IN. On the other hand, in accordance with the signal of the output node B of the push-pull stage 110, the MOS transistors Q14 and Q15 are first set to the non-conductive state.

Subsequently, when the voltage level of the output node C of the bootstrap type drive stage 120 rises, the MOS transistor Q10 conducts and the node F is charged. During the charging operation of the node F by this MOS transistor Q10, the MOS transistor Q14 is already in a non-conduction state in accordance with the potential of the node B, and the low-side power supply from the high-side power supply line 102 through the paths of the MOS transistors Q10 and Q14. The flow of current through line 104 is prevented.

When the voltage level of the node F rises, the MOS transistor Q11 is turned on to charge the output node 150 to raise the voltage level of the output signal OUT. Also in the charging operation of the output node 150, after the MOS transistor Q15 is brought into a non-conducting state according to the signal on the output node B of the push-pull stage 110, the MOS transistor Q11 conducts, and therefore, from the high-side power supply line 102 There is no path through which current flows to the right power line 104. When the node D is maintained at the voltage VH-Vthn level, the node E is at the low side power supply voltage -VL level, and the node F is charged, and the voltage level is changed from the low side power supply voltage -VL to the voltage VH-Vthn. Can be raised to level.

When the voltage level of the output signal OUT rises and the gate-source voltage of the MOS transistor Q12 becomes higher than the threshold voltage, the node D is discharged by the MOS transistor Q12, and the voltage level thereof decreases, so that the MOS transistor Q13 Transfer to a nonconducting state.

When the MOS transistor Q13 is turned off, the MOS transistor Q9 raises the voltage level of the node E in accordance with the voltage level of the node F. When the voltage level of the node E rises when the voltage of the node E rises, the MOS transistor Q10 becomes non-conductive, so that the node F is in a floating state, and the voltage of the node E is caused by the capacitive coupling of the capacitor CP3. As the level increases, the voltage level of the node F rises to the voltage VH + ΔVB. Therefore, the node E is charged to the voltage VH level by the MOS transistor Q9. As the voltage level of the node F increases, the gate potential of the MOS transistor Q11 increases, so that the output signal OUT from the output node 150 is driven at a high speed to the voltage VH level.

Therefore, when raising the voltage level of the output signal OUT, current flows in the paths of the MOS transistors Q9 and Q13. However, by sufficiently reducing the current driving force of these MOS transistors Q9 and Q13, the current consumption can be reduced. The period in which the direct current (the current flowing from the high side power supply line 102 to the low side power supply line 104) flows in the MOS transistors Q9 and Q13 is a transition time of the output signal OUT and can be shortened sufficiently. By sufficiently increasing the current driving force of the MOS transistor Q11, even when the load of the output node 150 is large, the output signal OUT can be driven to the voltage VH level at high speed.

When the input signal IN falls from the high level voltage VDD to the low level voltage (reference voltage) GND, at the input terminal 100, first, the voltage level of the node 9 becomes a voltage level close to the voltage -VL. The voltage level of the node A rises, and the voltage level of the node A becomes the high side power supply voltage VH.

As the voltage level of the node A rises, in the push-pull stage 110, the MOS transistor Q3 conducts, and the node B is driven to the voltage level of the voltage level VH-Vthn. At this time, since the MOS transistor Q4 is already in the non-conducting state due to the voltage level of the node 9, there is no path through which the current flows from the high side power supply line 102 to the low side power supply line 104 when the node B is being charged.

When the voltage level of the output node B of the push-pull stage 110 rises, the node C is discharged by the MOS transistor Q7 in the bootstrap type drive stage 120, and the voltage level thereof decreases.

In the final output terminal 130, as the voltage level of the output node B of the push-pull stage 110 rises, the MOS transistors Q14 and Q15 become conductive, and the node F is lowered to the voltage -VL level, and the output signal OUT Lower the voltage level. Therefore, the MOS transistors Q9 and Q11 are in a non-conductive state, and the output signal OUT from the output node 150 is driven to the low side power supply voltage -VL level by the MOS transistor Q15.

As the voltage level of the output node A of the input terminal 100 rises, the MOS transistor Q8 conducts, and the node D is charged, and the voltage level thereof is charged to the voltage VH-Vth level. Thus, the MOS transistor Q13 conducts, so that the node E is energized. Drive to the VL level. At the time of conduction of the MOS transistor Q13, the MOS transistor Q9 is already in a non-conductive state due to the potential drop of the node F in response to the potential change of the node B, and the voltage level of the node E is decreased, and the MOS transistors Q9 and Q13 are turned off. There is no current path through it.

When the voltage level of the output signal OUT decreases, the MOS transistor Q12 is brought into a non-conductive state. In this case, in the paths of the MOS transistors Q8 and Q12, the right power source from the high-side power supply line 102 through the MOS transistors Q8 and Q12 until the voltage level of the output signal OUT decreases and the MOS transistor Q12 is in a non-conductive state. Current flows through line 104. However, since the output signal OUT is driven at a low side power supply voltage -VL level at high speed, the amount of current flowing through these MOS transistors Q8 and Q12 can be made sufficiently small.

In the steady state, since there is no path in which the DC current flows from the high side power line 102 to the low side power line 104 in the final output terminal 130, the driving capability of the MOS transistors Q11 and Q15 can be increased. Even when the output load capacity of the output node 150 is large, the output signal OUT can be changed by driving the final output node at high speed.

The input stage 100 and the bootstrap type driving stage 120 are receiver circuits, and current flows in the MOS transistors Q1 and Q6 and the MOS transistors Q5 and Q7. However, in the input stage 100 and the bootstrap type driving stage 120, since the voltage levels of the nodes A and C are complementarily changed, the input stage 100 and the bootstrap driving are driven in accordance with the logic level of the input signal IN. When only one of the stages 120 outputs a low level signal, current flows, and the power consumption can be set to the same level as that of the level conversion circuit in which only one bootstrap type load circuit is provided.

Also, in the configuration of the level conversion circuit shown in Fig. 13, a P-channel MOS transistor is used instead of the N-channel MOS transistor, and the voltage polarity is reversed (the voltage -VL is supplied to the power supply line 102, and the power supply line 104 is supplied to the power supply line 104). Voltage VH is supplied), and the same level conversion circuit can be realized.

As described above, according to the fifth embodiment of the present invention, the final output node is driven in accordance with the output signal of the first stage level conversion stage by using the ratioless circuit, and the level of the low current consumption which can change the output signal at high speed. The conversion circuit can be realized.

(Example 6)

Fig. 15 is a diagram showing the configuration of main parts of the level conversion circuit according to the sixth embodiment of the present invention. In Fig. 15, the configuration of the input first stage conversion stage for driving the output node 2 in accordance with the input signal IN is shown. 15 may be used in combination with any one of the first to fifth embodiments. In the input ultra-short conversion stage shown in FIG. 15, an N-channel MOS transistor 200 selectively conducting in accordance with the signal on the output node 2 is provided between the node 9 and the low side power supply node 4. As shown in FIG. That is, taking the level conversion circuit shown in FIG. 1 as an example, the MOS transistor 200 is used in place of the resistance element 7. FIG.

FIG. 16 is a signal waveform diagram showing the operation of the input conversion stage shown in FIG. Hereinafter, with reference to FIG. 16, operation | movement of the input ultra-short conversion stage shown in this FIG. 15 is demonstrated. When the input signal IN is the reference voltage GND level, the voltage level of the output node 2 is the voltage VH level, and the node 9 is maintained at the low side power supply voltage -VL level by the MOS transistor 20O.

When the input signal IN rises from the low level GND to the high level VDD, the voltage level of the node 9 rises, so that the MOS transistor 6 conducts and the voltage level of the node 2 falls. The voltage level of the output node 2 is a circuit circuit for driving the output node 2 of the level converting stage, and is a voltage level higher than the low side power supply voltage -VL. However, by sufficiently reducing the output offset voltage, the MOS transistor 200 can be set to a non-conductive state. In this case, the node 9 has only a leakage current flowing through the MOS transistor 200, and there is no problem of a drop in the voltage level of the node 9 as in the case of using a resistance element, thus eliminating the restriction on the high level period of the input signal IN. The flexibility of the circuit is improved.

In addition, since the gate potential of the MOS transistor 6 can be kept constant, and therefore the voltage level of the output node 2 is kept constant, the problem that the low level voltage of the output node 2 rises can be solved, and the output node 2 It is possible to improve the operating margin for the low side voltage of the circuit receiving the voltage of.

 (Change example)

17 is a diagram showing a modification of the sixth embodiment of the present invention. In Fig. 17, the P channel 16 is used to perform level conversion of the high level voltage level of the input signal IN. In this input superstage conversion stage, a P-channel MOS transistor 202 selectively conducting in response to the voltage on the output node 12 is connected between the high side power supply node 3 and the gate node 19 of the MOS transistor 16. That is, the P-channel MOS transistor 202 which responds to the signal of the output node 12 is used instead of the current drive element 17 of the level converting circuit shown in FIG.

In the case of the configuration of the input conversion stage shown in FIG. 17, when the input signal IN becomes low and the voltage level of the node 19 decreases by the capacitor 18, the node 12 is charged by the MOS transistor 16, and high. The voltage level close to the side power supply voltage VH is reached. In this case, therefore, the MOS transistor 202 can be kept in a non-conductive state by setting the offset voltage of the output node 12 to a voltage level that keeps the MOS transistor 202 in a non-conductive state. Therefore, when the input signal IN is at the low level, the voltage level of the node 19 can be prevented from rising by the charging current, and the restriction on the low level period of the input signal IN can be removed.

When the input signal IN is raised to the high level, the node 19 is driven by the capacitor 18 to the voltage level of the high side power supply voltage VH, and the MOS transistor 16 is in a non-conducting state, and the low level voltage of the output node 12 is reduced. It doesn't hurt anything at all. At this time, the node 19 is maintained at the high side power supply voltage VH level by the MOS transistor 202.

As described above, according to the sixth embodiment of the present invention, a gate node of an output drive MOS transistor that receives an input signal through a capacitive element as a gate, and a MOS that receives a voltage of a drive node of the output drive MOS transistor into its gate The transistors are connected, and the potential of the gate node of the output drive MOS transistor can be suppressed from being changed, so that the restrictions on the high level period and the low level period of the input signal can be removed.

(Example 7)

Fig. 18 is a diagram showing the configuration of main parts of the level conversion circuit according to the seventh embodiment of the present invention. In the level converting circuit shown in Fig. 18, in the configuration of the level converting circuit shown in Fig. 15, a high resistance resistor element 210 is provided between the gate node 9 and the low side power supply node 4. Connect. The other structure of the circuit shown in FIG. 18 is the same as the structure shown in FIG. 15, and attaches | subjects the same reference numeral to the corresponding part, and the detailed description is abbreviate | omitted.

The resistance value RI of the resistance element 210 is made large enough. By using the resistor element 210, the initial potential of the gate node 9 is set to the low side power supply voltage -VL. By sufficiently increasing the resistance value RI of the resistance element 210 and lowering the drive current amount to less than or equal to the leakage current of the MOS transistor 200, the potential level of the gate node 9 in the steady state can be suppressed unnecessarily, and the gate can be precisely corrected. By initially setting the potential of the node 9, a signal may be generated at the output node 2 according to the input signal IN.

At this time, although not shown in the drawing, also in the configuration shown in FIG. 17, according to the seventh embodiment of the present invention, by connecting a high resistance resistor in parallel with the MOS transistor 202, the voltage level of the gate node 19 is changed to the high side power supply voltage. Initially set to VH.

As described above, according to the seventh embodiment of the present invention, the resistance of the high resistance in parallel with the MOS transistor receiving the output node potential through the gate to the gate of the output drive MOS transistor receiving the input signal to the gate through the capacitor The element (current limiting element) is connected, and the gate potential of the output drive MOS transistor can be surely set to the predetermined voltage level.

(Example 8)

Fig. 19 is a diagram showing the configuration of main parts of the level conversion circuit according to the eighth embodiment of the present invention. In the level conversion circuit shown in Fig. 19, instead of the high resistance resistor element 210 shown in Fig. 18, the gate is turned on in accordance with the output signal (power on reset signal) POR of the power on reset (POR) circuit 230. An N-channel MOS transistor 220 is provided which couples the node 9 to the low side power node 4. The other structure of the level conversion circuit shown in FIG. 19 is the same as that of the level conversion circuit shown in FIG. 18, and the same reference numerals are attached to corresponding parts, and detailed description thereof is omitted.

The power-on reset circuit 230 operates the high-side power supply voltage VH and the low-side power supply voltage -VL as both operating power supply voltages, and when the voltages VH and -VL are supplied, the power-on reset signal POR is set to H level for a predetermined period. Drive at (voltage VH level). The power-on reset signal POR is maintained at the low side power supply voltage VL level in the steady state.

That is, as shown in FIG. 20, both the voltage VH and -VL are the reference voltage GND level before power supply. When the power is turned on, the voltage level of the high side power supply voltage VH rises to reach the predetermined voltage level VH, and the low side power supply voltage -VL also reaches the predetermined voltage level (-VL). In response to this power-on, when the voltages VH and -VL reach a predetermined voltage level or change stably, the power-on reset signal POR from the power-on reset circuit 230 rises to the voltage VH level, and thus MOS Transistor 220 conducts. Thus, the gate node 9 is connected to the low side power supply node 4, and the gate node 9 is initially set to the voltage level.

When the predetermined period has elapsed, the power-on reset signal POR from this power-on reset circuit 230 is at the voltage -VL level, and the MOS transistor 220 is in a non-conductive state. In the normal operation, the MOS transistor 220 is kept in a non-conductive state, so that the MOS transistor 220 does not adversely affect the level conversion operation of the input signal IN at all.

FIG. 21 is a diagram schematically showing an example of the configuration of the power-on reset circuit 230 shown in FIG. 19. In Fig. 21, the power-on reset circuit 230 receives the voltages VDD and GND as the operating voltage, receives the VH input detection circuit 240 for detecting the input of the high side power supply voltage VH, and the voltages VDD and GND as the operating power supply voltage. And receive and operate the VL input detection circuit 242 that detects the input of the low side power supply voltage -VL, and the voltages VDD and GND as the two-operation power supply voltages. A received NAND circuit 244, a level converting circuit 246 for converting the level of the output signal of the NAND circuit 244, and a one shot pulse generating circuit 248 for generating a one-shot pulse signal in response to the rising of the output signal MPOR of the level converting circuit 246. Include.

The VH input detection circuit 240 includes, for example, a capacitor and a resistor connected in series between the high-side power supply node and the ground node, and the high-side power supply is caused by a voltage change caused by the capacitive coupling of the capacitor. It is detected whether or not the voltage VH is input by using an inverter or the like, and during this input, the voltage input detection signal PUPH is driven to the H level.

The VL input detection circuit 242 includes, for example, a resistor and a capacitor connected in series between a power supply node receiving a voltage VDD and a low side power supply node receiving a low side power supply voltage -VL. Capacitive coupling detects the input of the low side power supply voltage -VL. The VL input detection circuit 242 drives the output signal PUPL to H level when the voltage -VL is applied.

The NAND gate 244 drives the output signal to the voltage GND level when both of the voltage input detection signals PUPH and PUPL are at the H level (voltage VDD level). When at least one of the voltage input detection signals PUPH and PUPL is at the low level, the NAND circuit 244 outputs a signal having a voltage VDD level.

The level conversion circuit 246 has the configuration shown in FIG. 1, for example, and converts the output signal of the NAND circuit 244 into a signal that is changed between the voltages VH and -VL.

The one-shot pulse generation circuit 248 operates the voltages VH and -VL as operating power supply voltages, generates a one-shot pulse signal in response to the rise of the signal MPOR from the level conversion circuit 246, and generates a power-on reset signal POR. .

FIG. 22 is a signal waveform diagram showing the operation of the power-on reset circuit 230 shown in FIG. 21. The operation of the power-on reset circuit 230 shown in FIG. 21 will be described below with reference to FIG. 22.

In this power-on reset circuit 230, it is assumed that voltages VDD and GND are stable before voltages VH and -VL.

When the voltage VH is input and the voltage level rises, the VH input detection circuit 240 detects this voltage rise by the capacitive coupling of the internal capacitor and raises the voltage input detection signal PUPH to the high level. Similarly, when the voltage -VL is input and the voltage level is lowered, the VL input detection circuit 242 detects this voltage level drop by capacitive coupling of the capacitor element therein, and sets the voltage input detection signal PUPL to the high level. Drive. When both of these detection signals PUPH and PUPL are at the high level of the voltage VDD level, the output signal of the NAND circuit 244 is at the low level of the voltage GND level.

The level conversion circuit 246 has the configuration shown in FIG. 1, for example, and inverts the logic level of the output signal of the NAND circuit 244 and converts the signal amplitude. Therefore, in response to the output signal of the NAND circuit 244 falling, the signal MPOR from the level conversion circuit 246 rises to the voltage VH level. In response to the rising of the signal MPOR, the one-shot pulse generating circuit 248 drives the output signal POR at the predetermined period voltage VH level, and drives the signal POR to the voltage -VL level after the predetermined time elapses.

Therefore, with the configuration of the power-on reset circuit 230 shown in Fig. 21, the power-on reset signal POR can be generated in the form of one shot pulse after the voltages VH and -VL both reach the predetermined voltage level.

At this time, according to the configuration of the power-on reset circuit 230 shown in FIG. 21, after the detection circuits 240 and 242 detect the input of the voltages VH and -VL, the power-on reset signal POR is added to the input sequence of these voltages. It can be generated regardless.

At this time, also in the eighth embodiment of the present invention, in the configuration shown in Fig. 19, the N-channel MOS transistors are all set to P-channel MOS transistors, and the high-side power supply voltage VH is supplied to the power supply node 4, thereby providing the amplitude of the high-side signal. Conversion can be performed. In that case, the inverted signal of the output signal POR of the one-shot pulse generating circuit 248 shown in FIG. 21 is supplied to the gate of the P-channel MOS transistor for initial setting as a power-on reset signal.

As described above, according to the eighth embodiment of the present invention, the internal node of the level conversion circuit is initially set in accordance with the power-on reset signal, and the internal node is correctly set to the predetermined voltage level, and in the normal operation mode, By setting this internal node in a floating state and capacitive coupling of the capacitor, the voltage level can be set exactly.

In this case, in Examples 1 to 8 described above, the MOS transistor may be a field effect transistor, a MOS transistor formed on a semiconductor substrate, or a thin film transistor (TFT) formed on an insulating substrate such as glass.

As described above, according to the present invention, one type of MOS transistor is used to constitute a level conversion circuit, and the gate of the output drive transistor is driven in accordance with an input signal through a capacitor. Therefore, the voltage of the source node of the output drive transistor can be output as the output signal irrespective of the voltage level of the corresponding logic level of the input signal. As a result, a low power consumption level conversion circuit can be realized.

Although the present invention has been described in detail, it is to be understood that this is for purposes of illustration and not limitation, and the spirit and scope of the invention is limited only by the appended claims.

Claims (3)

An input signal having a first power supply and a second power supply and having an amplitude smaller than the difference between the voltages of the first and second power supplies is a signal that is changed between voltage levels corresponding to the voltages of the first and second power supplies. In the level conversion circuit to be converted, A first insulated gate field effect transistor coupled between an output node and the first power supply; A first capacitor coupled between the node receiving the input signal and the gate of the first insulated gate field effect transistor; A first current driving device coupled between the gate of the first insulated gate field effect transistor and the first power source; And a second current driving device coupled between the second power supply and the output node and separated from the gate of the first insulated gate field effect transistor. The method of claim 1, The first current driving element is coupled between the first power supply and the gate of the first insulated gate field effect transistor, and is the same conductivity type as the first insulated gate field effect transistor and is gated to the output node. And a second insulated gate field effect transistor coupled thereto. The method of claim 1, The second current driving device, A second insulated gate field effect transistor of the same conductivity type as the first insulated gate field effect transistor coupled between the second power supply and the output node; A third insulated gate of the same conductivity type as the first insulated gate field effect transistor coupled between the second power supply and the gate of the second insulated gate field effect transistor and diode-connected in a forward direction from the second power supply Type field effect transistor, And a second capacitor connected between the output node and the gate of the second insulated gate field effect transistor, wherein a signal after level conversion is generated in the output node.

Images