KR100732634B1 - Nor flash memory controlling data hold time according to clock frequency - Google Patents

Abstract

A NOR flash memory controlling data hold time according to a clock frequency is provided to satisfy parameter characteristics related with data output regardless of the clock frequency, by controlling the delay time of a clock signal. A NOR flash memory cell(100) includes a memory cell(110). A sense amplifier(120) senses data stored in the memory cell. A data output buffer(140) outputs data sensed by the sense amplifier in response to a clock signal. A clock delay circuit(160) delays an external clock signal, and provides the clock signal to the data output buffer. A delay control circuit(170) controls delay time of the clock delay circuit according to the frequency of the clock signal. The data output buffer controls data hold time of the sensed data in response to the clock signal, and the delay control circuit controls delay time of the clock delay circuit according to a latency value stored in a mode register.

Description

NOR FlASH MEMORY CONTROLLING DATA HOLD TIME ACCORDING TO CLOCK FREQUENCY

1 shows a memory cell of a NOR flash memory.

2 is a block diagram illustrating a NOR flash memory according to the present invention.

3 is a timing diagram illustrating an operating characteristic of the NOR flash memory illustrated in FIG. 2.

* Explanation of symbols for main parts of drawings *

100; NOR flash memory 110; Memory cell array

120; Sense amplifier 130; Data output control circuit

140; Data output buffer 150; Clock buffer

160; Clock delay circuit 170; Delay control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a NOR flash memory that adjusts a data holding time according to a clock frequency.

A semiconductor memory device is a memory device that stores data and can be read out when needed. Semiconductor memory devices can be roughly divided into random access memory (RAM) and read only memory (ROM). RAM is a so-called volatile memory that loses its stored data when the power is turned off. RAM includes Dynamic RAM (DRAM) and Static RAM (SRAM). ROM is nonvolatile memory that does not lose its stored data even when its power supply is interrupted. The ROM includes PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), Flash Memory, and the like.

Flash memory is largely classified into NAND flash memory and NOR Flash memory. NAND flash memory has a string structure in which a plurality of memory cells are connected in series to one bit line. In contrast, NOR flash memory has a structure in which a plurality of memory cells are connected in parallel to one bit line.

1 shows a memory cell of a NOR flash memory. FIG. 1A illustrates a cross-sectional view of the memory cell 10, and FIG. 1B illustrates a circuit symbol of the memory cell 10 shown in FIG. 1A and a bias condition during a read operation. Shows.

Referring to FIG. 1A, the memory cell 10 includes a source 3, a drain 4, a first insulating film 5, a floating gate 6, a second insulating film 7, and a control gate 8. And the substrate 9. The source 3 and the drain 4 are formed on the P-type substrate 9.

The source 3 is connected to the source line SL, and the drain 4 is connected to the bit line BL. The floating gate 6 is formed over the channel region with a thin first insulating film 5 of 100 Å or less therebetween. The control gate 8 is formed on the floating gate 6 with the second insulating film (or ONO film) 7 interposed therebetween. The control gate 8 is connected to the word line WL. A bulk voltage BK is applied to the substrate 9.

The source 3, the drain 4, the control gate 8, and the substrate 9 of the memory cell 10 have a predetermined bias voltage during program, erase, and read operations. Is approved.

Referring to FIG. 1B, in a read operation, a source line voltage of about 0 V is applied to the source 3, a bit line voltage of about 1 V is applied to the drain 4, and a control gate 8 is applied to the control gate 8. A word line voltage of about 5V is applied and a bulk voltage of about 0V is applied to the substrate 9.

When a read operation is performed according to such a bias condition, the programmed cell is blocked from the current path from the drain 4 to the source 3. In contrast, erased cells form a current path from the drain 4 to the source 3. Here, the programmed cell is called an 'off cell' and the erased cell is called an 'on cell'.

In general, NOR flash memory includes a sense amplifier and a data output buffer to read data stored in a memory cell during a read operation. The sense amplifier senses data stored in the memory cell, and the data output buffer outputs the sensed data to the outside in response to the clock signal.

The NOR flash memory optionally performs a synchronous read operation in synchronization with a clock signal. In this case, the NOR flash memory has data input / output characteristic parameters corresponding to respective clock frequencies. Various characteristic parameters for synchronous read operation are disclosed in a NOR Flash Memory data book published by Samsung Electronics.

For example, tBA defines burst access time and tBDH defines data hold time. When the clock frequency is 66 MHz, the maximum value of the burst access time tBA is 11 nS, and the minimum value of the data retention time tBDH is 4 nS. When the clock frequency is 133 MHz, the maximum value of the burst access time tBA is 6 nS, and the minimum value of the data retention time tBDH is 1.5 nS. That is, when the NOR flash memory operates at a low frequency of 66 MHz, the burst access time tBA cannot exceed 11 nS, and the data retention time tBDH must be longer than 4 nS. When operating at a high frequency of 133 MHz, the burst access time tBA cannot exceed 6 nS, and the data retention time tBDH must be longer than 1.5 nS. The burst access time tBA and the data hold time tBDH according to the clock frequency are shown in Figs. 3 (a) and 3 (b).

Therefore, the conventional NOR flash memory has a parameter value corresponding to each clock frequency. If a NOR flash memory with a burst access time (tBA) or data hold time (tBDH) parameter set to operate at a high frequency (133 MHz) is used at a low frequency (66 MHz), the burst access time (tBA) will result in a design margin but The holding time tBDH is problematic. The problem of the data holding time tBDH is described again in FIG. 3 (c).

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a NOR flash memory that satisfies parameter characteristics related to data output regardless of clock frequency.

The NOR flash memory according to the present invention comprises a memory cell; A sense amplifier configured to sense data stored in the memory cell; A data output buffer configured to output data sensed by the sense amplifier in response to a clock signal; A clock delay circuit that delays an external clock signal for a predetermined time and provides the clock signal to the data output buffer; And a delay control circuit for adjusting a delay time of the clock delay circuit according to the frequency of the clock signal. Herein, the data output buffer adjusts a data hold time of the sensed data in response to the clock signal.

In an embodiment, the delay control circuit adjusts the delay time of the clock delay circuit according to the latency value stored in the mode register. Alternatively, the delay control circuit adjusts the delay time of the clock delay circuit according to the information stored in the fuse circuit. Here, the fuse circuit is a laser fuse.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram illustrating a NOR flash memory according to an embodiment of the present invention. Referring to FIG. 2, the NOR flash memory 100 includes a memory cell array 110, a sense amplifier 120, a data output control circuit 130, a data output buffer 140, a clock buffer 150, and a clock delay circuit. 160, and a delay control circuit 170.

The memory cell array 110 is composed of a plurality of memory cells. The plurality of memory cells are connected to the plurality of word lines and the plurality of bit lines. Each memory cell receives a word line voltage through a word line and a bit line voltage through a bit line. The memory cell array 110 sends the data stored in the selected memory cell to the sense amplifier 120 under the control of the data output control circuit 130.

The sense amplifier 120 senses and amplifies data stored in the selected memory cell. In general, the sense amplifier 120 compares the sensing voltage and the reference voltage during a read operation. Here, the reference voltage is provided from a reference voltage generating circuit (not shown). The sense amplifier 140 performs a sensing operation using the power supply voltage Vcc or the ground voltage Vss. The sense amplifier 120 sends the sensed data to the data output buffer 140 under the control of the data output control circuit 130.

The data output control circuit 130 controls the read operation of the NOR flash memory 100. The data output control circuit 130 outputs various control signals for performing a read operation in response to the internal clock signal CLKi. Here, the internal clock signal CLKi is provided from the clock buffer 150. The clock buffer 150 buffers the external clock signal CLKx and generates an internal clock signal CLKi. The data output control circuit 130 includes all circuits related to data output, such as an address buffer and an address decoder.

The data output buffer 140 outputs data sensed by the sense amplifier 120 in a read operation. The data output buffer 140 outputs sensed data in synchronization with the clock signal CLKd. The clock signal CLKd is a delayed clock signal obtained by delaying the internal clock signal CLKi for a predetermined time. The delay clock signal CLKd is provided from the clock delay circuit 160.

The clock delay circuit 160 receives the internal clock signal CLKi and delays it for a predetermined time. Here, clock delay circuit 160 is comprised of at least one or more delay elements (not shown). The delay time of the clock delay circuit 160 is adjusted by the delay control circuit 170.

The delay control circuit 170 may be implemented in various ways. For example, the delay control circuit 170 may adjust the delay time according to the latency value stored in the mode register (not shown). Alternatively, the delay control circuit 170 may adjust the delay time using a fuse circuit (not shown). The fuse circuit stores information about the delay time of the clock delay circuit 160. Here, the fuse circuit includes an electronic fuse, a laser fuse, and the like.

3 is a timing diagram illustrating an operating characteristic of the NOR flash memory 100 illustrated in FIG. 2. FIG. 3A shows a data output of a NOR flash memory having high frequency parameter characteristics at high frequency (HF). If the clock frequency is 133 MHz, the burst access time tBA (H) is 6 nS at maximum, and the data retention time tBDH (H) is at least 1.5 nS. 3 (b) shows a data output of a NOR flash memory having low frequency parameter characteristics at a low frequency (LF). If the clock frequency is 66 MHz, the burst access time tBA (L) is at most 11 nS and the data retention time tBDH (L) is at least 4 nS.

3 (c) shows a data output of a conventional NOR flash memory having high frequency parameter characteristics at low frequency LF. For low frequency (66MHz) normal operation of NOR flash memory, up to 11nS burst access time (tBA (L)) and at least 4nS data retention time (tBDH (L)) must be guaranteed. However, referring to FIG. 2C, the conventional NOR flash memory has a burst access time tBA (H) of 6 nS and a data retention time tBDH (H) of 1.5 nS. Therefore, there is no problem because the burst access time tBA (H) is less than 11 nS, but the data holding time tBDH (H) is less than 4 nS, which is outside the allowable range. That is, the data retention time tBDH (H) should be at least 4 nS or more, but malfunction may occur because it is only 1.5 nS.

3 (d) shows the data output of the NOR flash memory according to the present invention. 3 (d) shows the data output of the NOR flash memory having high frequency parameter characteristics at low frequency LF. Referring to Figures 2 and 3 (d), the operation of the NOR flash memory 100 according to the present invention will be described.

3D illustrates an external clock signal CLKx provided to the NOR flash memory 100 and a delayed clock signal CLKd provided to the data output buffer 140. The delay clock signal CLKd is a delay of the external clock signal CLKx by a predetermined delay time tD. The predetermined delay time tD is adjusted by the delay control circuit 170. The data is output in synchronization with the delay clock signal CLKd. That is, data is output after the burst access time tBA (H) has passed from the first rising transition time point of the delay clock signal CLKd. The data is held from the second rising transition point of the delay clock signal CLKd to the data holding time tBDH (H).

On the other hand, the NOR flash memory 100 according to the present invention, as described above, in order to operate normally at a low frequency (66 MHz), a burst access time tBA (L) of up to 11 nS and a data holding time tBDH (at least 4 nS) L)) shall be guaranteed. As shown in FIG. 3 (d), when the delay time tD is adjusted in the NOR flash memory 100 according to the present invention, the data retention time tBDH (L) may be 4 nS or more. Therefore, the NOR flash memory 100 according to the present invention may satisfy all parameter characteristics related to data output regardless of a clock frequency.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

The NOR flash memory according to the present invention adjusts a delay time of a clock signal to satisfy parameter characteristics related to data output regardless of a clock frequency.

Claims (4)

Memory cells; A sense amplifier configured to sense data stored in the memory cell; A data output buffer configured to output data sensed by the sense amplifier in response to a clock signal; A clock delay circuit that delays an external clock signal for a predetermined time and provides the clock signal to the data output buffer; And A delay control circuit for adjusting a delay time of the clock delay circuit according to a frequency of the clock signal, The data output buffer adjusts a data hold time of the sensed data in response to the clock signal, and the delay control circuit adjusts a delay time of the clock delay circuit according to a latency value stored in a mode register. NOR flash memory. delete The method of claim 1, And the delay control circuit adjusts a delay time of the clock delay circuit according to information stored in a fuse circuit. The method of claim 3, wherein The fuse circuit is a NOR flash memory, characterized in that the laser fuse.

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