KR100732026B1 - Method for fabricating semiconductor device - Google Patents

Abstract

After the PLZT film 30 is formed as a raw material film of the capacitor dielectric film, the upper electrode film 31 is formed on the PLZT film 30. The upper electrode film 31 is composed of two layers of IrO _x films having different compositions. Next, the back surface of the semiconductor substrate 11 is washed. Then, the Ir adhesion film 32 is formed on the upper electrode film 31. At this time, the substrate temperature is 400 ° C or higher. Next, a TiN film and a TEOS film are sequentially formed as a hard mask. In this method, while the temperature of the semiconductor substrate 11 is maintained at 400 ° C or higher when the Ir adhesion film 32 is formed, carbon remaining on the upper electrode film 31 after cleaning the back surface is released into the chamber. do. For this reason, the adhesiveness between the TiN film | membrane formed and the Ir adhesion film 32 becomes high after that, and peeling of a TiN film becomes difficult to occur.

Ferroelectric film, upper electrode film, precious metal element, mask adhesion film, hard mask, etching, semiconductor device, manufacturing method

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

The present invention relates to a method of manufacturing a semiconductor device suitable for the manufacture of ferroelectric capacitors using batch etching.

A ferroelectric memory (FeRAM) stores information using the hysteresis characteristics of the ferroelectric. In a ferroelectric memory, a ferroelectric capacitor having a ferroelectric film as a capacitor dielectric film between a pair of electrodes is provided for each memory cell. In the ferroelectric, polarization occurs in accordance with the applied voltage between the electrodes, and spontaneous polarization remains even when the applied voltage is removed. In addition, when the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Therefore, when the spontaneous polarization is detected, the information can be read.

In the ferroelectric memory, as with other semiconductor devices, it is necessary to reduce the cell area. The structure of the ferroelectric memory is mainly classified into a planar structure and a stack structure, and the stack structure has a smaller cell area than the planar structure. The stack structure is a structure in which a capacitor is formed directly on the plug formed on the drain of the field effect transistor provided for each cell. That is, a barrier metal film, a lower electrode, a ferroelectric film, and an upper electrode are sequentially deposited directly on the W plug.

The barrier metal film plays a role of suppressing diffusion of oxygen from the upper layer into the W plug. As a material of the barrier metal film, a combination of TiN, Ir, IrO ₂ , Pt, and SRO (SrRuO ₃ ) is used. However, the barrier metal film and the lower electrode cannot be clearly distinguished because many materials that can function as the lower electrode are used as it is. As a structure in which the barrier metal film and the lower electrode film are combined, an Ir film, an IrO ₂ film, a Pt film, a PtO film, and a Pt film are stacked in this order.

In order to meet the demand for miniaturization of the device, it is preferable to etch in a shape close to the vertical without having an inclination on the side surface of each film constituting the capacitor. As such a method of etching, there is a method of collectively etching each film, and a method of collectively etching the upper electrode film and the ferroelectric film.

In order to form a ferroelectric capacitor having a stack structure by using batch etching, etching using a hard mask is required. This is because the selectivity of the organic resist mask and the ferroelectric film is low.

As the material of the hard mask used in the bulk etch, such as SiO _2, SiN, and TiN are widely used. Among them, TiN is hardly etched in etching using a gas in which oxygen is added to halogen, and therefore, TiN is suitable as a mask material for etching when forming a ferroelectric capacitor.

However, in the etching using the gas in which oxygen is added to the halogen, the etching rate significantly decreases at the time of etching the ferroelectric film. For this reason, it is not preferable to use such a gas at the time of etching a ferroelectric film in terms of throughput.

In contrast, when the SiO ₂ film is used as a mask for forming a hard mask having a laminated structure in which a SiO ₂ film is formed on the TiN film and the ferroelectric film is etched, and the TiN film is used as a mask in etching the lower electrode film, the throughput becomes good.

In addition, after depositing each film constituting the ferroelectric capacitor, it is necessary to clean the back surface (backside) of the wafer in order to remove residues of the organic resist used when forming contact holes and the like.

However, when batch etching using the above-described hard mask of the laminated structure is performed, the throughput becomes good, but when forming TEOS (Tetra Ethyl Ortho Silicate), the upper part is covered over the entire surface of the wafer. Peeling may occur between the electrode film and the hard mask, or peeling may occur in the lower electrode film and the barrier metal film at the edge of the wafer.

In addition, the loss of a capacitor may occur at the time of collective etching or when removing a hard mask. That is, the upper electrode, the capacitor dielectric film, etc. constituting the capacitor may peel off and disappear completely.

On the other hand, Japanese Laid-Open Patent Publication No. 2001-135798 discloses a structure in which a metal silicide layer is used as the wiring layer in contact with the upper electrode in order to suppress the deterioration of the characteristics of the ferroelectric capacitor by the heat treatment after the metal wiring is formed. In this structure, a laminate of IrO _x films and Ir films is used as the upper electrode. In the manufacture of the capacitor element, the upper electrode film is patterned using a lithography method (resist mask) and a dry etching method, and then the lithography method and a dry etching method are applied to the ferroelectric film and the lower electrode film. Patterning is performed.

However, in this conventional manufacturing method, a hard mask is required to perform batch etching without performing batch etching of the upper electrode film, the ferroelectric film and the lower electrode film. For this reason, the problem of peeling as mentioned above cannot be solved.

[Patent Document 1] Japanese Patent Application Laid-Open No. 2001-135798

Disclosure of the Invention

An object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress peeling of a film.

When the inventor of the present invention investigated the cause of peeling in the conventional manufacturing method, even after cleaning the back (backside) of the wafer, carbon remained on the upper electrode film, which caused this carbon, It was found that peeling occurred between the upper electrode film and the hard mask. The inventors also found that a portion where the PtO _x film and the IrO _x film directly contact each other exists at the edge of the wafer, and when a relatively large stress acts on this part during manufacturing, peeling from this part occurs.

For example, the inventors analyzed TDS (Temperature Release Gas Spectroscopy: Thermal Desertion Spectroscopy) on two kinds of wafers subjected to back cleaning. At this time, one wafer was analyzed after the ashing treatment for 30 seconds in an oxygen atmosphere of 200 ° C. after the back cleaning, and the other wafer was analyzed without the above ashing treatment. The results of the analysis are shown in Figures 1A and 1B. 1A is a graph showing an analysis result for a substance having a molecular weight of 28 (such as CO and C ₂ H ₄ ), and FIG. 1B is a graph showing an analysis result for a substance having a molecular weight of 44 (such as CO ₂ ). In FIG. 1A and FIG. 1B, ◆ shows the result with respect to the wafer which carried out the ashing process, and ■ shows the result with respect to the wafer which did not perform the ashing process.

In the wafer without ashing treatment, as shown in FIGS. 1A and 1B, an escape peak of a gas containing carbon in the vicinity of 350 ° C. was clearly seen. In contrast, in the wafer subjected to ashing, as shown in FIGS. 1A and 1B, almost no escape peak of the gas containing carbon was observed. These facts mean that carbon remains on the surface of the wafer even after the back cleaning is performed.

Moreover, this inventor observed the cross section of the periphery of a wafer using a scanning electron microscope (SEM). 2A and 2B are SEM photographs showing a cross section of the periphery of the wafer. In the lower electrode and the capacitor dielectric film, peeling occurred at the interface between the IrO _x film and the PtO film. In the upper electrode and the hard mask, peeling occurred at the interface between the IrO _x film serving as the upper electrode and the TiN film constituting the hard mask.

2A and 2B, when an IrO _x film (thickness: 200 nm) is formed on a thermal oxide film (SiO ₂ film) (FOX), and a TiN film and a TEOS film are further formed thereon as a hard mask. In the peripheral portion, peeling occurred at the interface between the thermal oxide film and the IrO _x film. This is considered to be because not only the adhesion between the IrO _x film and the TiN film is low, but also the relatively strong stress acted by the thickness of the IrO _x film becoming thin at about 40 nm.

The present invention has been made based on these experimental results and recognition.

In the method for manufacturing a semiconductor device according to the present invention, a ferroelectric film is formed on the semiconductor substrate as a raw material film of a capacitor dielectric film of a ferroelectric capacitor. Next, an upper electrode film is formed on the ferroelectric film as a raw material film of the upper electrode of the ferroelectric capacitor. Then, a mask adhesion film containing a noble metal element is formed on the upper electrode film. Thereafter, a hard mask is formed on the mask adhesion film. The upper electrode film and the ferroelectric film are etched using the hard mask.

1A is a graph showing an analysis result for a substance having a molecular weight of 28, and FIG. 1B is a graph showing an analysis result for a substance having a molecular weight of 44.

2A and 2B are SEM photographs showing a cross section of the periphery of the wafer;

3 is a circuit diagram showing a configuration of a memory cell array of a ferroelectric memory (semiconductor device) manufactured by the method according to the embodiment of the present invention.

4A to 4E are sectional views showing a method of manufacturing the ferroelectric memory (semiconductor device) according to the first embodiment of the present invention in the order of steps.

5 is a cross-sectional view showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the second embodiment of the present invention.

6 is a graph showing the results of a test of switching characteristics.

7 is a cross-sectional view showing a method for manufacturing a ferroelectric memory (semiconductor device) according to the third embodiment of the present invention.

Best Mode for Carrying Out the Invention

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described concretely with reference to an accompanying drawing. 3 is a circuit diagram showing a configuration of a memory cell array of a ferroelectric memory (semiconductor device) manufactured by the method according to the embodiment of the present invention.

The memory cell array includes a plurality of bit lines 3 extending in one direction, and a plurality of word lines 4 and plates extending in a direction perpendicular to the direction in which the bit lines 3 extend. A plate line 5 is provided. Further, the plurality of ferroelectric memory memory cells according to the present embodiment are arranged in an array so as to match the lattice formed by the bit lines 3, the word lines 4, and the plate lines 5. have. Each memory cell is provided with a ferroelectric capacitor 1 and a MOS transistor 2.

The gate of the MOS transistor 2 is connected to the word line 4. One source / drain of the MOS transistor 2 is connected to the bit line 3, and the other source / drain is connected to one electrode of the ferroelectric capacitor 1. The other electrode of the ferroelectric capacitor 1 is connected to the plate line 5. Further, each word line 4 and plate line 5 are shared by a plurality of MOS transistors 2 side by side in the same direction as the direction in which they extend. Similarly, each bit line 3 is shared by a plurality of MOS transistors 2 side by side in the same direction in which they extend. The direction in which the word line 4 and the plate line 5 extend and the direction in which the bit line 3 extends may be called "row direction" and "column direction", respectively.

In the memory cell array of the ferroelectric memory configured as described above, data is stored in accordance with the polarization state of the ferroelectric film provided in the ferroelectric capacitor 1.

(1st embodiment)

Next, a first embodiment of the present invention will be described. 4A to 4E are cross-sectional views showing a method of manufacturing the ferroelectric memory (semiconductor device) according to the first embodiment of the present invention in the order of steps. 4A to 4E, however, show a cross section perpendicular to the direction in which the bit line 3 extends. 4A to 4E show portions corresponding to two MOS transistors that share one bit line (corresponding to bit line 3 in FIG. 1).

In 1st Embodiment, as shown to FIG. 4A, the well 12 is first formed in the surface of the semiconductor substrate 11, such as a silicon substrate. Then, the element isolation region 13 is formed on the surface of the semiconductor substrate 11 by, for example, shallow trench isolation (STI). Subsequently, the gate insulating film 14, the gate electrode 15, the cap film 16, the side wall 17, the source / drain diffusion layer 18 and the silicide layer 19 are formed on the surface of the well 12. The MOS transistor 20 is formed as a switching element. This MOS transistor 20 corresponds to the MOS transistor 2 in FIG. In addition, although two source / drain diffusion layers 18 are formed in each MOS transistor 20 for the source and the drain, one of them is shared between the two MOS transistors 20.

Next, the silicon oxynitride film 21 is formed on the entire surface so as to cover the MOS transistor 20, and the SiO ₂ film 22 is further formed on the entire surface as an interlayer insulating film, and CMP (chemical mechanical polishing) The SiO ₂ film 22 is planarized by this. The silicon oxynitride film 21, the gate insulating film 14 is formed to prevent hydrogen degradation such as at the time of forming the SiO ₂ film 22. Thereafter, contact holes reaching up to each silicide layer 19 are formed in the SiO ₂ film 22 and the silicon oxynitride film 21 to open the plug contact portion. Then, after the glue film 23 is formed in the contact hole, the W plug 24 is formed by embedding the W film by CVD, for example, by performing CMP to planarize it.

Subsequently, as shown in FIG. 4B, the Ir film 25 is formed on the SiO ₂ film 22 by sputtering. As conditions at this time, for example, the substrate temperature is 500 ° C, the deposition power is 1 kW, the flow rate of Ar gas is 100 sccm, the pressure in the chamber is 0.35 Pa, and the deposition time is 176 seconds. It is done. As a result, an Ir film 25 having a thickness of about 250 nm is obtained.

Then, an IrO _x film 26 is formed on the Ir film 25 by sputtering. As conditions at this time, for example, the substrate temperature is 50 ° C, the deposition power is 1 kW, the flow rate of Ar gas is 60 sccm, the flow rate of O ₂ gas is 60 sccm, and the pressure in the chamber Is 0.37 Pa, and the film formation time is 10 seconds. As a result, an IrO _x film 26 having a thickness of about 28 nm is obtained.

Then, a Pt film 27 is formed on the IrO _x film 26 by sputtering. As the conditions at this time, for example, the substrate temperature is 350 ° C, the deposition power is 1 kW, the flow rate of Ar gas is 100 sccm, the pressure in the chamber is 0.38 Pa, and the deposition time is 8 seconds. It is done. As a result, a Pt film 27 having a thickness of about 15 nm is obtained. In the formation of the Pt film 27, a clamp ring is used to prevent the Pt film 27 and the semiconductor substrate (silicon substrate) 11 from directly contacting and reacting. For this reason, there exists a part in which the Pt film 27 is not formed in the edge of the semiconductor substrate 11.

Thereafter, a PtO _x film 28 is formed on the Pt film 27 by sputtering. As the conditions at this time, for example, the substrate temperature is 350 ° C, the deposition power is 1 kW, the flow rate of Ar gas is 36 sccm, the flow rate of O ₂ gas is 144 sccm, and the pressure in the chamber Is 6.2 Pa, and the film formation time is 22 seconds. As a result, a PtO _x film 28 having a thickness of about 25 nm is formed. In the edge of the semiconductor substrate 11, there is a portion where the Pt film 27 is not formed. In this portion, the PtO _x film 28 is formed on the IrO _x film 26.

Then, a Pt film 29 is formed on the PtO _x film 28 by sputtering. As conditions at this time, for example, the substrate temperature is 100 ° C, the deposition power is 1 kW, the flow rate of Ar gas is 100 sccm, the pressure in the chamber is 0.4 Pa, and the deposition time is 32 seconds. It is done. As a result, a Pt film 29 having a thickness of about 50 nm is formed.

These Ir films 25, IrO _x films 26, Pt films 27, PtO _x films 28 and Pt films 29 constitute a barrier metal film and a lower electrode film.

In addition, the Ir film 25 and the IrO _x film 26 can be formed using the same chamber, and the Pt film 27, the PtO _x film 28, and the Pt film 29 use the same chamber. Can be formed.

Next, the Pt films 27 and 29 are crystallized by performing rapid heat treatment in an Ar atmosphere at 750 ° C. for 60 seconds, for example.

Then, as shown in FIG. 4C, a PLZT ((Pb, La) (Zr, Ti) O ₃ ) film 30 is formed on the Pt film 29 by sputtering, and the crystallization annealing is performed. The PLZT film may be formed, for example, by the MOCVD method. However, when the MOCVD method is used, it is preferable to change the configuration of the lower electrode.

Thereafter, the upper electrode film 31 is formed on the PLZT film 30 by sputtering. The upper electrode film 31 is composed of, for example, two layers of IrO _x films having different compositions from each other. In the formation of the IrO _x film for the first layer, for example, the substrate temperature is set to room temperature, the film forming power is 2 kW, the flow rate of Ar gas is 100 sccm, and the flow rate of O ₂ gas is 59 sccm. The IrO _x film of the first layer is, for example, about 50 nm. After the first layer of IrO _x film is formed, annealing is performed, and then the second layer of IrO _x film is formed. The IrO _x film of the second layer is, for example, about 75 to 125 nm.

Next, the back surface (back surface) of the semiconductor substrate (wafer) 11 is washed.

An Ir adhesion film (mask adhesion film) 32 is formed on the upper electrode film 31 by sputtering. As the conditions at this time, for example, the substrate temperature is 400 ° C or higher, the flow rate of Ar gas is 100 sccm, the deposition power is 1 kW, and the deposition time is 7 seconds. As a result, an Ir adhesion film 32 having a thickness of about 10 nm is formed. In forming the Ir adhesion film 32, the semiconductor substrate 11 is held on the wafer stage set at 400 ° C. for 30 seconds and then film formation is started. This is to stabilize the substrate temperature.

After the Ir adhesion film 32 is formed, as shown in Fig. 4D, the upper electrode film 31, the PLZT film 30, the Pt film 29, the PtO _x film 28, the Pt film 27, When patterning the IrO _x film 26 and the Ir film 25, a TiN film 33 and a TEOS film 34 which are used as hard masks are sequentially formed. The TiN film 33 is formed at 200 ° C., for example, and the thickness thereof is about 200 nm. The TEOS film 34 is formed, for example, at 390 ° C., and has a thickness of about 390 nm.

Next, by patterning the TEOS film 34 and the TiN film 33, a hard mask is formed only in a predetermined region for forming the stacked ferroelectric capacitor.

Then, as shown in FIG. 4E, the upper electrode film 31, the PLZT film 30, and the Pt film (using the patterning and etching technique using the TEOS film 34 and the TiN film 33 as hard masks) are used. 29), the PtO _x film 28, the Pt film 27, the IrO _x film 26, and the Ir film 25 are collectively processed to form a ferroelectric capacitor having a stacked structure. This ferroelectric capacitor corresponds to the ferroelectric capacitor 1 in FIG.

Thereafter, the hard masks (TEOS film 34 and TiN film 33) are removed. Subsequently, recovery annealing is performed in order to recover damage to the PLZT film 30 by the film forming, etching process or the like.

Next, an alumina film 35 is formed on the entire surface as a protective film to protect the ferroelectric capacitor from process damage. Then, the interlayer insulating film 36 is formed on the entire surface, and the planarization of the interlayer insulating film 36 is performed by CMP.

Thereafter, contact holes reaching the W plug 24 are formed in the interlayer insulating film 36 and the alumina film 35 using patterning and etching techniques. Subsequently, after forming the glue film 37 in this contact hole, the W film is embedded and the W plug 38 is formed by CMP planarization.

Next, a W oxidation prevention insulating film (not shown) is formed over the entire surface. As the W oxidation preventing insulating film, for example, a SiON film is used. Then, using a patterning and etching technique, contact holes reaching the Ir adhesion film 32 are formed in the W oxidation preventing insulating film and the interlayer insulating film 36. Subsequently, annealing is performed to recover damage by etching. After this annealing, the W oxidation prevention insulating film is removed by etch back.

Next, the lower glue film 39, the wiring material film 40, and the upper glue film 41 are sequentially deposited.

Then, an antireflection film (not shown) is formed on the glue film 41, and a resist film (not shown) is applied. Thereafter, the resist film is processed to match the wiring pattern, and the antireflection film, the glue film 41, the wiring material film 40 and the glue film 39 are etched using the processed resist film as a mask. As the antireflection film, for example, a SiON film is used. By this etching, as shown in FIG. 4E, the wiring 42 which consists of the predetermined | prescribed planar glue film 41, the wiring material film 40, and the glue film 39 is obtained.

Thereafter, the interlayer insulating film 43 is formed, the glue film 44 and the W plug 45 are embedded in the contact holes, and the wiring after the second layer is formed from the bottom. For example, a cover film made of a TEOS film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor. In addition, when forming the upper layer wiring, the wiring 42 connected to the upper electrode film 31 via the Ir adhesion film 32 is connected to the plate line, and the source shared by the two MOS transistors 20. The wiring 42 connected to the drain diffusion layer 18 is connected to the bit line. The gate electrode 15 may be itself a word line, and in the upper layer wiring, the gate electrode 15 may be connected to the word line.

According to this first embodiment, the carbon remaining on the upper electrode film 31 after the back cleaning is maintained while the temperature of the semiconductor substrate 11 is maintained at 400 ° C or higher in forming the Ir adhesion film 32. Is released into the chamber. For this reason, the adhesiveness between the TiN film 33 formed and the Ir adhesion film 32 becomes high after that, and peeling of the TiN film 33 becomes difficult to occur.

In addition, when forming the Ir adhesion film 32, since it is not necessary to use the clamp ring required for formation of the Pt film, the Ir adhesion film 32 is formed over the entire surface of the semiconductor substrate 11. In addition, the film formation temperature of Ir adhesion film 32 is 400 degreeC, and the internal stress of the Ir film formed at this temperature is extremely low. For this reason, the stress acting on each film already formed is also small, and even if the IrO _x film 26 and the PtO _x film 28 directly contact each other, no peeling occurs between them.

In fact, when the inventor of the present invention formed a hard mask as in the first embodiment, good results were obtained. Here, the content is demonstrated. In addition, in order to compare with 1st Embodiment (Example 1), the following Example 2 and 3 and Comparative Examples 4 and 5 were also evaluated similarly to Example 1.

In Example 2, after the back washing was performed, ashing was performed in an oxygen atmosphere at 200 ° C. for 2 minutes, and then a hard mask (TEOS film / TiN film) was formed.

In Example 3, after forming a TiN film similarly to Example 2, the ring-shaped part of 3 mm was removed by cutting from the outer edge of the semiconductor substrate 11. Subsequently, a TEOS film was formed.

In the comparative example 4, after performing back surface washing, the hard mask was formed as it was. It is a method similar to the conventional method.

In Comparative Example 5, after the back washing, a TiN film was formed, and the TEOS film was formed at a film forming temperature of 340 ° C. under high film forming power.

And the generation | occurrence | production situation of the peeling in the center part of a semiconductor substrate (wafer) and the peeling in the edge was evaluated about these samples. The results are shown in Table 1. The denominator in Table 1 is the number of the semiconductor substrates tested, and the molecule | numerator is the number of the semiconductor substrates which peeled.

As shown in Table 1, in Examples 1-3, peeling in the center part did not generate | occur | produce at all. However, in Example 2, peeling at the edge occurred. In addition, in Example 3, although peeling is suppressed, compared with Example 1, the number of processes increases.

On the other hand, in Comparative Examples 4 and 5, peeling occurred at the central portion and the edges.

(2nd embodiment)

Next, a second embodiment of the present invention will be described. 5 is a cross-sectional view showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the second embodiment of the present invention. 5 shows a cross section perpendicular to the direction in which the bit line 3 extends.

In 2nd Embodiment, first, as shown in FIG. 5, the process from formation of the well 12 to formation of the W plug 24 is performed similarly to 1st Embodiment.

Next, an Ir film is formed over the entire surface, for example, at a thickness of 400 nm. The Ir film is then patterned using patterning and etching techniques to selectively form a barrier metal film 51 over the W plug 24 connected to the lower electrode of the ferroelectric capacitor.

Thereafter, oxidation of the W plug 24 is prevented, and at the same time, the entire W antioxidant film 52 serving as an etching stopper when etching the lower electrode film, the ferroelectric film, and the upper electrode film formed in a later step is performed. On the surface, a capacitor adhesion film 53 having high adhesion to the lower electrode film is formed thereon. As the W antioxidant film 52, for example, a SiN film or a SiON film having a thickness of about 100 nm is formed. As the capacitor adhesion film 53, for example, a TEOS film having a thickness of about 800 nm is formed.

Next, CMP is performed using the barrier metal film 51 as a stopper. In addition, the capacitor adhesion film 53 also contributes to the oxidation prevention of the W plug 24.

Then, similarly to the first embodiment, the process after formation of the Ir film 25 is performed to complete the ferroelectric memory having the ferroelectric capacitor. However, in this embodiment, since the barrier metal film 51 is formed under the Ir film 25, the thickness of the Ir film 25 is thinner than that of the first embodiment, for example, 30 nm.

According to this second embodiment, the same effect as that of the first embodiment is obtained, and the W plug 24 is provided due to the presence of the barrier metal film 51, the W antioxidant film 52, and the capacitor adhesion film 53. The oxidation of) becomes more difficult to occur.

In fact, when the inventor of the present invention formed a hard mask as in the second embodiment, good results were obtained. Here, the content is demonstrated. In addition, the following Example 12 and Comparative Example 13 were evaluated similarly to Example 11 for the comparison with 2nd Embodiment (Example 11).

Moreover, in Example 12, after performing back washing, the ashing process was performed in 200 degreeC for 2 minutes in oxygen atmosphere, and the TiN film was formed after that. And similarly to Example 3, the ring-shaped part of 3 mm was removed from the outer edge of the semiconductor substrate 11 by cutting. Subsequently, a TEOS film was formed.

In the comparative example 13, after performing back surface washing, the hard mask was formed as it was in the same manner as in the comparative example 4. It is a method similar to the conventional method.

And the generation | occurrence | production situation of the peeling in the center part of a semiconductor substrate (wafer) and the peeling in the edge was evaluated about these samples. The results are shown in Table 2. The denominator in Table 2 is the number of semiconductor substrates tested, and the molecule is the number of semiconductor substrates where peeling occurred.

As shown in Table 2, in Examples 11 and 12, peeling in the center part did not occur at all. However, in Example 12, although peeling was suppressed, compared with Example 11, the number of processes increases.

On the other hand, in Comparative Example 13, peeling occurred at the center portion and the edges.

In addition, about Example 11 and 12, after performing the etching at the high temperature using a hard mask, the inspection of the capacitor omission in the effective shot using a defect inspection apparatus, and the capacitor outside the effective shot using an optical microscope The test | inspection of loss | disappearance and the test | inspection of capacitor peeling were performed. The results are shown in Table 3. The denominator in Table 3 is the number of semiconductor substrates subjected to the test, and the molecule is the number of semiconductor substrates on which peeling or capacitor disappearance occurred. Here, "capacitor omission" means that the upper electrode or ferroelectric film of the capacitor is completely peeled off. In addition, in the inspection of capacitor peeling, the situation of peeling (not completely peeling off) which partially occurred in any of the films constituting the capacitor was observed. In addition, the loss of the capacitor out of the effective shot occurred at the wet processing for removing the TiN film constituting the hard mask, and the peeling of the capacitor occurred at the wet processing. In addition, "in an effective shot" means the part which the predetermined rectangular area was ensured in the center part of a wafer, and "out of an effective shot" means the part which the predetermined rectangular area is not secured in the peripheral part of a wafer. In addition, the inspection object of capacitor peeling is a capacitor whose length of one side is 200 micrometers in plan view.

As shown in Table 3, in Example 11, defect did not generate | occur | produce by either test | inspection. On the other hand, in Example 12, capacitor peeling occurred before the wet treatment, and capacitor disappearance outside the effective shot occurred after the wet treatment. From this result, it turned out that formation of Ir adhesive film is the most effective.

In addition, the inventors of Example 11 and 12 carried out the measurement of the switching charge amount Qsw as a test of the switching characteristics of the capacitor in the state where the wiring of the first layer was formed from the bottom. In this measurement, switching voltages were 1.8V and 3.0V. This result is shown in FIG.

As shown in FIG. 6, in Example 11, the switching charge amount was about 1 μm / cm ² higher than that of Example 12. From this, it is thought that Ir adhesion film does not have a side effect of a catalyst.

(Third embodiment)

Next, a third embodiment of the present invention will be described. In the first and second embodiments, the present invention is applied to a ferroelectric capacitor having a stack structure. In the third embodiment, the present invention is applied to a ferroelectric capacitor having a planar structure.

In the planar ferroelectric capacitor, the upper electrode film and the ferroelectric film are collectively etched to suppress an increase in the capacitor area. In this batch etching, generally, a single layer TiN film, SiON film, SiN film, TEOS film, or the like is used as the hard mask. Therefore, similarly to the ferroelectric capacitor of the stack structure, when the hard mask is formed, peeling of the film and loss of the capacitor are likely to occur when the hard mask is removed after the batch etching is performed.

This embodiment solves such a subject. 7 is a cross-sectional view showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the third embodiment of the present invention. 7 shows a cross section perpendicular to the direction in which the bit line 3 extends.

In 3rd Embodiment, first, as shown in FIG. 7, the process from formation of the well 12 to formation of the W plug 24 is performed similarly to 1st Embodiment.

Next, a lower electrode adhesion film and a Pt film (not shown) are sequentially formed on the entire surface. The lower electrode adhesion film and the Pt film (lower electrode film) are formed by, for example, a sputtering method. The lower electrode adhesion film is formed at 20 ° C., for example, and its thickness is about 20 nm. In addition, a Pt film is formed at 100 degreeC, for example, and the thickness is about 175 nm. As the lower electrode adhesion film, for example, a Ti film, a TiO _x film, or an Al ₂ O ₃ film can be used. Then, the lower electrode adhesion film and the Pt film are patterned to form the lower electrode 61.

A ferroelectric film, for example, a PLZT film (not shown), is then formed on the Pt film (lower electrode film) by the sputtering method. Thereafter, the PLZT film is subjected to heat treatment of 600 ° C. or higher in an Ar and O ₂ atmosphere by RTA (Rapid Thermal Annealing). As a result, the ferroelectric film is crystallized and the Pt film as the lower electrode film is densified. For this reason, mutual diffusion of Pt and O in the vicinity of an interface between a Pt film and a ferroelectric film is suppressed.

Thereafter, on the crystallized ferroelectric film, an upper electrode film (not shown) made of IrO ₂ having a thickness of about 200 nm is formed by the sputtering method.

Then, the back surface of the semiconductor substrate (wafer) 11 is washed.

Next, an Ir adhesion film (not shown) is formed on the upper electrode film by the sputtering method. An Ir adhesion film is formed at the substrate temperature of 400 degreeC, for example, and the thickness is about 10 nm. In the same manner as in the first embodiment, a TiN film and a TEOS film are sequentially formed as a hard mask for batch etching. Then, the TiN film and the TEOS film are patterned.

Then, by collectively etching the upper electrode film and the ferroelectric film, the capacitor dielectric film 62 made of the ferroelectric film and the upper electrode 63 made of the Pt film are formed. Then, the hard mask is removed. Thereafter, recovery annealing is performed (650 ° C. for 60 minutes in an oxygen atmosphere).

In the same manner as in the first embodiment, the process after formation of the alumina film 35 is performed to complete the ferroelectric memory having the ferroelectric capacitor.

According to this third embodiment, even when a ferroelectric capacitor having a planar structure is manufactured, peeling off of the hard mask can be prevented.

In addition, the mask adhesion film is not limited to an Ir film, for example, a Ru film, a Rh film, a Pd film, etc. may be used, and the oxide film of these elements may be used.

In addition, the materials of the upper electrode film and the lower electrode film are not limited. As the upper electrode film, for example, an oxide film of Ir, Ru, Pt, Rh, Pd may be used, or a laminate of such oxide films may be used. Alternatively, a laminate formed by forming an SrRuO ₃ film on these oxide films may be used.

In addition, it is preferable to make the temperature at the time of batch etching into normal temperature or high temperature.

As a part of the hard mask, a Ti film may be used instead of the TiN film.

As the ferroelectric film, a compound film having a perovskite structure, such as a PZT (Pb (Zr, Ti) O ₃ ) film, a film in which trace amounts of Ca, Sr, Si, etc. are added to the PZT film, in addition to the PLZT film; Or a compound film having a Bi layer structure such as SBT (SrBi ₂ Ta ₂ O ₉ ) may be used. The method of forming the ferroelectric film is not particularly limited, and the ferroelectric film can be formed by the sol-gel method, the sputtering method, the MOCVD method, or the like.

As described above in detail, the present invention can prevent peeling and loss of a capacitor when forming a hard mask. For this reason, a ferroelectric capacitor having a stack structure suitable for miniaturization can be manufactured with high yield.

TABLE 1

sample Peeling in the center Peeling at the Edge Example 1 0/40 0/40 Example 2 0/10 10/10 Example 3 0/7 0/7 Comparative Example 4 40/40 40/40 Comparative Example 5 4/13 2/13

TABLE 2

sample Peeling in the center Peeling at the Edge Example 11 0/40 0/40 Example 12 0/7 0/7 Comparative Example 13 30/30 30/30

TABLE 3

sample Defect inspection device Optical microscope Capacitor Dissipation in Effective Shot Capacitor Dissipation Outside Effective Short Peeling of the Capacitor Example 11 0/2 0/2 0/4 Example 12 0/2 1/1 3/3

Claims (20)

Forming a ferroelectric film on the semiconductor substrate as a raw material film of the capacitor dielectric film of the ferroelectric capacitor; Forming an upper electrode film as a raw material film of the upper electrode of the ferroelectric capacitor on the ferroelectric film; Forming a mask adhesion film containing a noble metal element on the upper electrode film; Forming a hard mask on the mask adhesion film; Etching the upper electrode film and the ferroelectric film using the hard mask, It has a manufacturing method of the semiconductor device characterized by the above-mentioned. The method of claim 1, And a step of washing the back surface of the semiconductor substrate between the step of forming the upper electrode film and the step of forming the mask adhesion film. The method of claim 1, The step of forming the mask adhesion film includes a step of heating the semiconductor substrate to 400 ° C. or higher. The method of claim 2, The step of forming the mask adhesion film includes a step of heating the semiconductor substrate to 400 ° C. or higher. The method of claim 1, Before the step of forming the ferroelectric film, a step of forming a lower electrode film on the upper side of the semiconductor substrate as a raw material film of the lower electrode of the ferroelectric capacitor; And the ferroelectric film is formed over the lower electrode film. The method of claim 2, Before the step of forming the ferroelectric film, a step of forming a lower electrode film on the upper side of the semiconductor substrate as a raw material film of the lower electrode of the ferroelectric capacitor; And the ferroelectric film is formed over the lower electrode film. The method of claim 5, And in the step of etching the upper electrode film and the ferroelectric film, the lower electrode film is also etched using the hard mask. The method of claim 6, And in the step of etching the upper electrode film and the ferroelectric film, the lower electrode film is also etched using the hard mask. The method of claim 1, And a film selected from the group consisting of an Ir film, a Ru film, an Rh film, and a Pd film as the mask adhesion film. The method of claim 1, An oxide film of one element selected from the group consisting of Ir, Ru, Rh and Pd is formed as the mask adhesion film. delete delete delete delete delete delete delete delete delete The method of claim 1, When forming the mask adhesion film, carbon remaining on the upper electrode film is removed.

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