KR100731430B1 - Thin film transistor having double active layer and the fabrication method thereof, and flat panel display device and organic light emitting device and liquid crystal display including the tft - Google Patents
Thin film transistor having double active layer and the fabrication method thereof, and flat panel display device and organic light emitting device and liquid crystal display including the tft Download PDFInfo
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Abstract
The thin film transistor having the structure according to one aspect of the present invention is composed of a lower layer which is an argon atmosphere layer and a double layer which is an upper layer which is a hydrogen atmosphere layer and the argon atmosphere layer which is a lower layer has a very thin amorphous incubation layer, Therefore, it contributes to reduce the source-drain current in the OFF state of the channel layer. Further, since the crystal grain size is large, the crystallinity of the following upper layer can be increased to improve the mobility of the upper layer in which the channel is formed.
Description
1 is a schematic view of an active layer of a thin film transistor according to the present invention,
2 is a graph showing the Raman spectrum of (a) μc-Si (H 2 ), (b) μc-Si (Ar)
3 is a TEM photograph of (a) μc-Si (H 2 ) and (b) μc-Si (Ar)
Figure 4 shows the HAADF image of μc-Si (Ar)
5 is a graph showing changes in the total conductivity σ S and the conductivity σ H of the upper layer in the bilayer according to the thickness variation of the μc-Si (Ar) layer as the lower layer.
BACKGROUND OF THE
OLEDs and LCDs are divided into passive matrix (PM) and active matrix (AM) schemes according to the driving method. In recent years, the AM scheme, which can individually control pixels, Respectively. The AM type OLED or LCD has one or more TFTs per pixel.
Thin film transistors used for display devices such as AMOLED and AMLCD are generally formed by depositing silicon on a transparent substrate such as glass or quartz, forming gate and gate electrodes, doping a source and a drain with dopants, And then forming an insulating layer thereon.
The active layer in which the source, drain, and channel of the thin film transistor are formed is usually formed by depositing a silicon layer on a transparent substrate such as glass using a chemical vapor deposition (CVD) method. However, the silicon layer directly deposited on the substrate by CVD or the like has a low electron mobility as an amorphous silicon film. Therefore, a technique of crystallizing the amorphous silicon layer into a crystalline silicon layer of a polycrystalline structure may be used to increase electron mobility.
Low temperature polycrystalline silicon (LTPS) or amorphous silicon (a-Si) can be used as an active layer in thin film transistor panels for AMOLED or AMLCD.
Among these, a-Si is advantageous in uniformity over a wide area, low cost, and no limit on the size of a panel. On the other hand, the a-Si has a very low electron mobility, a bias stress, The stability is lowered.
In addition, LTPS has an advantage of excellent electron transporting ability compared to a-Si, but it is expensive because of its complicated process and low yield, and has a poor uniformity over a wide area. There is a disadvantage in that there is a limit.
Due to the above-mentioned disadvantages of LTPS and a-Si, microcrystalline Si (hereinafter referred to as " μc-Si ") has been sought as an active layer of a thin film transistor as an alternative material for these materials.
The deposition process and equipment of μc-Si is similar to that of a-Si, so it has the advantage that a-Si possesses for LTPS. Therefore, the uniformity is good over a wide area, the cost is low, and the panel size is not limited. In addition, the μc-Si thin film transistor has excellent electron mobility, a large driving current, and excellent stability under bias stress as compared with an a-Si thin film transistor. Furthermore, μc-Si can produce very attractive p-channel thin film transistors in AMOLED technology.
The advantages and disadvantages of these various silicon materials are summarized in Table 1.
[Table 1] Summary of advantages and disadvantages of various silicon materials used as active layers of thin film transistors
The structure of μc-Si can have various structures from hydrogen-added amorphous structure to polycrystalline structure with different particle sizes depending on the deposition technique employed and deposition conditions thereof. In addition, the volume fraction of the crystalline varies depending on the film thickness.
Conventional μc-Si films are usually formed in a hydrogen atmosphere to include an amorphous incubation layer about 10-50 nm thick at the substrate interface, and the crystallinity at the top of the film increases. Near the film surface of 200-300 nm thickness, the volume fraction of crystalline can reach 100%.
However, this thick channel layer has the problem of increasing the source-drain current in the OFF state. In order to obtain a product having excellent performance, the active layer should have a high crystallinity with a thin thickness of 100 nm or less. Therefore, the amorphous incubation layer is very thin or needs to be removed.
In other words, in order for μc-Si to be used as an active layer of a thin film transistor by making full use of the advantages described above in comparison with LTPS or a-Si, the amorphous incubation layer is formed to be very thin so as to reduce the total thickness of the active layer, It is necessary to reduce the source-drain current and to improve the mobility by increasing the crystallinity of the active layer. However, the μc-Si film formed in the conventional hydrogen atmosphere did not satisfy both of these conditions at the same time.
It is an object of the present invention to improve the mobility while keeping the thickness of the μc-Si active layer of a thin film transistor used in flat panel display devices such as AMOLED and AMLCD thin.
According to an aspect of the present invention, there is provided a thin film transistor comprising:
And a microcrystalline silicon active layer, wherein the active layer is composed of an upper layer and a lower layer, the lower layer is an argon atmosphere layer, and the upper layer is a hydrogen atmosphere layer.
At this time, the thickness of the lower layer is preferably 5 nm or more.
The thickness of the active layer is preferably 100 nm or less.
Further, it is preferable that the thickness of the lower layer accounts for 20 to 60% of the total thickness. At this time, the crystallinity of the lower layer is 50% or more, and the grain size existing in the lower layer is 15 to 30 nm.
Also, the thin film transistor may have a top gate structure.
According to another aspect of the present invention, there is provided a flat panel display device including the thin film transistor.
According to still another aspect of the present invention, there is provided an active matrix organic light emitting display device (AMOLED) or a liquid crystal display device (AMLCD), wherein the thin film transistor is mounted.
According to another aspect of the present invention, there is provided a method of forming a thin film transistor,
A first step of forming a film in an argon atmosphere, and a second step of forming a film in a hydrogen atmosphere, the method comprising: forming a microcrystalline silicon active layer;
At this time, when the film thickness formed in the first step reaches 20 to 60% of the whole, it is preferable to perform the second step.
In addition, the active layer may be formed by a plasma enhanced chemical vapor deposition (PECVD) method.
Further, the active layer may be doped with boron (B) by an ion shower method.
Hereinafter, the structure of the AMOLED and the AMLCD will be briefly described, and the active layer of the thin film transistor used in the AMOLED and the AMLCD will be described in detail with reference to the accompanying drawings. However, the content of the present invention is not limited to AMOLED and AMLCD, and can be applied to any flat panel display device using the thin film transistor described below.
The AMOLED or AMLCD according to the present invention is the same as the conventional AMOLED structure and the AMLCD structure except for the active layer of the thin film transistor arranged for each pixel.
First, the structure of the AMOLED with the thin film transistor is briefly described.
In the AMOLED, a semiconductor active layer, a gate electrode, and source and drain electrodes are provided on the upper surface of the glass substrate and the buffer layer. A gate insulating film is interposed between the semiconductor active layer and the gate electrode to be insulated, and an interlayer insulating film is interposed between the gate electrode and the source and drain electrodes to be insulated. The source and drain electrodes are respectively connected to the source and drain regions of the semiconductor active layer through contact holes. A passivation film and a planarizing film are stacked on the source and drain electrodes, and an anode layer is disposed on the planarizing film. The anode layer is connected to the drain electrode. An organic layer is coated on the anode layer, and a cathode layer is coated on the anode layer, thereby forming the AMOLED. However, the structure of the AMOLED of the present invention is not limited to the above-described back light emitting structure, and may have a front or both-side light emitting structure, or may adopt various existing structures.
Next, the structure and principle of the AMLCD equipped with the thin film transistor will be briefly described.
The AMOLED includes an upper array substrate and a lower array substrate bonded together with a liquid crystal therebetween. The liquid crystal is rotated in response to an electric field applied thereto to adjust the amount of light transmitted through the lower array substrate. The upper array substrate has a color filter and a common electrode formed on the back surface of the upper substrate. The color filter is arranged in a striped form of red (R), green (G), and blue (B) color filter layers to transmit light in a specific wavelength band, thereby enabling color display. The lower array substrate is formed such that a data line and a gate line, which are insulated with a gate insulating film therebetween, cross each other on the entire surface of the lower substrate, and a thin film transistor is formed at the intersection.
The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode with a channel portion including an active layer and an ohmic contact layer therebetween. The TFT is connected to the pixel electrode through a contact hole passing through the protective film. Such a TFT selectively supplies the data signal from the data line to the pixel electrode in response to the gate signal from the gate line.
The pixel electrode is formed of a transparent conductive material having a high light transmittance and located in a cell region divided by a data line and a gate line. This pixel electrode generates a potential difference with the common electrode by the data signal supplied via the drain electrode. The liquid crystal located between the lower substrate and the upper substrate due to this potential difference is rotated by the dielectric anisotropy. Thus, the light supplied from the light source via the pixel electrode is transmitted to the upper substrate. However, the structure of the AMLCD of the present invention is not limited to the structure described above, and various existing structures may be adopted.
As described above, a source, a drain, and a channel are formed in the active layer of the thin film transistor mounted on the AMOLED or the AMLCD. The active layer is formed on the glass substrate and the buffer layer.
1 is a schematic view of an active layer of a thin film transistor of a top gate structure according to an aspect of the present invention.
Referring to the drawing, the μc-Si active layer is composed of an upper and a lower double layer, the lower layer is an argon atmosphere layer, and the upper layer is a hydrogen atmosphere layer. The hydrogen atmosphere layer is denser than the argon atmosphere layer. Therefore, it is possible to distinguish by observing SEM after etching at Secco etch.
μc-Si refers to microcrystalline Si as described above. The deposition process and equipment of μc-Si is similar to that of a-Si, so it has the advantage that a-Si possesses for LTPS. Therefore, the uniformity is good over a wide area, the cost is low, and the panel size is not limited. In addition, the μc-Si thin film transistor has excellent electron mobility, a large driving current, and excellent stability under bias stress as compared with an a-Si thin film transistor. Furthermore, μc-Si can produce very attractive p-channel thin film transistors in AMOLED technology.
The structure of μc-Si can have various structures from hydrogen-added amorphous structure to polycrystalline structure with different particle sizes depending on the deposition technique employed and deposition conditions thereof. In addition, the volume fraction of the crystalline varies depending on the film thickness.
In the present invention, the μc-Si active layer is composed of upper and lower double layers, the lower layer is formed of an argon atmosphere layer and the upper layer is formed of a hydrogen atmosphere layer, which is based on the following experimental results.
Example
In this embodiment, μc-Si was deposited on a large glass substrate (370 × 400 mm 2) by plasma enhanced chemical vapor deposition (PECVD) at an excitation frequency of 13.56 MHz and a temperature of 330 ° C.
Two different types of μc-Si were deposited, one of which was a mixture of silane and hydrogen (H 2 ) gas at a pressure of 2 Torr, the other type of μc-Si was a silane and a mixture of silane and argon (Ar). For the sake of convenience, the deposited materials are represented by μc-Si (H 2 ) and μc-Si (Ar), respectively. The thicknesses of the μc-Si (H 2 ) film and the μc-Si (Ar) film vary within a range of 20 to 100 nm, respectively.
As shown in FIG. 1, in the present invention, a bilayer structure was developed by sequentially depositing a μc-Si (Ar) layer and a μc-Si (H 2 ) layer.
The thickness of the μc-Si (Ar) layer as the lower layer is preferably 5 nm or more. If the thickness of the lower layer is less than 5 nm, the crystallinity of μc-Si (Ar) is too low to act as a seed layer.
The thickness of the active layer is preferably 100 nm or less. If the thickness of the active layer is too thick, the channel layer becomes thick, which causes a problem of increasing the source-drain current in the OFF state. Therefore, in order to obtain a product having excellent performance, it is preferable that the active layer has a high crystallinity while having a thin thickness of 100 nm or less.
In this embodiment, the thickness of the underlying layer varies within the range of 20 to 60 nm, while the overall thickness of the structure remains constant at 100 nm.
A portion of the film was doped with boron (B) by an ion shower method at an accelerating voltage of 17 keV and a doping ion density of 2 × 10 14 cm -2 . Dopant activation was performed by Rapid Thermal Annealing (RTA) for 1 minute at 650 ° C.
The microstructure of the deposited film was observed by Raman spectroscopy, SEM and high-resolution TEM, and a four-point probe was used to measure the film conductivity.
Experiment result
(1) Structural characteristics of μc-Si (H 2 ) and μc-Si (Ar) single layers
Fig. 2 shows Raman spectra of μc-Si (H 2 ) and μc-Si (Ar) at different film thicknesses. A typical Raman waveform of μc-Si includes two bands. A broad low energy band with a maximum at 480 cm -1 is related to the amorphous fraction and a narrow high energy peak with a center at 520 cm -1 is related to the crystalline fraction. There are several known techniques for dividing Raman spectra into crystalline and amorphous contributions. The most common method is to use three peaks of the tested spectrum. A third peak is located in the range of 500-510 cm -1 , which is related to the silicon grain interface mode or small grain size smaller than 5 nm.
The crystalline volume fraction (C) can be calculated using the following equation.
C = (I 520 + I 510 ) / (I 520 + I 510 +? I 480 ) - (1)
Where I 520 , I 510 , I 480 are the peak values of the band and γ is the cross-sectional ratio for phonon excitation of crystalline silicon and amorphous silicon. The parameter? Depends on the grain size, which changes from about 0.9 to 0.7 when the grain size changes from 5 nm to 15 nm. In this embodiment, the γ value was set at 0.9 for μc-Si (H 2 ) and 0.7 for μc-Si (Ar). According to the equation (1), the crystallinity value of μc-Si (H 2 ) is 39% at a film thickness of 50 nm, but increases to 57% at 100 nm. μc-Si (Ar) has a higher crystallinity value, with crystallinity values of 50% and 68% at 20 nm and 100 nm film thickness, respectively.
The results show very important facts, that in μc-Si (Ar) the amorphous incubation layer is very thin or even absent. Also, the spectrum of μc-Si (Ar) has a narrower width than the spectrum of μc-Si (H 2 ) with FWHM of 8.2 cm -1 and FWHM of 13.1 cm -1 , Indicating that the grain size is larger.
The high resolution TEM data shown in FIG. 3 is consistent with the Raman result. FIG. 3 shows that the structure of μc-Si (Ar) is close to that of polysilicon, whereas that of μc-Si (H 2 ) is separated from each other by a large amorphous structure. The crystal grain sizes obtained from TEM images are 5 to 10 nm for μc-Si (H 2 ) and 15 to 30 nm for μc-Si (Ar).
However, when examined with a High-Angle Annular Dark-Field (HAADF) microscope, there is a significant amount of voids in μc-Si (Ar). 4 shows an HAADF image of μc-Si (Ar). The bright region is the polysilicon portion and the dark region is the void or very low density silicon.
it can not be used as an active layer of a thin film transistor itself due to numerous pores of μc-Si (Ar). However, μc-Si (Ar) can be used as a seed layer capable of improving the crystallinity of the following deposition film because the incubation layer thickness is thin and the grain size is relatively large.
(2) Electric transport characteristics of μc-Si (Ar) / μc-Si (H 2 ) bilayer structure
To evaluate the quality of the bilayer structure, boron (B) was doped into the bilayer and the sheet resistance R S of the bilayer was measured after RTA activation. For comparison, the R s of a single layer of μc-Si (Ar) and μc-Si (H 2 ) were also measured.
To compare films having different thicknesses, R S was again calculated as a conductivity S by the following equation. σ S = 1 / (R S d), where d is the total thickness of the structure.
In the top gate structure thin film transistor, the quality of the upper part of the active layer is very important. For good thin film transistor performance, the channel region near the gate insulating film interface must have a high crystallinity with a low defect density. To this end, the conductivity (σ H ) of the upper μc-Si (H 2 ) layer in the bilayer structure was calculated using the following equation.
σ H = (σ S d - σ Ar d Ar ) / (d - d Ar ) - (2)
Where Ar is the conductivity and d Ar is the thickness of the μc-Si (Ar) layer.
Fig. 5 shows the total conductivity sigma S according to the thickness change of the lower layer μc-Si (Ar) layer and the upper layer conductivity σ H in the bilayer structure.
The μc-Si (H 2 ) single film shows an extreme case where the thickness of the μc-Si (Ar) layer is zero. Conversely, the μc-Si (Ar) single film shows an extreme case in which the thickness of the μc-Si (H 2 ) layer is zero. As shown in Fig. 5, μc-Si (Ar) has lower conductivity than μc-Si (H 2 ) despite its high crystallinity. This is due to the influence of numerous pores and associated defects in μc-Si (Ar).
The structure having a 20 nm thick μc-Si (Ar) layer has a sigma S value larger than that of each of μc-Si (Ar) and μc-Si (H 2 ) single films. Here, if the thickness of μc-Si (Ar) is increased, the influence of μc-Si (Ar) having a high resistance becomes large, so that the value of σ S becomes small. However, as the thickness of the lower μc-Si (Ar) layer becomes smaller, the conductivity σ H of the upper μc-Si (H 2 ) layer gradually increases. The σ H value is about 1.7 times greater than the conductivity of μc-Si (H 2 ) and about 2.5 times greater than the conductivity of μc-Si (Ar).
Therefore, it is preferable that the thickness of the lower layer accounts for 20 to 60% of the total thickness. In this case, the crystallinity of the μc-Si (Ar) layer is 50% or more when the thickness of the μc-Si (Ar) layer as the lower layer is 20% Is 15 to 30 nm.
The increase in the conductivity of μc-Si indicates that the quality of the material is improved. , Μc-Si (Ar) has a very thin layer of incubation, and therefore contain a large amount sufficiently large crystal grains of which can serve as new seed cleaners negotiation in 20㎚ of thickness, μc-Si (H 2) as described above Which facilitates grain formation during deposition. As the thickness of μc-Si (Ar) increases, the crystal and grain size also increase, which substantially improves the upper μc-Si (H 2 ) layer.
Notably, the conductivity of p-type μc-Si is only 7 times less than the conductivity of high-quality laser crystallized polysilicon at the same doping and activation conditions. Furthermore, the σ Ar value of 3.86S used in the calculation of σ H in equation (2) is the value measured in μc-Si (Ar) film of 100 nm thickness. However, the degree of crystallization of μc-Si (Ar) and the resulting conductivity become smaller as the thickness increases. Therefore, the value of? H in FIG. 5 is undervalued.
The thin film transistor according to the present invention is composed of a lower layer which is an argon atmosphere layer and a double layer which is an upper layer which is a hydrogen atmosphere layer and the argon atmosphere layer which is a lower layer has a very thin amorphous incubation layer to reduce the total thickness of the active layer, Drain current of the upper layer due to the increase of the crystallinity of the upper layer due to the larger crystal grain size, thereby improving the mobility of the upper layer in which the channel is formed.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. .
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| US9553197B2 (en) | 2015-05-04 | 2017-01-24 | Samsung Display Co., Ltd. | Thin film transistor and display device including the same |
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| JP2009135277A (en) * | 2007-11-30 | 2009-06-18 | Tokyo Electron Ltd | Film formation method, thin-film transistor, solar battery, and manufacturing apparatus, and display apparatus |
| KR101638977B1 (en) | 2009-11-13 | 2016-07-12 | 삼성전자주식회사 | Transistor, method of manufacturing the same and electronic device comprising transistor |
| KR20220003670A (en) * | 2019-06-04 | 2022-01-10 | 어플라이드 머티어리얼스, 인코포레이티드 | thin film transistor |
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| KR970077745A (en) * | 1996-05-28 | 1997-12-12 | 장진 | Structure and Fabrication Method of Thin Film Transistor Using Chlorine-Containing Amorphous Silicon / Amorphous Silicon Multilayer as Active Layer |
| KR20010003517A (en) * | 1999-06-23 | 2001-01-15 | 구본준 | Thin film transistor and a method for fabricating the same |
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| KR970077745A (en) * | 1996-05-28 | 1997-12-12 | 장진 | Structure and Fabrication Method of Thin Film Transistor Using Chlorine-Containing Amorphous Silicon / Amorphous Silicon Multilayer as Active Layer |
| KR20010003517A (en) * | 1999-06-23 | 2001-01-15 | 구본준 | Thin film transistor and a method for fabricating the same |
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| US9553197B2 (en) | 2015-05-04 | 2017-01-24 | Samsung Display Co., Ltd. | Thin film transistor and display device including the same |
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