KR100731118B1 - Cmos image sensor and method for manufacturing the same - Google Patents

Abstract

A CMOS image sensor and its manufacturing method are provided to reduce chromatic aberration and to improve characteristics of the image sensor by using a double lens structure composed of a convex lens and a concave lens. An interlayer dielectric is formed on a semiconductor substrate(200) having a plurality of photodiodes and a variety of transistors. A concave lens(214) is formed on the interlayer dielectric corresponding to each photodiode. A convex lens(213) is formed on the resultant structure corresponding to the concave lens. A planarization layer is formed on the resultant structure. A color filter layer(216) is formed on the planarization layer corresponding to each photodiode. A microlens(215) is formed on each color filter layer.

Description

CMOS image sensor and method for manufacturing the same

1 is an equivalent circuit diagram of a typical 3T CMOS image sensor

2 is a layout diagram showing unit pixels of a general 3T CMOS image sensor;

3 is a cross-sectional view showing a CMOS image sensor according to the prior art

4 is a cross-sectional view showing a CMOS image sensor according to the present invention

5A to 5I are cross-sectional views illustrating a method of manufacturing the CMOS image sensor according to the present invention.

Explanation of symbols for the main parts of the drawings

200 semiconductor substrate 201 epi layer

202 Device isolation film 203 Gate insulation film

204: gate electrode 205: n ^- type diffusion region

206: sidewall of insulating film 207: high concentration n ⁺ type diffusion region

208: nitride film for blocking diffusion 209: first interlayer insulating film

210: metal wiring 211: second interlayer insulating film

212 silicon nitride film 213 convex lens

214: concave lens 215: first planarization layer

216: color filter layer 217: second planarization layer

215: Micro Lens

The present invention relates to an image sensor and a method of manufacturing the same, and more particularly, to a CMOS image sensor and a method of manufacturing the same to improve the sensitivity of the image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) is an individual metal-oxide-metal (MOS). ) Capacitors are in close proximity to each other and charge carriers are stored and transported in the capacitors. Complementary MOS image sensors use control circuits and signal processing circuits as peripheral circuits. It is a device that employs a switching method of making as many MOS transistors as the number of pixels using CMOS technology and sequentially detecting the output using the same.

CCD has many disadvantages such as complicated driving method, high power consumption, complicated process due to the large number of mask process steps, and difficulty in making one chip because signal processing circuit cannot be implemented in CCD chip. Recently, in order to overcome such drawbacks, the development of CMOS image sensors using sub-micron CMOS manufacturing techniques has been studied.

The CMOS image sensor forms an image by forming a photodiode and a MOS transistor in a unit pixel, and sequentially detects signals by switching method, and realizes images by using CMOS manufacturing technology. Compared to CCD process which requires two masks, the process is very simple, and it is possible to make various signal processing circuits and one-chip, which is attracting attention as the next generation image sensor.

On the other hand, CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors. The layout of the unit pixels of the 3T type CMOS image sensor is as follows.

FIG. 1 is an equivalent circuit diagram of a general 3T CMOS image sensor, and FIG. 2 is a layout diagram illustrating unit pixels of a general 3T CMOS image sensor.

As shown in FIG. 1, a unit pixel of a general 3T CMOS image sensor includes one photodiode (PD) and three nMOS transistors T1, T2, and T3. The cathode of the photodiode PD is connected to the drain of the first nMOS transistor T1 and the gate of the second nMOS transistor T2.

The sources of the first and second nMOS transistors T1 and T2 are all connected to a power supply line supplied with a reference voltage VR, and the gate of the first nMOS transistor T1 has a reset signal RST. It is connected to the reset line supplied.

In addition, the source of the third nMOS transistor T3 is connected to the drain of the second nMOS transistor, and the drain of the third nMOS transistor T3 is connected to a read circuit (not shown in the figure) via a signal line, The gate of the third nMOS transistor T3 is connected to a column select line to which the selection signal SLCT is supplied.

Accordingly, the first nMOS transistor T1 is referred to as a reset transistor Rx, the second nMOS transistor T2 is referred to as a drive transistor Dx, and the third nMOS transistor T3 is referred to as a selection transistor Sx.

As shown in FIG. 2, in the unit pixel of a general 3T CMOS image sensor, an active region 10 is defined so that one photodiode 20 is formed in a wide portion of the active region 10. Gate electrodes 120, 130, and 140 of three transistors that overlap each other in the active region 10 of the remaining portion are formed.

That is, the reset transistor Rx is formed by the gate electrode 120, the drive transistor Dx is formed by the gate electrode 130, and the selection transistor Sx is formed by the gate electrode 140. Is formed.

Here, impurity ions are implanted into the active region 10 of each transistor except for lower portions of the gate electrodes 120, 130, and 140 to form source / drain regions of each transistor.

Therefore, a power supply voltage Vdd is applied to a source / drain region between the reset transistor Rx and the drive transistor Dx, and a source / drain region on one side of the select transistor Sx is shown in a read circuit (not shown). Not used).

Although not illustrated in the drawings, the gate electrodes 120, 130, and 140 described above are connected to respective signal lines, and each of the signal lines has a pad at one end thereof and is connected to an external driving circuit.

3 is a cross-sectional view showing a CMOS image sensor according to the prior art.

As shown in FIG. 3, a p ⁻ type epitaxial layer 101 is grown on a p ⁺⁺ type semiconductor substrate 100 defined as an element isolation region and an active region (photodiode region and transistor region). A field oxide film 102 is formed in the device isolation region of the substrate 100 to separate green, red, and blue light input regions, and an n ⁻ type diffusion region 103 is formed in the photodiode region of the semiconductor substrate 100. do.

Subsequently, gate electrodes 105 are formed in the transistor region of the semiconductor substrate 100 through the gate insulating layer 104, and insulating layer sidewalls 106 are formed on both sides of the gate electrode 105, and the gate electrode is formed. The diffusion barrier film 107 is formed on the entire surface of the semiconductor substrate 100 including the 105.

A first interlayer insulating layer 108 is formed on the diffusion barrier layer 107, and various metal wires 109 are formed on the first interlayer insulating layer 108 at regular intervals.

In addition, a second interlayer insulating film 110 is formed on the entire surface of the semiconductor substrate 100 including the metal wiring 109 to have a thickness of about 4000 GPa, and a silicon nitride film 111 is formed on the second interlayer insulating film 110. The color filter layer 112 of red (R), green (G), and blue (B) is formed on the silicon nitride film 111 to correspond to each of the n ⁻ type diffusion regions 103. Is formed.

In addition, a planarization layer 113 is formed on an entire surface of the semiconductor substrate 100 including the color filter layers 112, and the microlens 114 is formed on the planarization layer 113 to correspond to each of the color filter layers 112. ) Is formed.

Herein, reference numeral 115 denotes a source and drain impurity region of the transistor.

However, the conventional CMOS image sensor has the following problems.

That is, since the color filter of the image sensor has different focal points depending on the wavelengths of the green, blue, and red filters, the transmittance of light incident through the microlenses to the photodiode decreases and the focal length is increased, thereby increasing the resolution of the image sensor. Decreases.

An object of the present invention is to provide a CMOS image sensor and a method of manufacturing the same to improve the sensitivity of the image sensor by correcting the chromatic aberration generated through the color filter to solve the above problems.

CMOS image sensor according to the present invention for achieving the above object is an interlayer insulating film formed on the front surface of a semiconductor substrate formed with a plurality of photodiodes and various transistors, and formed on the interlayer insulating film corresponding to each of the photodiodes A color erasing bi-lens, a planarization layer formed on the front surface of the semiconductor substrate including the chrominance bilens, a color filter layer formed on the planarization layer at regular intervals corresponding to the photodiodes, and on the color filter layers. Characterized in that it comprises a microlens formed.

In addition, the method for manufacturing the CMOS image sensor according to the present invention for achieving the above object comprises the steps of forming a plurality of photodiodes and various transistors having a predetermined interval on the semiconductor substrate, and an interlayer insulating film on the front surface of the semiconductor substrate Forming a planarization double lens on the interlayer insulating layer to correspond to each photodiode, forming a planarization layer on an entire surface of the semiconductor substrate including the chrominance bilens, and forming a planarization layer on the planarization layer. And forming a plurality of color filter layers corresponding to each of the photodiodes, and forming a plurality of microlenses on the color filter layer corresponding to each of the color filter layers.

Hereinafter, a CMOS image sensor and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view showing the CMOS image sensor according to the present invention.

As shown in FIG. 4, a p ⁻ type epitaxial layer 201 is grown on a p ⁺⁺ type semiconductor substrate 200 defined as an element isolation region and an active region (photodiode region and transistor region). An isolation layer 202 is formed in the isolation region of the substrate 200 to separate input regions of green light, red light, and blue light, and an n ⁻ type diffusion region 205 is formed in the photodiode region of the semiconductor substrate 200. Is formed.

Subsequently, gate electrodes 204 are formed in the transistor region of the semiconductor substrate 200 through the gate insulating layer 203, and insulating layer sidewalls 206 are formed on both sides of the gate electrode 204. A diffusion barrier nitride film 208 is formed over the entire surface of the semiconductor substrate 200 including the 204.

A first interlayer insulating film 209 is formed on the diffusion barrier nitride film 208, and various metal wires 210 are formed on the first interlayer insulating film 209 at regular intervals.

In addition, a second interlayer insulating film 211 and a silicon nitride film 212 are sequentially formed on the entire surface of the semiconductor substrate 200 including the metal wiring 210, and correspond to the n ⁻ type diffusion regions 205. The concave lens 213 and the convex lens 214 are formed on the silicon nitride film 212.

In addition, a first planarization layer 215 is formed on the entire surface of the semiconductor substrate 200 including the concave lens 213 and the convex lens 214, and each n ⁻ type is formed on the first planarization layer 215. The color filter layers 216 of R, G, and B are formed to correspond to the diffusion region 205, and the second planarization layer 217 is formed on the entire surface of the semiconductor substrate 200 including the color filter layers 216.

In addition, a microlens 218 is formed on the second planarization layer 217 to correspond to each of the color filter layers 216.

Here, reference numeral 207, which is not described, denotes source and drain impurity regions of the transistor.

5A to 5I are cross-sectional views illustrating a method of manufacturing the CMOS image sensor according to the present invention.

As shown in FIG. 5A, a low concentration first conductivity type (P ⁻ type) epi layer 201 is formed in an epitaxial process on a semiconductor substrate 200 such as a high concentration first conductivity type (P ⁺⁺ type) polycrystalline silicon. ).

In this case, the epitaxial layer 201 increases and decreases the ability of the low voltage photodiode to collect photo charges by forming a large and deep depletion region in the photodiode and further improves the optical sensitivity.

In addition, the semiconductor substrate 200 defines a photodiode region, a transistor region, and an isolation region, and forms an isolation layer 202 in the isolation region using an STI process or a LOCOS process.

 Thereafter, a gate insulating film 203 and a conductive layer (for example, a high concentration polycrystalline silicon layer) are sequentially deposited on the entire epitaxial layer 201 where the device isolation film 202 is formed, and optionally the conductive layer and the gate insulating film are deposited. It removes and forms the gate electrode 204 of each transistor.

The gate insulating layer 203 may be formed by a thermal oxidation process or a CVD method, and a silicide layer may be further formed on the conductive layer to form a gate electrode.

Meanwhile, a thermal oxidation process may be performed on the surfaces of the gate electrode 204 and the semiconductor substrate 200 to form a thermal oxide film (not shown).

In addition, the width of the gate electrode 204 may be larger than the width of the conventional gate electrode to reflect an increase in the thickness of the thermal oxide film.

Next, a low concentration second conductivity type (n ⁻ -type) impurity ion is implanted into the photodiode region of the semiconductor substrate 200 to form an n ⁻ type diffusion region 205.

Subsequently, an insulating film is formed on the entire surface of the semiconductor substrate 200 and then etched back to form insulating film sidewalls 206 on both sides of the gate electrode 204.

In addition, a high concentration n ⁺ type diffusion region 207 is formed by implanting a high concentration of second conductivity type (n ⁺ type) impurity ions into the transistor region of the semiconductor substrate 200.

As shown in FIG. 5B, an impurity in the n ⁻ type diffusion region 205 and the high concentration n ⁺ type diffusion region 207 is formed by performing a heat treatment process (eg, a rapid heat treatment process) on the semiconductor substrate 200. Diffusion of ions.

Meanwhile, before forming the high concentration n ⁺ type diffusion region 207, an n ⁻ type diffusion region (not shown) may be formed in the transistor region through ion implantation energy lower than the n ⁻ type diffusion region 205. have.

Next, a nitride film 208 for blocking diffusion is formed on the entire surface of the semiconductor substrate 200.

As shown in FIG. 5C, the first interlayer insulating film 209 is formed on the entire surface of the semiconductor substrate 200 including the diffusion preventing nitride film 208.

Here, the first interlayer insulating film 209 may be formed of an xylene-based insulating film, and the dark current may be effectively reduced by restoring the danglin bond of the semiconductor substrate 200 due to the large amount of hydrogen ions contained therein.

Subsequently, a metal film is deposited on the first interlayer insulating film 209, and the metal film is selectively etched through a photo and etching process to form various metal wires 210.

As shown in FIG. 5D, the second interlayer insulating film 211 is formed on the entire surface of the semiconductor substrate 200 including the metal wiring 210 to have a thickness of 3000 to 4000 kPa.

Here, the second interlayer insulating film 211 uses any one of USG (Undoped Silicate Glass), PSG, BSG, BPSG.

Meanwhile, a thickness of the second interlayer insulating layer 211 may be reduced by performing a chemical mechanical polishing (CMP) process on the entire surface of the second interlayer insulating layer 211.

As shown in FIG. 5E, a silicon nitride (SiN) film 212 having a thickness of 2000 to 3000 Å is formed on the second interlayer insulating film 211.

Subsequently, M6 sinter is performed on the entire surface of the silicon nitride film 212. At this time, the hydrogen (H) contained in the silicon nitride film 212 is diffused by the M6 sintering process to perform damage curing.

Meanwhile, a CMP process may be applied to the entire surface of the silicon nitride film 212 to reduce the thickness of the silicon nitride film 212 by polishing a predetermined thickness from the surface.

As shown in FIG. 5F, a concave lens 213 is formed on the silicon nitride film 212 so as to correspond to each of the n ⁻ type diffusion regions 205.

As shown in FIG. 5G, a convex lens 214 is formed on the concave lens 213 to correspond to the concave lens 213. The convex lens 214 is formed to correspond to the concave lens 213. In detail, the convex lens 214 may be formed independently on the concave portion to correspond to the concave portion of the concave lens 213.

As shown in FIG. 5H, a first planarization layer 215 is formed on the entire surface of the semiconductor substrate 200 including the convex lenses 214, and each convex lens is formed on the first planarization layer 215. Corresponding to 214, the color filter layer 216 of red (R), blue (B), and green (G) is formed.

Here, each color filter layer 216 is coated on the first planarization layer 215 by using a salt resist, and then subjected to exposure and development to form color filter layers for filtering light for each wavelength band. .

In addition, each color filter layer 216 is coated with a photosensitive material to have a thickness of 1 ~ 5㎛ and patterned by a photolithography process using a separate mask to form a color filter layer for filtering light for each wavelength band as a single layer do.

As shown in FIG. 5I, a second planarization layer 217 is formed on the entire surface of the semiconductor substrate 200 including the color filter layers 216.

In this case, the planarization layer 217 is formed on the front surface of the semiconductor substrate 200 including the color filter layers 216. It is formed by depositing a nitride film.

Meanwhile, a CMP or etch back process may be performed on the entire surface of the second planarization layer 217 to reduce the thickness from the upper surface by a predetermined thickness.

On the other hand, since the optical transmission is very important, the image sensor is formed to a thickness of 1000 ~ 6000Å in order to exclude the interference phenomenon of the thin film due to the thickness of the second planarization layer 217.

Next, a microlens photoresist is coated on the entire surface of the semiconductor substrate 200 including the second planarization layer 217 in order to focus light efficiently on the n ⁻ type diffusion region 205.

Subsequently, the photoresist is selectively patterned by an exposure and development process to form a microlens pattern.

In the case where the photoresist is a positive resist, the microlens may be exposed to a front exposure because the transmittance is improved only when the photo active compound of the initiator, which is an absorber of the photoresist, is decomposed. Decompose the remaining photo active compound in the pattern.

On the other hand, through the front exposure to the microlens pattern as described above to increase the transmittance and generate a photo acid (photo acid) to increase the flow (flow ability) of the microlens.

The semiconductor substrate 200 having the microlens pattern formed thereon is heat-treated at a temperature of 300 to 700 ° C. in a state where the microlens pattern is formed on a hot plate (not shown). Lens 218 is formed.

Subsequently, the microlens 218 reflowed by the heat treatment is cooled. Here, the cooling process is performed in a state where the semiconductor substrate 200 is placed on a cool plate.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the method for manufacturing the CMOS image sensor according to the present invention has the following effects.

In other words, before forming the color filter, by forming the chrominance double lens consisting of convex and concave lenses, it is possible to prevent the spot where the light is differently focused according to the wavelength generated after passing the color filter, thereby reducing the amount of chromatic aberration. The sensitivity characteristic of the sensor can be improved.

Claims (5)

An interlayer insulating film formed on the front surface of the semiconductor substrate on which a plurality of photodiodes and various transistors are formed; A concave lens formed on the interlayer insulating layer so as to correspond to each of the photodiodes; A convex lens formed to correspond to the concave lens; A planarization layer formed on an entire surface of the semiconductor substrate including the convex lens; A color filter layer formed at regular intervals on the planarization layer to correspond to each photodiode; CMOS image sensor comprising a microlens formed on each of the color filter layers. delete The method of claim 1, The convex lens is The CMOS image sensor, characterized in that both the upper surface and the lower surface is formed independently on the concave lens in a convex form. Forming a plurality of photodiodes and various transistors at regular intervals on the semiconductor substrate; Forming an interlayer insulating film on the entire surface of the semiconductor substrate; Forming a concave lens on the interlayer insulating layer to correspond to each of the photodiodes; Forming a convex lens to correspond to the concave lens; Forming a planarization layer on an entire surface of the semiconductor substrate including the convex lens; Forming a plurality of color filter layers on the planarization layer to correspond to each of the photodiodes, respectively; And forming a plurality of microlenses on the color filter layer corresponding to each of the color filter layers. The method of claim 4, wherein The convex lens is A method for manufacturing a CMOS image sensor, characterized in that the upper surface and the lower surface are both convexly formed on the concave lens independently.

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