KR100724254B1 - Image sensor - Google Patents

Abstract

The present invention provides an image sensor capable of varying a driving current of a pixel. To this end, the present invention provides a unit pixel including a photodiode and a plurality of transistors, and a buffer amplifier to read an output of the unit pixel. A correlated double sampling circuit and a first transistor operating as the buffer amplifier to increase and output a gate voltage of the first transistor above a saturation voltage in order to operate in a saturation region even if any signal is input within an operating range. And a correction circuit comprising a current mirror, wherein the current mirror includes: a variable resistor unit for variably controlling an amount of current flowing from a power source voltage source; a second transistor connected between the variable resistor unit and a ground voltage source to operate as a diode; Contacting the gate terminal of the first transistor A third transistor connected between the connected node and a second current source connected to a ground voltage source, and having a gate terminal connected to the gate terminal of the second transistor and operating according to a voltage applied to the gate terminal of the second transistor. The present invention provides an image sensor that includes an image sensor, thereby changing pixel driving current by simply changing a layout through a wiring process, thereby improving distribution of dead zone deviation (DZD) and dark bad pixel (DBP).

CMOS image sensor, correlated double sampling circuit (CDS), buffer amplifier, saturation region, current mirror, variable resistor, DZD, DBP

Description

Image sensor {IMAGE SENSOR}

1 is a circuit diagram illustrating a CMOS image sensor according to the prior art.

2 is a circuit diagram illustrating another CMOS image sensor according to the prior art.

3 is a circuit diagram illustrating another CMOS image sensor according to the prior art.

4 is a view for comparing the signal setting time of the CMOS image sensor according to the prior art shown in FIG. 2 and FIG.

5 and 6 are diagrams for explaining the Dead Zone Deviation (DZD) distribution in the CMOS image sensor according to the prior art.

7 is a circuit diagram illustrating a CMOS image sensor according to an embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a CMOS image sensor according to an example of the variable resistor unit illustrated in FIG. 7.

9 is a circuit diagram illustrating a CMOS image sensor according to another example of the variable resistor unit illustrated in FIG. 7.

10 to 12 are diagrams for explaining the effect of the CMOS image sensor according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: unit pixel

20: correlated double sampling circuit

30, 132: current source

40: clamp circuit

130. 230: Current mirror

CDS: Correlated Double Sampling Circuit

231: variable resistor

TECHNICAL FIELD The present invention relates to semiconductor design technology, and more particularly, to design technology of an image sensor.

Recently, the demand of digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

The camera module basically includes an image sensor. In general, an image sensor refers to a device that converts an optical image into an electrical signal. As such an image sensor, a charge coupled device (hereinafter referred to as a CCD) and a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor are widely used.

CCD has a complicated driving method, high power consumption, complicated process due to the large number of mask processes in the manufacturing process, and it is difficult to realize a signal processing circuit in a chip, making it difficult to make one chip. There are disadvantages. In contrast, CMOS image sensors are receiving more attention recently because of the monolithic integration of control, drive, and signal processing circuitry on a single chip. In addition, CMOS image sensors offer potentially lower cost than conventional CCDs due to low voltage operation and low power consumption, compatibility with peripherals, and the availability of standard CMOS fabrication processes.

However, analog signals generated by light receiving elements, such as photo diodes, in CMOS image sensors have various parasitic effects caused by parasitic capacitance, resistance, dark current leakage, or mismatch of semiconductor device characteristics. Such a parasitic effect is essentially generated in a semiconductor device, resulting in a decrease in the signal to noise ratio of the image data. Therefore, noise is an important factor that limits the performance of CMOS image sensors.

Noise in the CMOS image sensor is caused by kT / C noise related to the sampling of the image data, 1 / f noise associated with the circuit used to amplify the image signal, and fixed by the mismatch of the signal processing circuit of the sensor. Patterned Pattern Noise (hereinafter referred to as FPN). Dual FPNs are not very good visually because they appear as vertical lines or strips in the image and are easily found in the human eye.

Recently, a Correlate Double Sampling circuit (hereinafter referred to as CDS) has been used in a read out circuit to remove such FPN.

1 and 2 are diagrams illustrating unit pixels and CDSs in a general CMOS image sensor. Here, as an example, a unit pixel having a 4-T (4-Transistor) structure will be described.

1 and 2, the unit pixel 10 includes one photodiode PD and four NMOS transistors M1 to M3. The four NMOS transistors M1 to M4 are transfer transistors (Tx) for transporting photo-generated charges concentrated in the photodiode PD to the floating diffusion region (FD), Accumulate in the reset transistor (Rx) and the floating diffusion region (FD) for setting the potential of the floating diffusion region FD to a desired value and discharging the electric charge to reset the floating diffusion region FD. A drive transistor (Dx) configured as a source follower to operate according to a charged charge and serving as a buffer amplifier, and a select transistor configured to allow addressing through switching; Sx). A plurality of such unit pixels 10 are arranged in a matrix to form pixel units.

The CDS 20 is provided one per column line of the pixel unit to read and process an analog signal output from the plurality of unit pixels connected to one column line to the column line. The CDS resets the floating diffusion region FD to the power supply voltage VDD by the reset transistor Rx that is turned on by the reset signal RST during the reset readout period. Electrons are emitted by a signal having a level corresponding to the potential of the diffusion region FD (hereinafter referred to as a reset voltage) and light irradiated to the photodiode PD during the signal detection section after the reset readout section. And holes are formed, and predetermined circuits for reading and sampling signals (hereinafter, referred to as image signal voltages) outputted to the column line CL having a level corresponding to the accumulation of electrons are configured.

This CDS 20 usually includes a PMOS transistor PM that functions as a buffer amplifier. A gate is connected to a node connected to the source terminal of the select transistor Sx to amplify and output the reset voltage and the image signal voltage output through the select transistor Sx.

On the other hand, when the difference between the reset voltage and the image signal voltage increases, fixed pattern noise (FPN) is generated on the screen. In the dark, the reset voltage is not a big problem because the difference between the image signal voltage is small, but in the very bright place, the difference between the reset voltage and the image signal voltage becomes large, so that the PMOS transistor PM does not operate in the saturation region, and the triode It will work in the area. Accordingly, the setting time of the video signal voltage is delayed, which may cause a fixed pattern noise.

In order to solve this problem, a CMOS image sensor includes a correction circuit. An example of such a correction circuit is illustrated in FIGS. 1 and 2. In FIG. 1, a current source 30 is provided as a correction circuit, and in FIG. 2, a clamp circuit 40 is provided.

First, as shown in FIG. 1, operation characteristics of a CMOS image sensor having a current source 30 are described as follows. Although the voltage is ideally '0' for the current source 30 connected to the node, the Von voltage is actually applied as a current mirror. This Von voltage eventually becomes the gate voltage of the PMOS transistor PM. If the Von voltage is too low, the saturation region of the PMOS transistor PM, i.e., the operating condition as shown in Equation 1 below, may enter the triode region. Fixed pattern noise is generated.

Vsd ≥ Vsg-| Vth | PMOS transistor PM operates in saturation region

Vsd ≤ Vsg-| Vth | PMOS transistor PM operates in triode region

In Equation 1, Vsd is a source-drain voltage of the PMOS transistor PM, Vsg is a source-gate voltage, and Vth represents a threshold voltage.

Meanwhile, as shown in FIG. 2, operation characteristics of the CM0S image sensor having the clamp circuit 40 are described as follows. The clamp circuit 40 connects the NMOS transistor NM between the power supply voltage terminal VDD and the node to maintain the potential of the node at a constant voltage. The NMOS transistor NM is turned on / off according to the voltage difference between the source and the drain. However, when the clamp circuit 40 is used, data of the image signal voltage may be lost, and noise of the power supply voltage terminal VDD and the transistor NM may be transmitted together with the signal. In addition, when the clamp signal is varied, it is difficult to control the current. In this case, the current may be significantly different from the current value set in the circuit design, thereby causing a problem in which the circuit does not operate normally and malfunctions.

Accordingly, recently, as shown in FIG. 3, a correction circuit for controlling a transistor operating as a buffer amplifier in a correlated double sampling circuit among analog circuits of the CMOS image sensor to operate in a saturation region under any input condition has been proposed.

Referring to FIG. 3, a correction circuit according to the related art includes a PMOS transistor (a PMOS transistor) in a dual correlation sampling circuit (CDS) including a PMOS transistor (PM) that operates as a buffer amplifier to amplify and output an analog signal output from a unit pixel. The PM) is formed of a current mirror 130 that maintains the gate voltage of the PMOS transistor PM above a predetermined voltage so as to operate in the saturation region regardless of which input is input within the operating range.

The current mirror 130 is connected to the first and second current sources 131 and 132, the first current source 131, and the ground so that the gate-source voltage of the PMOS transistor PM is always operated at 2 Von, which is the minimum saturation voltage. An NMOS transistor NM1 connected between a voltage source VSS and operating as a diode, a node connected to a gate terminal of the PMOS transistor PM, and a second current source 132 connected to a gate terminal The NMOS transistor NM2 is connected to the gate terminal of the NMOS transistor NM1 and operates according to the gate voltage of the NMOS transistor NM1.

In the correction circuit 130, it is possible to increase the node voltage to 2Von, thereby allowing the PMOS transistor PM connected to the node to be always operated in the saturation region. As a result, as shown in Figure 4, it can be seen that the setting time is significantly reduced when the correction circuit is applied. Here, 'A' is a waveform when the correction circuit shown in FIG. 3 is applied, and 'B' is a waveform when the correction circuit shown in FIG. 1 or 2 is applied.

However, in the correction circuit 130 according to the related art, when the current Ia flowing through the current source 131 is fixed, the drive transistor Dx, the select transistor Sx, and the NMOS transistor NM2 serving as the load transistor, respectively, are fixed. Since the currents Ib, Ic, and Id are all fixed, the pixel driving current cannot be adjusted. This will be described with reference to FIGS. 5 and 6.

5 and 6 are waveform diagrams showing Dead Zone Deviation (DZD) distributions according to high and low Ia. 5 is a waveform diagram showing a DZD distribution when 'Ia' is high, and FIG. 6 is a waveform diagram showing a DZD distribution when 'Ia' is low. In the case of FIG. 5, the DZD decreases because the pixel driving current is sufficient, and the DZD decreases even more because the pixel driving current is not sufficient when 'Ia' is low.

As described above, in the correction circuit according to the related art, when the value of 'Ia' is fixed, it is difficult to properly control the driving current of the pixel according to the environment, so that it is difficult to control the DZD and DBP distribution, which results in low light characteristics and noise in low light. An increasing problem arises.

Accordingly, an object of the present invention is to provide an image sensor capable of varying a driving current of a pixel, which is devised to solve the above-described problems of the prior art.

According to an aspect of the present invention, there is provided a unit pixel including a photodiode and a plurality of transistors, a correlated double sampling circuit including a buffer amplifier to read an output of the unit pixel, and the buffer. The first transistor, which operates as an amplifier, includes a correction circuit including a current mirror that raises and outputs the gate voltage of the first transistor above the saturation voltage in order to operate in the saturation region regardless of which signal is input within the operating range. The current mirror may include a variable resistor unit for variably controlling an amount of current flowing from a power source voltage source, a second transistor connected between the variable resistor unit and a ground voltage source to operate as a diode, and connected to a gate terminal of the first transistor. A second current source connected to the node and the ground voltage source Is connected to the gate terminal is connected to the gate end of the second transistor, it provides an image sensor including a third transistor, which operates in accordance with the voltage applied to the gate terminal of the second transistor.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals throughout the specification represent the same elements performing the same function.

Example

7 is a circuit diagram illustrating a correction circuit of an image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 7, the correction circuit according to the embodiment of the present invention changes the resistance by changing the resistance instead of the current source 131 constituting the current mirror 130 in the correction circuit according to the related art shown in FIG. 3. A variable resistor unit 231 can be selectively controlled.

The variable resistor unit 231 may be implemented in various examples as illustrated in FIGS. 8 and 9.

First, as shown in FIG. 8, the variable resistor unit 231 has a structure in which a plurality of resistors R1 to R3 are connected in series between the power supply voltage source VDD and the NMOS transistor NM1. Each of the resistors R1 to R3 is formed during the device manufacturing process, and any one of the nodes 1 to 3 is selectively connected to the drain terminal of the NMOS transistor NM1 during the metal wiring process. That is, the resistance value is controlled by changing the mask process in the metallization process and selecting the resistance variably.

In addition, as shown in FIG. 9, the variable resistor unit 231 may be implemented using a transistor, which is an active device, instead of the resistors R1 to R3, which are passive devices. For example, NMOS transistors NM3 to NM5 may be implemented. In this case, the widths (W) of the transistors are formed differently in order to change the respective resistance values. One of the nodes ① to ③ is selectively connected to the drain terminal of the NMOS transistor NM1 during the metal wiring process. In addition, as shown in FIG. 8, the mask value is changed during the metallization process to control the resistance value.

The current according to the connection relationship between the NMOS transistors NM3 to NM5 shown in FIG. 9 will be described below.

Referring to FIG. 9, when only the node ① is connected to the drain terminal of the NMOS transistor NM1, the current flowing through the drain terminal of the NMOS transistor NM1 is referred to as 'Idtot1', and the nodes ① and ② are connected to the NMOS transistor NM1. If the current flowing when connected to the drain terminal of the () is called 'Idtot2', if the current flowing when the node (①, ②, ③) is connected to the drain terminal of the NMOS transistor (NM1) 'Idtot3', each current value is It can be expressed as Equation 2.

Idtot1 = Idsat × W

Idtot2 = Idsat × 2W

Idtot3 = Idsat × 3 W

On the other hand, the resistance variable unit 231 according to the embodiment of the present invention described above can easily control the connection relationship through the wiring process, such as metal wiring and contact plug (contact plug).

Therefore, irrespective of the resistance elements or transistor elements shown in FIGS. 8 and 9, the number of the NMOS transistor NM1 may be controlled by increasing the number within the allowable space and controlling the connection accordingly through a wiring process if necessary. Current can be controlled.

On the other hand, 'A, B' in Figs. 8 and 9 shows a part that can control the connection state through the wiring process.

Hereinafter, the effects obtained through the correction circuit according to the embodiment of the present invention will be described.

First, the pixel driving current can be changed by simply changing the layout through the wiring process. That is, the pixel driving current can be changed by freely controlling the resistance value through the wiring process.

Second, by increasing the pixel driving current, the DZD distribution (ie, noise) may be improved as shown in FIG. 12.

Third, as shown in FIG. 10, the DBP distribution may be improved by improving the DZD distribution.

Fourth, it is possible to reduce the dead zone (DZ) as shown in FIG. 11 by improving the DZD distribution.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, the pixel driving current can be changed by simply changing the layout through the wiring process. That is, the pixel driving current can be changed by freely controlling the resistance value through the wiring process.

Second, by increasing the pixel driving current, the DZD distribution (ie, noise) may be improved as shown in FIG. 12.

Third, as shown in FIG. 10, the DBP distribution may be improved by improving the DZD distribution.

Fourth, it is possible to reduce the dead zone (DZ) as shown in FIG. 11 by improving the DZD distribution.

Claims (6)

A unit pixel including a photo diode and a plurality of transistors; A correlated double sampling circuit comprising a buffer amplifier for reading the output of the unit pixel; And The first transistor, which operates as the buffer amplifier, includes a correction circuit including a current mirror that raises and outputs the gate voltage of the first transistor above the saturation voltage in order to operate in the saturation region even if any signal is input within the operating range. But The current mirror, A variable resistor unit for variably controlling the amount of current flowing from the power source voltage source; A second transistor connected between the variable resistor unit and a ground voltage source to operate as a diode; And A node connected to a gate terminal of the first transistor and a second current source connected to a ground voltage source, the gate terminal being connected to a gate terminal of the second transistor, and according to a voltage applied to the gate terminal of the second transistor. Third transistor in operation Image sensor comprising a. The method of claim 1, The variable resistor unit includes a plurality of resistor elements connected in series, and includes a metal line to select any one of the resistor elements and to connect with the drain terminal of the second transistor. The method of claim 1, The variable resistor unit includes a plurality of fourth transistors connected in parallel, and a metal line configured to select at least one of the plurality of fourth transistors and to connect the drain terminal of the second transistor. The method of claim 3, wherein And the fourth transistors are formed to have different widths. The method of claim 4, wherein The second to fourth transistors are NMOS transistors. The method of claim 5, And the first transistor is a PMOS transistor.

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