KR100723831B1 - Method and storage media for scheduling hardwares and softwares in system-on-chip design - Google Patents

Abstract

A hardware / software scheduling method for system on chip design and a recording medium for realizing this function are disclosed. In the SOC scheduling method, a priority graph and a constraint graph are generated from operating clock cycles of hardware / software modules, operating priorities and system structure information between modules, and a system-wide operating clock cycle and pipeline on a given system structure. Generates a schedule result for the operating time of each module satisfying the number. In addition, if the operating clock cycle of the entire system is not satisfied, the optimum number of pipelines and corresponding schedule results are generated.

Description

Hardware and Software Scheduling Method for System-on-Chip Design and Recording Media Implementing This Function {Method and storage media for scheduling hardwares and softwares in system-on-chip design}

1 is a conceptual diagram of a hardware / software scheduler according to an embodiment of the present invention.

2 is a flowchart illustrating an operation of a hardware / software scheduler according to an embodiment of the present invention.

3 is a block diagram showing an example of one system designed with SOC.

4 is an example of representing system structure information for the system of FIG. 3.

<Description of Major Symbols in Drawing>

110: hardware / software operation clock cycle

120: total number of operating cycles and pipelines

130: Hardware / Software Action Priority

140: system structure information

160: Scheduler

170: Hardware / Software Schedule

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system-on-chip (SOC), and more particularly, to a scheduling method to be referred to in order to be able to estimate the performance of a SOC system to be designed in advance, and to easily write a program to control the system. A recording medium for realizing this function.

In general, a system designed with an SOC has a number of circuit modules that perform a series of iterative processes on a given input data. That is, each hardware module and software module included in the system processes the given input data and passes it as input to other hardware or software modules. When these series of operations are completed on each hardware module and software module, the desired system output is obtained. do.

In order to achieve the desired performance of such an SOC system, a core control program executed by a processor included in the system must be appropriately written in consideration of operating time of hardware and software modules. In order to support this, scheduling has conventionally been made regarding a schedule task. For example, there are software tasks handled by a computer's processor, hardwired tasks around the processor, or tasks relating to data processing in a network.

However, since most systems are being developed based on the type of SOC today, the performance of the SOC system to be designed is estimated in advance based on the scheduling related to the operating time of the hardware and software modules in the overall system to be designed. There is a demand for a program to easily control a system.

Accordingly, the present invention has been made to solve the above problems, and the technical problem to be achieved by the present invention is to satisfy the performance given in the SOC system structure to be designed, various hardware modules and software included in the system The present invention provides a scheduling method for generating a schedule result related to control of operating time of modules and a recording medium for realizing this function.

SOC scheduling method according to the present invention for achieving the above technical problem, the operating clock cycle of hardware / software modules included in the SOC system, the operation priority of each module, the system structure, the operating clock cycle and the number of pipelines of the entire system Receiving information related to; Generating a priority graph of each of the hardware / software modules as a node and an edge of each module as an edge from the operational priority of each module; Generating a constraint graph from the priority graph by reflecting an operation clock cycle of each module to the edge; Reflecting the system structure information in the constraint graph; And generating a schedule result for the operation time of each module satisfying the operation clock cycle and the pipeline number of the entire system with respect to the given system structure information.

The SOC scheduling method may further include generating an optimal number of pipelines that can be satisfied and a corresponding schedule result when the operating clock cycle of the entire system is not satisfied with respect to the number of pipelines. do.

The system structure information may include tasks to be executed in each module and a corresponding operation clock cycle.

The schedule result may include data throughput of the entire system corresponding to the given pipeline number, or include corresponding results for each of at least two or more pipelines over the given pipeline number. .

The recording medium for the scheduler function of the SOC system in which the computer-readable and executable code is recorded according to the present invention for achieving the above another technical problem, the operation clock cycle of the hardware / software modules included in the SOC system, each Receiving information on an operation priority of a module, a system structure, an operation clock cycle and a pipeline number of the entire system; Generating a priority graph of each of the hardware / software modules as a node and an edge of each module as an edge from the operational priority of each module; Generating a constraint graph from the priority graph by reflecting an operation clock cycle of each module to the edge; Reflecting the system structure information in the constraint graph; And generating a schedule result for an operation time of each module satisfying the operation clock cycle and the number of pipelines of the entire system with respect to the given system structure information.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

In general, a system designed as an SOC includes various hardware modules and software modules, and each module performs an iterative series of operations on a given input data to complete a required operation, thereby obtaining a system output.

In this case, the hardware modules may operate independently and simultaneously, or each hardware module may operate in a pipelined structure depending on the system implementation. However, since there is generally one processor that processes software modules and controls the hardware modules, the processor is a system. In order to achieve this required performance, the operating time of each hardware module and software module should be controlled. For this purpose, the control program for operating the processor should control the operation in the proper order in consideration of the operation cycle of each hardware and software module and the operation priority of each module.

Each hardware module and software module included in an SOC system is designed to satisfy an interdependent data processing order in a given system structure. In the present invention, in the design of such an SOC system, a scheduling method that can be referred to in order to estimate the performance of the SOC system to be designed in advance and to easily prepare a program for controlling the system accordingly. In the SOC system scheduling, hardware modules that are not data dependent may be executed independently and simultaneously, and hardware modules operating in a pipelined structure may be scheduled to perform corresponding pipeline operations within a given number of pipelines. In addition, when a given total operation cannot be completed within a given number of pipelines, the number of pipelines and a schedule corresponding thereto are generated. In this case, when the number of pipelines is 1, it means that the modules do not substantially correspond to the pipeline structure and each module processes them in a sequential operation.

To this end, a conceptual diagram 100 of the hardware / software scheduler 160 in accordance with one embodiment of the present invention is shown in FIG. 1. Referring to FIG. 1, the scheduler 160 includes operation clock cycle information 110 of hardware / software modules included in an SOC system, operation priority information 130 of each module, system structure information 140, and the entire system. The operation clock cycle and pipeline number information 120 is inputted to generate a schedule result 170 for the operation time of each module. Reference is made to the flowchart of FIG. 2 to describe the operation of the scheduler 160.

First, the scheduler 160 is a priority graph in which each hardware / software module is a node and an dependency relationship of each module is an edge from an operation priority of each input module. To generate (S210 of FIG. 2). Assuming that the SOC system 300 as shown in FIG. 3 is designed, the processor 310, the program memory 320, the hardware data memory 330, the direct memory access controller (DMAC) 340, Each of the first hardware module 350 and the second hardware module 360 may be a node V, and a priority graph G (V, E) having edge E as an element may be generated.

Next, the scheduler 160 generates the constraint graph from the priority graph by reflecting the input operation clock cycle of each module to the edge (S220 of FIG. 2). In the example of FIG. 3, the operating clock cycle of each of the processor 310, the program memory 320, the hardware data memory 330, the DMAC 340, the first hardware module 350 and the second hardware module 360 is When reflected at the edge indicating the inter-module dependency, the operating time between each module to satisfy the operating clock cycle can be estimated approximately.

Next, the scheduler 160 reflects the received system structure information in the constraint graph (S230 of FIG. 2). The input system structure information includes detailed tasks to be executed in each module. In addition, an operation clock cycle of each task may be included.

A constraint graph 400 reflecting system structure information for the system of FIG. 3 is shown in FIG. 4. Referring to the constraint graph 400, the tasks performed by the system of FIG. 3 are controlled by the software module (processor) 410, DMAC set-up 420, hardware setup 430, and DMA transfer. 440, and operation 450 of the hardware module. For example, a constraint graph C (V, E) may be made of a vertex T representing tasks such as the graph of FIG. 4 and an edge R reflecting the constraint. In Figure 4, it means that the operation connected to the edge can not be performed at the same time. The control 410 of the software module is an operation in which the processor 310 executes a program in the program memory 320. The processor 310 may perform a DMAC setup 420 instructing the operation of the DMAC 340, and may perform a hardware setup 430 instructing the operation of the first hardware module 350 and the second hardware module 360. Can be. The DMAC 340 receives a command from the processor 310 and performs a data transfer between the hardware data memory 330 and the first hardware module 350 and the second hardware module 360. In charge of. The first hardware module 350 and the second hardware module 360 are responsible for an operation 450 of a hardware module that performs a given operation by using data received from the hardware data memory 330.

As such, when system structure information is reflected in the constraint graph, the scheduler 160 performs an initial scheduling to satisfy the constraint graph without considering the input pipeline number or the operating clock cycle of the entire system ( S240 of FIG. 2). For example, in this initial scheduling, a method of scheduling hardware and software modules based on the earliest possible execution time, a method of scheduling hardware and software modules based on the latest possible execution time, or a combination thereof Is possible.

Lastly, the scheduler 160 performs a final scheduling based on the initial scheduling result and modifies the system to satisfy it by considering the number of operating clock cycles and pipelines of the entire system (S250 of FIG. 2). Accordingly, the scheduler 160 generates a schedule result for the operation time of each module. For example, in this final scheduling, the list of hardware and software modules to be executed first is scheduled, and then the schedule of repeating the scheduling of the most advantageous hardware or software module first is compared by comparing various conditions of each module. scheduling) may be used.

At this time, the scheduler 160 generates an optimal number of pipelines and corresponding schedule results when the operating clock cycle of the entire system is not satisfied with respect to the number of pipelines. Determining the optimal number of pipelines in this final scheduling step finds a hardware module with an operating clock cycle greater than the system operating clock cycle in the current scheduling results, and then converts the operating clock cycle (absolute cycle) of this hardware module into an overall system operation. The quotient divided by the clock cycle is the number of pipelines. The quotient is taken as the starting position (pipeline cycle) in the pipeline by taking the remaining values and then satisfying the constraint graph. This process repeats until all hardware modules satisfy the constraint graph and the pipeline cycle values are satisfied within the given operating system clock cycle.

As such, the scheduler 160 outputs a schedule result for the operation time of each module corresponding to the operating clock cycle and the number of pipelines of the entire system, and thus the data throughput of the entire system corresponding to the input pipeline number. It may include. For example, in a data compression system, such is the frame rate of an encoder that processes a given macroblock. In addition, the scheduler 160 sets the input pipeline number as the minimum pipeline, estimates the scheduling having a larger pipeline number, and generates a corresponding schedule result for each of the corresponding pipelines. have. For example, in the above encoder example, when the pipeline number is input as 4, it is possible to generate a schedule result regarding the operation time and frame rate of each module for all cases where the pipeline number is 4, 5, 6, and so on. have.

The functions used in the methods disclosed herein can be embodied as computer readable codes on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

As described above, in the SOC scheduling method according to an embodiment of the present invention, a priority graph and a constraint graph are generated from an operation clock cycle of hardware / software modules, operation priority and system structure information between modules, Based on the system structure, a schedule result for the operation time of each module that satisfies the system operating clock cycle and the number of pipelines is generated. In addition, if the operating clock cycle of the entire system is not satisfied, the optimum number of pipelines and corresponding schedule results are generated.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In the SOC scheduling method according to the present invention, since the scheduling result is generated to satisfy the performance given to the SOC system structure to be designed, the system performance can be estimated in advance, and accordingly, a program for controlling the system can be easily written. can do. In addition, for pipelined SOC systems, it is possible to provide an optimal number of pipelines and corresponding schedule results from performance requirements.

Claims (5)

(a) receiving information on an operating clock cycle of hardware / software modules included in an SOC system, an operating priority of each module, a system structure, an operating clock cycle of the entire system, and a number of pipelines; (b) generating a priority graph of each of the hardware / software modules as a node and an edge of each module as an edge from the operational priority of each module; (c) generating from the priority graph a first constraint graph representing the operating time between each predicted module such that an operating clock cycle of each module is satisfied; (d) generating a second constraint graph represented by a vertex and an edge by reflecting the system structure information on the constraint graph so that an operation connected to an edge according to the system structure information cannot be performed at the same time; And (e) Performing initial scheduling to satisfy the second constraint graph and performing final scheduling to satisfy the number of operating clock cycles and pipelines of the entire system based on the initial scheduling result to schedule the operation time of each module. Generating a result; SOC scheduling method comprising the. The method of claim 1, wherein step (e) If the operating clock cycle of the entire system is not satisfied with respect to the number of pipelines in the initial scheduling result, a module having an operating clock cycle larger than the system operating clock cycle is found in the initial scheduling result and the operating clock cycle of the module and the And determining the number of pipelines based on an operating clock cycle of the entire system. The method of claim 1, wherein the system structure information, SOC scheduling method comprising a task to be executed in each module and a corresponding operation clock cycle. The method of claim 3, wherein the schedule result, SOC scheduling method comprising the data throughput of the entire system corresponding to the given number of pipelines. The method of claim 4, wherein the schedule result, SOC scheduling method comprising the results corresponding to each of at least two or more pipelines of the given number of pipelines.

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