KR100723770B1 - Nonvolatile memory device - Google Patents

Nonvolatile memory device Download PDF

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Publication number
KR100723770B1
KR100723770B1 KR1020040114139A KR20040114139A KR100723770B1 KR 100723770 B1 KR100723770 B1 KR 100723770B1 KR 1020040114139 A KR1020040114139 A KR 1020040114139A KR 20040114139 A KR20040114139 A KR 20040114139A KR 100723770 B1 KR100723770 B1 KR 100723770B1
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KR
South Korea
Prior art keywords
high voltage
decoder
gate line
device
high
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Application number
KR1020040114139A
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Korean (ko)
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KR20060075362A (en
Inventor
김기석
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020040114139A priority Critical patent/KR100723770B1/en
Publication of KR20060075362A publication Critical patent/KR20060075362A/en
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Publication of KR100723770B1 publication Critical patent/KR100723770B1/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/08Address circuits; Decoders; Word-line control circuits

Abstract

The present invention relates to a non-volatile memory device, and flashes the gate line of the high voltage device constituting the X-decoder so that the width of the high-voltage device that can be reduced according to technology advancement is reflected in the X-decoder layout reduction. By arranging in a direction perpendicular to the gate line direction of the cell, even if the device size is reduced, the number of high voltage devices that can be formed in one block can be kept constant. Therefore, there is an effect that can improve the degree of integration of the device.
Flash memory, X-decoder, high integration

Description

Nonvolatile memory device             

1 illustrates an X-decoder structure of a nonvolatile memory device according to the prior art.

2 is a graph showing the block pitch reduction phenomenon and the basic space required for the X-decoder high voltage device arrangement according to the technology advancement.

3 is a graph showing changes in word line loading according to technological progress

FIG. 4 is a graph showing the variation of the width of high voltage devices constituting the X-decoder according to the progress of technology.

5 illustrates an X-decoder structure of a nonvolatile memory device according to an embodiment of the present invention.

6 is a graph showing the number of high voltage devices that can be formed in one block according to cell size when the present invention is applied.

<Explanation of symbols for the main parts of the drawings>

100: gate line of the high voltage device

200: gate line of the flash cell                 

101a and 101b: source and drain of a high voltage device

102: contact

103: metal wiring

The present invention relates to a nonvolatile memory device, and more particularly to a nonvolatile memory device suitable for improving the degree of integration of the device.

 In recent years, there is an increasing demand for a semiconductor memory device capable of electrically writing and erasing data and not requiring a refresh function. In order to develop a large-capacity memory device capable of replacing and storing a large amount of data, a high integration technology of a memory cell is being developed.

In order to achieve the above object, a NAND flash memory device in which a plurality of cells are connected in series to form one string and two strings share one contact. Was proposed.

A NAND flash memory device includes a plurality of word lines that connect cells arranged in a row direction to one, and an X-decoder is used to select any one of the word lines.

The X-decoder is composed of a plurality of high voltage devices, and operates a flash cell by applying a high voltage of 0 [V] to one selected word line and 4.5 [V] for the remaining unselected word lines.

This X-decoder occupies about 30% of the peripheral circuitry and is an important part of determining the possibility of a package when the product seeks high integration.

Therefore, as the device is highly integrated, the reduction of the high-voltage device constituting the X-decoder is continuously demanded, but since the operating voltage of the flash cell cannot be reduced, the breakdown voltage of the high-voltage device ( Breakdown voltage cannot be reduced, which means gate oxide thickness, channel length, contact to gate spacing and contact to active distance of high voltage devices. Spacing) cannot be reduced.

1 is a view illustrating an X-decoder structure of a nonvolatile memory device according to the prior art, in which gate lines 11 of a high voltage device constituting the X-decoder are arranged in a direction parallel to the gate lines 21 of a flash cell. have.

Unexplained reference numeral 12a denotes a source of the high voltage element, 12b denotes a drain of the high voltage element, and 13 denotes a contact.

In a high voltage device having such a layout, factors that cannot be shrunk in the high voltage device constituting the X-decoder, such as the channel length L, the contact-gate distance, and the contact-active distance, are critical in the block. As the dimension is determined, as the technology is advanced, the higher the degree of integration, the more impossible the construction of the X-decoder is.

FIG. 2 is a graph showing a block pitch reduction phenomenon and a basic space required for arranging an X-decoder high voltage device according to technological progress.

Referring to FIG. 2, the basic space required for the arrangement of the high voltage device is 5.6 μm, and when the block pitch of the X-decoder is 5.6 μm or less, that is, when the technology is about 0.86 nm or less, it becomes impossible to configure the X-decoder. can do.

FIG. 3 is a graph showing changes in word line loading according to technology advancement. As the integration of technology progresses, the word line loading that the X-decoder needs to drive is exponentially reduced.

Wordline loading is the product of the capacitance of a gate of an X-decoder high voltage device and the resistance (C × R). When word line loading is large, it takes time for the high voltage transistor to rise to the output voltage. High consumption and small word line loading require less time to ramp up to the output voltage.

FIG. 4 is a graph showing the variation of the width of the high voltage device constituting the X-decoder according to the technology progress, and the reduction of the word line loading according to the technology progress is the width of the high voltage device while maintaining the same performance. Width can be reduced.

Accordingly, the present invention improves the layout of the high-voltage device constituting the X-decoder so that the width of the high-voltage device, which can be reduced according to technology advancement, is reflected in the X-decoder layout reduction. It is an object of the present invention to provide a nonvolatile memory device capable of increasing the number of high voltage devices that can be formed.

In addition, another object of the present invention is to provide a nonvolatile memory device capable of improving the degree of integration by increasing the number of high voltage devices that can be formed in one block, thereby eliminating the direct limitation factor caused by the X-decoder.

A nonvolatile memory device according to the present invention includes memory cells in which data is stored; And
And a high voltage device configured to supply a high voltage for driving the memory cells to a gate of the memory cells, wherein the gate line direction of the memory cells and the gate line direction of the high voltage devices are perpendicular to each other. Is arranged.

Preferably, a wiring for applying the drain voltage of the high voltage device to the gate line of the memory cell.

Preferably, the high voltage devices are configured to have independent gate lines.

Preferably, the gate line of the high voltage device is configured to be shared by two or more high voltage devices arranged in the gate line direction.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

5 is a diagram illustrating an X-decoder structure of a nonvolatile memory device according to an embodiment of the present invention, where 100 is a gate line of a high voltage device constituting an X-decoder, 101a is a source of a high voltage device, and 101b is a high voltage device. A drain, 102 denotes a contact, 200 denotes a gate line of a flash cell, and 103 denotes a metal wiring for applying a drain voltage of a high voltage element to the gate line of the flash cell.

Referring to FIG. 5, the width of the high voltage device constituting the X-decoder is disposed to have a direction perpendicular to the direction of the gate line 200 of the flash cell.

In other words, the gate line 200 parallel to the width W of the high voltage element is disposed in a direction perpendicular to the direction of the gate line 200 of the flash cell.

It converts the factor that determines dimensions in a block from the non-shrinkable ones such as gate length and contact gate distance to the width of the highly integrated device, which is a shrinkable factor. W) can also be reduced.

Therefore, the number of high voltage devices arranged in the gate line direction within the same block pitch can be increased.

In the embodiment presented using the above drawings, the high voltage devices arranged in the gate line direction are configured to share one gate line.                     

In this case, since the high voltage devices are controlled at once through the shared gate line, an erase operation in a block unit is performed.

In addition, although not shown in the drawing, there is also a method of increasing the degrees of freedom of the high voltage device by configuring the high voltage devices arranged in the gate line direction to have independent gate lines.

In this case, since the high voltage device is controlled separately through each gate line, an erase operation in a page unit is performed.

FIG. 6 is a graph showing the number of high voltage devices that can be formed in one block according to the reduction of the cell size according to the present invention. Even though the cell size is reduced, about 2.2 to 2.4 constant number of high voltage devices are arranged in one block It can be done.

This means that the cell size reduction is not limited due to the X-decoder. When the present invention is applied, device integration can be easily achieved.

As described above, the present invention provides the gate line of the flash cell gate line of the high voltage device constituting the X-decoder so that the width of the high-voltage device that can be reduced according to the progress of technology is reflected in the reduction of the X-decoder layout. By arranging in a direction perpendicular to the direction, the number of high voltage elements that can be formed in one block can be kept constant even if the element size is reduced.                     

Therefore, there is an effect that it becomes possible to manufacture a highly integrated device.

Claims (4)

  1. Memory cells in which data is stored; And
    An X-decoder comprising high voltage elements for supplying a high voltage for driving the memory cells to a gate of the memory cells,
    The gate line direction of the memory cells and the gate line direction of the high voltage devices are arranged in a direction perpendicular to each other.
  2. The method of claim 1,
    And a wiring for applying the drain voltage of the high voltage device to the gate line of the memory cell.
  3. The method of claim 1,
    And the high voltage devices are configured to have independent gate lines.
  4. The method of claim 1,
    And the gate line of the high voltage device is shared by two or more high voltage devices arranged in a gate line direction.
KR1020040114139A 2004-12-28 2004-12-28 Nonvolatile memory device KR100723770B1 (en)

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Application Number Priority Date Filing Date Title
KR1020040114139A KR100723770B1 (en) 2004-12-28 2004-12-28 Nonvolatile memory device

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KR20060075362A KR20060075362A (en) 2006-07-04
KR100723770B1 true KR100723770B1 (en) 2007-05-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9576612B2 (en) 2014-04-07 2017-02-21 Samsung Electronics Co., Ltd. Nonvolatile memory device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200166386Y1 (en) * 1999-08-02 2000-02-15 유소양 Dressing set for home

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200166386Y1 (en) * 1999-08-02 2000-02-15 유소양 Dressing set for home

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9576612B2 (en) 2014-04-07 2017-02-21 Samsung Electronics Co., Ltd. Nonvolatile memory device

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