KR100720750B1 - Global closed loop control system with dv/dt and emi/switching loss reduction - Google Patents

Abstract

Motor drive system 10 control provides wide area closed loop feedback that cooperatively operates system components to adaptively provide noise reduction and noise cancellation feedback. Active EMI filter 12 reduces differential and common mode noise on the input, and provides noise level indication to system controller 11. Power switches in both power converter 14 and power inverter 16 are cooperatively controlled with dynamic dv / dt control to reduce switching noise in accordance with the profile specified by the controller 11. The dv / dt control is provided to the high voltage IC as an analog signal, and is classified as a pulse width for a level shifting circuit that supplies control signals to the high voltage gate drive 21. Noise extraction circuits and techniques obtain fast noise sampling to allow noise cancellation and adaptive noise reduction.

Description

GLOBAL CLOSED LOOP CONTROL SYSTEM WITH DV / DT AND EMI / SWITCHING LOSS REDUCTION}

1 is a system block diagram of a motor control system according to the present invention.

2 is a circuit block diagram of a gate drive HVIC with dv / dt control.

3 is a graph illustrating the relationship between EMI noise and switching losses affected from dv / dt control.

4 is a simplified circuit diagram of a half bridge switch configuration for modeling differential mode noise sources.

5 provides a concise description of how differential and common mode noise affects the system of FIG. 1.

6 is a block diagram illustrating a drawing of a noise sensing feature according to the present invention.

7 is a circuit block diagram of a high side gate control in accordance with the present invention.

FIG. 8 is a timing diagram illustrating the operation of the dv / dt control in the gate driver circuit on the high side described in FIG.

9 is a circuit diagram of a conventional active EMI filter.

10 is an equivalent circuit diagram of the circuit described in FIG. 9.

This application is based on U.S. Patent Application No. 60 / 399,368 filed on July 25, 2002, entitled "EMI / LOSS OPTIMIZATION SYSTEM WITH GLOBAL CLOSED LOOP CONTROL." And assert its priority. And US Patent Application No. 60 / 398,621, entitled "DV / DT CONTROLLED GATE DRIVE HVIC", filed Jul. 25, 2002, claims its priority. The entire contents of the foregoing patent applications are incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to closed loop power control systems, and more particularly to closed loop power control systems that reduce EMI and switching losses and can control the rate of change of gate drive signals.

High-speed switching devices, such as bipolar transistors, MOSFETs and IGBTs, allow the carrier frequency for voltage-source PWM inverters to be increased, leading to excellent operating characteristics. However, high-speed switching causes the following serious problems resulting from high rates of change in voltage and / or current:

a) ground current is drawn to ground through stray capacitors and long cables inside the motor;

b) EMI is conducted and radiated;

c) the motor carries current and shaft voltage; And

d) The insulation life of the motor and converter is reduced.

The voltage and / or current changes generated by fast switching are oscillated at high frequency when the switching devices change state because parasitic stray capacitance inevitably exists inside a load such as an AC motor, a switching converter. Produce common mode and differential mode currents. Thus, each time the inverter switches, the potential of the corresponding inverter output stage moves rapidly with respect to ground, and a pulse of common mode current flows from the direct current link to the inverter through the heat sink motor cable and the motor coils to ground. The amplitude of the current pulses of a Class B (home) motor drive typically ranges from several hundred milliamps to several amps, with pulse widths typically 250 to 500 ns. For Class A (industrial) drives, depending on the size of the motor and the length of the motor cable, pulse current magnitudes typically range from a few amps with pulse widths of 250 to 500 ns to 20 amps with pulse widths of 1-2 μs.

The common mode oscillation current has a frequency spectral range from the switching frequency of the converter to several tens of MHZ, which creates a magnetic field and generates radio-electromagnetic interference (EMI), adversely affecting electronic devices such as wireless receivers or medical equipment Gives.

In some motor appliances, a number of government regulations apply to the degree of allowable line current EMI and the degree of allowable ground current. Thus, in class B home applications, the ground current must be kept below 1-20 mA each (along the log curve) for the frequency range 0-30 kHz, and the conducted line current EMI must be 150 kHz-300 MHz It should remain below the specified value for the range (below about 60 dB * V). For motor drive applications for class A industrial applications, the limits on ground current are less stringent. However, line current EMI is still limited to within 150kHz to 30MHz.

In general, common mode chokes and EMI filters based on passive components may not completely solve this noise and EMI problem. Passive filters, consisting of a "Y" capacitor and a common mode inductor at the input AC line, have been used to filter the common mode current within such drive circuits. Passive common mode filters are limited in the PWM frequency that can be used and are physically large (often occupying most of the motor drive structure volume) and expensive. Moreover, these filters are functionally incomplete in that they exhibit undesirable resonances as opposed to the desired filtering operation. In addition, in general purpose industrial drives, the drive circuit and motor are connected by cables of length 100 meters and more. The longer the cable, the larger the common mode EMI conducted in the motor cable, and the larger the required size of a typical passive common mode input filter.

Common mode converters with additional coils shorted by a resistor are known, which can damp the oscillating ground current. Unfortunately, there is still a small amount of aperiodic ground current in this circuit.

Active filters for common mode circuit control in pulse width modulation (PWM) controlled motor drive circuits are known. Typical devices are described in the article "ACTIVE CIRCUIT FOR CANCELLATION OF COMMON MODE VOLTAGE GENERATED BY A PWM INVERTER" and Ogasawara, published by Satoshi Ogasawara et al. In IEES Transactions on Power Electronics, Vol. 13, NO.5, September 1998. Described in US Pat. No. 5,831,842.

10 illustrates one typical prior art active filter circuit (ie EMI) and noise cancellation device for an AC motor. In FIG. 10, an alternating current source comprising an input terminal L and a neutral terminal is connected to an alternating current input terminal of a rectifier 40 in a full wave bridge configuration. Although a single phase power source is shown, the principles in FIG. 10 and all figures to be illustrated may also be implemented with three or multiple phase inputs. The positive and negative buses of the rectifier 40 comprise A and B points, respectively, and are connected to a PWM control inverter 41 in a three phase bridge configuration at inverter terminals B and F. The output AC terminals of the inverter are connected to an AC motor 42. In addition, the filter capacitor 40a is connected to both terminals B and F. The ground housing of the motor 42 is connected to the ground line 43 having the ground terminal 43a.

The active filter consists of a pair of transistors Q1 and Q2 connected across the DC output line of the rectifier 40, the emitters of which are connected to node E. These transistors define an amplifier controlled by the output coil 44 of the differential converter, with the input coils 45, 47 of the differential converter connected to the positive and negative output buses of the rectifier 40. The polarities of the coils are indicated by general points. Coil 44 is connected between the control terminals of Q1 and Q2 and the common emitter node E. An isolating capacitor 47 is connected to the ground line 43 at node C.

The active filter, including the capacitor 47, defines the path through which most common mode currents are diverted. Otherwise, the common mode current may flow to L or N in reverse with the paths N, A, B, M (motor 42), 43, 43a (or reverse path when the polarity is reversed) or L or N, D, F, M, 43, 43a (or reverse path when the polarity is reversed) Therefore, most common mode currents are switched from the positive terminal A to the paths B, M, C, E, Q2, F, B for "positive current", and B, M, for "negative current". Switch to C, E, Q1, B path. This switching is possible by appropriate control of transistors Q1 and Q2. The path of the common mode current flowing into the negative terminal D follows the path of F, M, C, E, Q2, F for "positive current", and F, M, C, E, Q1 for "voice current". Follow the path of, B. The degree of switching depends on the current gain of coil 44 and the current gain of Q2 for "positive current", and the current gain of coil 44 and current gain of Q1 for "negative current". In order to obtain a sufficient degree of switching of the common mode current, the overall current gain of the coil 44 and the transistors Q1 and Q2 must be large.

The sense transducers 44, 45, 46 in FIG. 10 are large and expensive to provide sufficiently large current gains. It is highly desirable to reduce the cost and size of the transducer without jeopardizing the operation of the circuit. A bigger problem that arises from the need for high gain is that these closed loop circuits tend to produce unwanted oscillations.

In addition, transistors Q1 and Q2 have not been known to operate in a linear range over a sufficiently large area defined as "headroom" in the circuit, which has been known to prevent the active filter operation. The headroom, or the voltage between the collector and emitter of transistors Q1 and Q2, is well understood by considering the approximate equivalent circuit of FIG. 10-shown in FIG. The ground potential at C in FIG. 11 is the same as the potential at the neutral line in FIG. Transistors Q1 and Q2 are shown as resistors R1 and R2, respectively, with diodes connected in parallel. The direct current bridge 40 is shown as two direct current sources 50 and 51, each of which produces an output voltage of VDC / 2. VDC is the total output voltage between the positive and negative terminals of terminals A and D, and AC source 52 has a peak alternating voltage of VDC / 2.

It is shown in FIG. 11 that the headroom may disappear in other portions of the period of the source 52. Therefore, consider the first situation where the leakage impedances of transistors Q1 and Q2 are identical. In this case, the values of the resistors R1 and R2 in Fig. 2 are substantially the same. Now, if the impedance of capacitor 47 is assumed to be much smaller than R1 and R2, the ground potential of terminal C is positive with respect to the DC central node 53 in FIG. 2 with (+) VDC / 2 and (-) VDC. As oscillating between / 2, the potential at the emitters of transistors Q1 and Q2 also oscillates between (+) VDC / 2 and (-) VDC / 2. Thus, during a period where the potential at node E is equal to or equal to the potential at the DC bus (at point B or F), insufficient voltage headroom exists for transistors Q1 and Q2 to operate as linear amplifiers, and active filter operation is lost. do.

Such filters are well known in many electronics, in particular power delivery systems. Systems that include power delivery generally include power inverters that can be used in motor supplies as well as in power supply products. Power inverters are generally supplied with electrical power through power transmission lines operating in multiphase mode. For example, three phase power supply is common in products including inverter operation and motor drives. The three phase power supply includes three transmission lines with a voltage potential between the three pairs of power transmission lines. That is, if a three phase input is supplied through lines L1, L2 and L3, there is a voltage potential between lines L1 and L2, between L2 and L3 and between L1 and L3. These phase-to-phase voltages are generally sinusoidal and out of phase with each other to provide effective power transfer.

In a three-phase system as described above, the transmission lines behave like differential voltage pairs when transmitting a power signal. The power signal is the value of the voltage between the various line pairs. This type of power transmission method is very useful for transmitting power signals while preventing noise disturbances affecting all power lines at the same time. In other words, if all power lines are badly affected by normal disturbance or noise signals, all lines are affected by the same amount and the differential voltages remain the same. Thus, for example, often three-phase transmission lines carry a common mode voltage, where the common mode voltage does not necessarily affect the power signals delivered to the inverter.

When an inverter is used to control and power the motor drive system, the inverter generally uses high frequency switching to direct the appropriate power signals to the motor coil to produce the desired operating performance. For example, the inverter can be operated to control the motor for specific torque operation or desired speed. Because of the high frequency switching of the inverter, there is often a sudden voltage transition in the lines that drive the motor, which is the original source of EMI. This EMI can produce common mode noise that interferes with motor control signals, feedback signals I / O, sensors, and the like. In addition, capacitive coupling between the inverter output and ground, or grounding of the motor itself, can produce high frequency ground currents that further interfere with control signals and other communication signals. The high frequency ground currents produce ground loops that act as loop antennas, inducing radiated interference and increasing the production of radiated noise. High frequency ground currents can also cause instantaneous voltage differences between two ground potential points, which interfere with and interfere with the proper reference of control and communication signals.

In addition to the filters, numerous measurements can control and reduce common mode noise and radiated EMI noise. For example, shielded power cables are used to connect the inverter to the motor to prevent noise currents exiting the motor drive system and into the ground. The power lines to the motor are twisted to provide a balanced capacitive coupling—reducing stray capacitive coupling to ground. Common mode chokes are often used in the power lines inside the motor to dampen common mode noise. EMI filters, such as those described above, are often attached to the inputs of the inverter to act as all pass filters to remove common mode noise from ground ground. Otherwise, the EMI filter creates a ground voltage differential across one or more components of the motor drive system.

Another technique to reduce EMI noise is to measure high frequency noise currents and provide compensation for any detected currents. Current converters, as described above and in other existing techniques, have been used to sense noise currents to determine the appropriate compensation to control EMI. However, properly sized current converters are difficult to handle, expensive and actually perform non-linear operation. It would be desirable to provide a circuit and technique that reduces EMI without the use of a current converter.

Often, an EMI reduction system exists as part of a large closed loop control to operate a synchronous motor using the inverter. For example, multiple high level systems may provide command and control signals to the inverter controller to operate a motor or power supply in connection with an associated high level system. Thus, in addition to reducing closed loop control including the inverter and sensor feedback, it is desirable to reduce EMI production throughout the system.

In high voltage inverter systems, level shifters are often used to provide control signals to half bridges that make up the various stages of the motor drive. In the level shifting system, the references are generally changed as a reference level that matches the inverter power supply at a logic voltage level. As a result, the control signals are transmitted in the form of pulses by the level shifting circuit to prevent additional energy loss caused by the power switches being held in the power conduction mode to allow signal transmission. Thus, the input signal is provided to a pulse generator that provides an impact coefficient of the input signal to the pulse train. The pulse train is then converted to a control signal to control the gate drive in the application. Often, due to the high frequency, high power switching characteristics, voltage spikes with a huge amount of voltage change per unit time are observed on the gate drive and half bridge components. It is desirable to control or reduce the change in voltage per unit time to prevent voltage spikes resulting in excess EMI and other disruptive control operations. Recently known solutions for controlling dv / dt of high frequency, high power switching applications are difficult, complex and expensive. Therefore, it is desirable to find simple control of high voltage, high frequency switching applications to modulate the dv / dt inverter gate drive.

In a motor drive with an inverter, space vector modulation is often used to control the motor based on quadrant switching of the switches of the inverter. In this form of motor control, accurate motor phase current measurements are useful to provide high performance control, such as speed or torque control, for specific applications. However, it is difficult to accurately measure motor phase current over a wide range of currents and temperatures. Hall effect sensors, for example, are used in lines that drive a motor, which is inherently difficult and expensive. In pulse width modulation (PWM) inverter drive systems, the motor phase current can be determined from the measurement of the DC bus current when non-zero basis vectors are used in the space vector modulation. Each base vector is assigned at a specific time in the PWM cycle to produce a command voltage vector. However, if the base voltage vector is only used for a very short time, the motor phase current cannot be determined directly from the DC bus current. The lack of observation of the motor phase current occurs due to practical considerations and limitations in the response of the components of the PWM inverter drive system. For example, time delays caused by a / d converter samples and hold times, slewing of the voltage during turn on, and other delay factors can affect the effects of the fundamental vectors used for a very short time. To prevent observation. Therefore, it is desirable to observe the effects of the fundamental vectors used for a very short time and to obtain all the values of the motor phase current for all control periods to obtain a high performance motor drive.

According to the present invention, a closed loop control system for synchronized synchronous motor control and synchronized switching to reduce EMI generation is provided. Wide area control according to the present invention provides dynamic bus voltage control with dynamic dv / dt control for inverter gate drives. A number of closed loop control parameters are sensed and provided as input to an algorithm related to the optimization of system operation. The integrated control system provides power factor correction control through a dynamic switching method, allowing "0" voltage switching at minimal current. Active EMI filtering significantly reduces common mode and differential mode noise in the system. The control system obtains an estimate of the motor current by measuring only the DC bus voltage provided to the inverter. Adaptive EMI noise reduction, along with an algorithm to synchronize switching between the inverter and the power factor correction circuit, increases the efficiency of the overall system and provides a more reliable and cost-effective overall motor drive system solution. In addition, the system control provides an interactive look ahead control scheme to adjust power factor correction and inverter operation for improved operational reliability and efficiency. Through the use of these techniques in an entire wide area closed loop control system, a reliable and efficient overall system is realized, along with a reduction in the size of the component due to a reduction in the voltage and current ratings required in the component. In addition, due to the increased efficiency of the overall system operation, the main passive components with high permissible ratings can be greatly reduced, or in some cases eliminated.

The present invention provides control of the rate of change of voltage per unit time when turning on or off the power switches of the power converter or power inverter for the motor drive system. The analog signal from the controller is provided to a high voltage gate drive integrated circuit to specify a change in voltage per unit time used to switch a power switch connected to the gate drive. In the case of a high side high voltage switch, typically shown in a half bridge switching arrangement, the gate command signal is level shifted to be referenced to the switching voltage for the high side power switch. The control signal for voltage change per unit time is applied to the level shifted gate command signal through the use of pulse width modulation. The gate command signal is divided into pulses for starting and stopping a switching event, the width of the pulses representing a desired control of the rate of change of voltage per unit time to be applied to the switching event.

There is a trade off between the control of EMI noise through the control of the voltage change per unit time applied to the gates of the power switches and the switching losses 내부 inside the power switches. Thus, the control of the present invention has an optimized control profile, switching losses and preferred control profiles that vary noise levels. For example, the control can be modified to improve the reduction of differential mode noise and the reduction of common mode noise.

Noise signals can be quickly measured according to the present invention by extracting an indication of noise energy from the noise signal and providing a synchronization signal associated with the extracted energy. The information about the signal is converted into a machine readable format using, for example, an a / d converter. The motor drive system controller can use the noise signal information to cancel noise in the system, to reduce the generated noise or to change the operating point of various components.

The invention will be explained in more detail with reference to the accompanying drawings.

According to FIG. 1, an overall wide closed loop motor control system is generally illustrated as system 10. System 10 includes several large subsystems, including active EMI filter 12, power factor correction and power converter circuit 14, inverter circuit 16, and inverter control 18. The global system control 11 provides the entire command, control and feedback circuitry and calculations for operating the drive system 10.

Active EMI filter 12 senses common and differential mode noise on input alternating lines L1, L2 and optionally common line COM, and provides a feedback signal to cancel out noise generated in system 10. A detailed description of the active EMI filter 12 showing various embodiments with circuit diagrams is provided in the currently pending US patent application Ser. No. 10 / ..... (Agent No. IR-2291). All of which are hereby incorporated by reference. Active EMI filter 12 has excellent noise reduction operation, which greatly improves overall efficiency and noise immunity in system 10. Active EMI filter 12 senses and cancels common and differential mode noise at the front end of system 10 using active switching without current conversion. By avoiding the current converter in the active EMI filter 12, a more linear noise filtering operation is achieved without the losses associated with current converter type filtering systems. Appropriately configured active EMI filters may be located in other parts of the motor drive system 10 that operate on the same principles as when the EMI filter 12 operates.

The PFC power converter 14 uses dynamic bus voltage control and minimizing switching losses to achieve increased efficiency and high performance. The switching in the PFC power converter 14 is controlled by the controller 11 and also provides a control signal for the voltage change rate per unit time dv / dt. The PFC power converter 14 provides feedback to the controller 11 which directs operating parameter values to obtain closed loop control for power factor correction and power conversion of the PFC power converter.

Gate driver 18 receives a gate command signal from controller 11 to provide a regulated gate signal to switches in inverter 16. One of the regulating elements driving the gate command signals for inverter 16 is the voltage change rate per unit time, which indicates the desired rate of change for the voltage groups or switch groups of the voltage switch imposed on gate driver 18. . Thus, as described in more detail below, the signaling provided by the controller 11 provides dynamic dv / dt control for the gating switches in the inverter 16.

The controller 11 obtains a signal from the shunt in the direct current to reconstruct the motor drive current without the need for additional and expensive current sensors in the motor drive lines. The motor current reconstruction via measurements on the bus is described in the detailed description of US Patent Application No. 10 / 402,107, which is incorporated herein by reference in its entirety. The motor current reconstruction is based on a space vector control algorithm that is part of the control operation of the controller 11.

The controller 11 performs a number of coordination functions and a number of synchronizing functions to obtain overall wide closed loop control for the system 11. For example, the controller 11 may output command signals to the PFC power converter 14 and the gate driver while reading the sensor information and the feedback information from the DC bus, the active EMI filter 12, and the PFC power converter 14. 18) to provide. Controller 11 operates the programmed algorithms and intelligence to achieve a number of optimization features in system 10. For example, the controller 11 adjusts the operation of the PFC power converter 14 to minimize switching losses in the PFC power converter 14 while providing dynamic bus voltage control. The controller 11 also performs synchronized switching operations in both the inverter 16 and the power converter 14 to reduce the composite EMI generated by asynchronous operation.

The controller 11 also includes a number of algorithms for motor drive control. For example, the controller 11 coordinates the operation of the converter 16 with a gate driver 18 that drives the motor present in the sinusoidal non-sensing control algorithm based system 10. The sinusoidal nonsensing algorithm does not require a pitback from the motor. Other algorithms available in the controller 11 are motor phase current measurement algorithms based on DC bus current measurements and space vector control measurements. Since the controller 11 has not only switching loss profiles and features but also a number of input parameters related to conducted or radiated EMI, an algorithm for the operating system 10 to reduce and minimize EMI and switching losses is provided. Available. As other operational profiles are applied for the motor drive in system 10, controller 11 provides adaptive loss minimization, bus voltage control, and EMI noise reduction. That is, the controller 11 has adaptation algorithms that provide dynamic control based on the specific operating characteristics of the system and provides the desired motor drive with the operable features required by the application. The controller 11 also uses interactive look ahead control to provide an assessment of the required operation of the PFC power converter 14 and inverter 16. Control 11 with predictive control type based on the desired operating profile and experience can increase the efficiency of system 10 while reducing the need for power component reading. For example, capacitor C _BUS may have a much smaller power ratio than required in the prior art, depending on the reduced cost and the reduced packaging size.

With reference to FIG. 2, the dv / dt control for the power switching phase of system 10 is generally illustrated by gate drive 20. In the example of inverter 10 of FIG. 1, three different gate drives 20 are used to control each half bridge of inverter 16 so as to obtain a desired control profile for the motor. Gate drive 20 receives input control signal HIN and input control signal LIN for high side and low side switch 21, 22 control separately. HIN and LIN are configured and adjusted so that both switches 21 and 22 are not at the same time. However, the space vector control method provided by the control via inputs HIN and LIN allows both switches 21 and 22 to be turned off at the same time.

An input signal HIN is provided to the level shifting circuit 24 to obtain an appropriate control voltage with reference to the high side logic ground reference VS. The level shifting circuit 24 is the same as that disclosed in US Pat. No. 5,502,412, the entire disclosure of which is incorporated herein by reference. Thus, the level shifting circuit 24 can actuate a control signal as a reference for a particular input potential difference between the line voltage and the line voltage return value, having a value less than a fixed ground reference, thereby causing a voltage swing. Can be avoided. The level shifting circuit 24 which references the high side switch 21 differently prevents the loss of the signal or communication between the control circuit and the high voltage thereby.

The high side gate drive also includes a variable pulse generator 26 operating on a high side voltage input control signal HIN with the dv / dt ratio signals TONH and TOFFH, which is described in more detail below. The dv / dt ratio signals TONH and TOFFH adjust the gate command signal HIN to transmit a specific rate of change with respect to the voltage applied to the high side switch 21. The gate command signals supplied to the input HIN are provided as pulses that reduce the power required to operate the level shifting circuit 24. Thus, TONH and TOFFH manipulate the pulse on input HIN to obtain a set of pulse lengths provided to input HIN and a reset pulse indicator. The level shift pulses are provided to the dv / dt filter 25 for both the set pulse output and the reset pulse output of the variable pulse generator 26. Filters 25 induce a small delay of the set and reset pulses provided to RS flip-flop 23, which serve as the drive logic command for gate drive circuit 27. Thus, when flip-flop 23 is set to ON, an upward transition is provided to gate drive circuit 27, and a duration indicated by the gate signal command provided with a high logic signal on input HIN. Is sent to the gate driver circuit 27 for a duration such as. For example, at the end of the pulse duration, the flip-flop 23 is reset, causing a transition from high side to low side in the gate drive circuit 27 on the input signal, and the switch ON time of the high side switch 21. Finish the gap for. The set and reset signals supplied by the filters 25 are also provided as inputs to the pulse-to-voltage converter 28, which controls the gate voltage of the CMOS driver switch in the gate drive circuit 27. Thus, gate voltage control is determined based on the switch ON and switch OFF signals in addition to the voltage signal derived from the pulse output length of the filters 25. According to this method, the rate of change with respect to the voltage per unit time applied to the gate of the high side switch 21 is controlled for a specific turn on and turn off profile.

In the low side switch 22, there is no level switching circuit for the gate command signal input LIN. Thus, the voltage change rates of the command signals TONL and TOFFL are directly provided to the gate voltage control of the low side switch driver circuit 29. Therefore, the voltage change rate per unit time applied to the gate of the low side switch 22 is directly controlled by the input voltage signals TONL and TOFFL.

The dv / dt control on the gate drive 20 controls the rate of change of voltage transmitted to the gates of the high and low side switches 21, 22, thereby reducing noise associated with half bridge switching. The noise reduction contributes to the wide area closed loop control for the system 10 to further enhance EMI noise reduction while improving the efficiency of the system. Referring to FIG. 3, a graph is provided showing the relationship between loss in the switches versus EMI noise generated by fast dv / dt in the power switches. In particular, the optimized operating points are in the vicinity of the origin of FIG. 3, and the optimized operating points correspond to small DC bus voltage values. The active EMI noise and power loss optimization algorithm finds the best application solution for EMI noise reduction and power loss reduction by considering the operating parameters influencing noise and switching losses. For example, as illustrated in FIG. 3, the reduction of EMI noise through voltage change rate control per unit time affects the losses in the power switches, so the optimized solution is based on the operating set point. Balance your considerations.

In determining the optimization method, the selections can be made based on differential mode noise reduction or common mode noise reduction. For differential mode noise reduction, dv / dt is made to slow down during the switch ON period, TON. For common mode noise reduction, dv / dt is slowed both during TON and during TOFF.

An example of a source of differential mode noise is provided in FIG. 4, where a positive motor current is generated based on the operation of a pair of switches in the inverter 16. In the first switch configuration, the high side switch is OFF, and the low side switch is ON, and motor current is induced in the low side line providing the motor coil. Thus, the low side switch is open and motor current continues to flow from the low side line to the motor coil through a free wheeling diode coupled to the low side switch. The next switch sequence is to close the high side switch to induce motor current from the high side line. Fast switching of the current direction results in high frequency transient currents in the inverter 16 and generates high frequency differential mode noise.

Referring to FIG. 5, an example of a collision of both differential mode noise feedback and common mode noise feedback is shown. Differential mode noise is typically present with high frequency noise related to the voltage difference between lines L1 and L2. Lines L1 and L2 are modeled capacitively connected together to illustrate the collision of differential mode noise. The active EMI filter 12 illustrated in FIG. 1 operates to reduce the differential mode noise and the high frequency noise current observed in lines L1 and L2 by matching the voltage.

The common mode noise illustrated in FIG. 5 is modeled with a power line capacitively connected to ground in the example of the present power line L1. The voltage difference in the ground line or the high frequency noise current flowing through the ground is coupled to the power line and generates both conducted and radiated EMI noise. In addition, the active EMI filter 12 illustrated in FIG. 1 is configured to reduce common mode noise by sensing and canceling the high frequency noise current present in the ground line. When active EMI filter 12 is operated in conjunction with EMI noise and switching loss optimization through control of the dv / dt associated with the switches in inverter 16, EMI noise and switching loss reduction in the overall system is achieved. do.

Another feature of the global closed loop control of the system 10 is fast noise sensing, which improves response time by canceling or balancing high frequency noise voltages and currents. The high speed noise sampling operates by extracting the noise energy from a sensed line, such as a ground line, and converting the extracted energy into a synchronous noise signal through a sample and hold circuit. Next, the noise energy extraction and noise synchronization are illustrated in steps 61 and 62 of FIG. 6. Thus, the synchronized noise signals illustrated with trapezoidal waveforms are flashed 3-bit analog / digital. It is digitized in the (A / D) converter 66. As a result, a synchronized pulse sequence is generated that represents the noise signal waveform 63 in a digitized format. A system controller 11 reads the noise signal information thus obtained, provides an operation command to the PFC power converter 14 and the gate driver 18, and provides the noise information to the noise control and loss reduction of the system 10. Used within the adaptive algorithm used in.

The application of the analog dv / dt control signal to control the change in voltage per unit time of the power switch in both the PFC power converter 14 and the inverter 16 is carried out via a number of pulse regulation and voltage ramp circuits. The controller 11 generates an analog voltage signal in the range of 0-3V to control the gate voltage of the gate drivers provided to the associated power switch. For example, the dv / dt command signals, such as TONH, TOFFH, TONL and TOFFL, contain information relating to the time period. The information related to the time period includes a time period for delaying or slowing the rate of change of voltage per unit time associated with changing the turn on and turn off order. As illustrated in FIG. 2, variable pulse generator 26 generates pulses in the range of 100-300 nanoseconds in proportion to the analog dv / dt command signal value. The timing of the pulses shows set and reset commands as determinants of the switching interval for the power switches. The length of the pulse interval associated with the analog dv / dt signal value and the gate command signal determines the rate of change value for the exchange of the power switch. For example, referring to FIG. 2, the high side switch control is provided as a series of switch commands on signal input HIN. The switch commands are converted into pulses that classify the switch command and the desired dv / dt control. The pulses help transmit information without keeping the switch in the ON setting to avoid unnecessary power consumption. According to the circuit illustrated in FIG. 2, the variable pulse generator 26 provides set and reset pulses equivalent to the start and end of the gate input control signal HIN. The variable pulse generator 26 also helps to vary the length of the start and end pulses based on the analog input associated with dv / dt ratio control for the high side power switch.

7 and 8, a simple diagram of the dv / dt control feature is illustrated. Circuit 70 is equivalent to the front end of the high side gate driver for gate drive 20. A timing figure is illustrated in FIG. 8 to explain the operation of the circuit 70. Gate command signal 80 illustrates the input into the two variable pulse generators 71 and 72. Pulse generator 72 generates reset pulse 82, while pulse generator 71 generates ON or set pulse 81. As can be seen from the timing diagrams 80-82, the reset pulse 82 indicates the end of the gate command signal 80, while the set pulse 81 indicates the gate command pulse 80. By applying the gate command signal as pulses rather than a single long gate turn-on command signal, the gate driver command keeps the N-channel level shifting switches ON for a long period of time. It can be level shifted to the power level associated with the high side switch 21 without undue losses that may occur when.

In FIG. 2, pulses 81 and 82 are illustrated with variable duration based on the input analog dv / dt ratio commands from input signals TONH and TOFFH. For example, according to the indication of FIG. 2, pulses 81 and 82 are in the range of 100 ns to 300 ns. Referring also to FIGS. 7 and 8, the level shifted drive signals based on pulses 81, 82 have a particular delay among others, in particular for the pulses 81, 82. It is sent to the dv / dt filter provided. The resulting filtered pulse train 83, 84 is flip-flop to reconstruct the gate command signal 80 in the gate drive circuit 27 (FIG. 2) driving the high side switch 21. FIG. Used to set and reset 76. In addition, pulse amplitude converters 77, 78 input pulses 83.84 and operate on them to generate gate voltage control signals TONV 85 and TOFFV 86. Gate voltage control signals TONV and TOFFV drive the CMOS switches used to operate the gate of the high side switch 21. Referring to FIG. 8, the signals TONV and TOFFV are illustrated with variable voltage levels based on the duration of the pulses 83, 84. The signal TONV starts with the rise of the ramp on the rising transition of the filtered set pulse 83 and flattens at the falling transition or end of the pulse 83. Thus, pulse 85 stays at the voltage value that is performed for a fixed period of time so that all signals within the gate drive control obtain proper propagation. Similarly, the signal TOFFV begins with the rise of the ramp on the rising transition of the pulsed reset pulse 84 and continues to the duration of the filtered reset pulse 84. At the end of the filtered reset pulse 84, the signal TOFFV is maintained at the voltage reached during the pulse, and a fixed time period for proper gate drive control again allows propagation of all control signals. The time period for the ramp rise of both TONV and TOFFV, as apparent from the comparison of pulse trains 83,84 to signals 85,86, is the pulse duration of the filtered set and reset pulses 83,84. Depends on The value reached at the end of the rise indicates how the gate turn on and turn off voltages adjust the switching of the high side power switch 21. With this type of control, despite the transfer of the gate command signal through the level shifting circuit 24 (FIG. 2), the dv / dt for gate turn on and turn off of the high side switch 21 is simply and Can be controlled easily. Clearly from FIG. 2, the analog dv / dt ratio control signals TONL and TOFFL for the low side switching 22 can be used directly with the gate voltage controls 220, 221 without the need for translation through the level shifting circuit. . Alternatively, if the COM line to gate driver 20 is floating for an input control signal, the low side level shifting circuit can be used to operate gate drive circuit 29 and low side switch 22. have. In this case, the circuit and operation may be as provided to the high side circuit.

It is clear that the overall gate drive circuit 20 illustrated in FIG. 2 can be performed on a single high voltage integrated circuit (HVIC). Such HVICs have input HIN, LIN and dv / dt ratio control signals with connections to positive and negative DC bus lines, high and low gate control lines and high voltage reference connections (VS). The HVIC can be used in each of the three legs for driving the multiphase motor illustrated in FIG. 1. That is, the three illustrated half bridges in the inverter 16 are controlled by the HVIC integrating the components of the gate driver 20.

Controller 11 can store a number of algorithms and programs related to adaptive adjustments based on different dv / dt profiles and given performance criteria. For example, in very noisy environments or in high precision or strong stability applications, the dv / dt ratio can be set very low to avoid large amounts of induced, conducted, or radiated EMI. In addition, the dv / dt settings may be adjusted to apply for either the turn on turn or both the turn on and turn off turn to individually affect either the differential mode or the common mode. By allowing flexible application of the dv / dt control, switching losses can be minimized while targeting specific noise production. The analog dv / dt signals applied to gate voltage controls 210, 211 and 220, 221 are preferred for fixed time periods that are somewhat greater than or approximately equivalent to the switch on time or switch off time of the main switching devices 21, 22. Maintained at the analog level. It is clear that the present invention is not limited to motor drives but can be applied to large groups of power supply systems. The power switches 21, 22 may thus be MOSFETs, as well as such MOSgated devices such as IGBTs. In addition, the analog voltages related to the dv / dt ratio control are applied to affect the gates of CMOS switches in gate drivers 27 and 29 through the CMOS transistor output to control the CMOS output impedance.

Wide area closed loop drive systems are described as achieving a number of strengths over existing technology systems through the coordination of various components and noise reduction techniques to perform a robust and noise resistant system as a whole. Active EMI filters are used to actively filter common and differential mode noise from input AC lines without the use of current transducers. The filtering may be used at the DC bus output stage. A buck / boost converter with PFC control is provided to obtain a DC bus voltage while appearing as a practical resistive load on the AC line. The power converter is actively controlled to reduce switching losses and at the same time achieves dynamic bus voltage control based on such dynamic and environmental vectors such as received noise. In addition, the switch in the PFC converter uses dynamic dv / dt control to further reduce the generated noise, and is operated in conjunction with the switches in the system inverter to further reduce EMI generation. Inverter switches are controlled with dynamic dv / dt technology to reduce transient and noise generating events. The sinusoidal non-sensing control algorithm implemented in the system control produces high performance with increased efficiency. Motor current phase measurement is processed in conjunction with a DC bus current measurement method based on the space vector control algorithm, and is also performed within the system controller. Dynamic control of various system elements optimizes the system for reduced EMI noise and reduced switching losses. The adaptive algorithm in the system controller provides closed loop EMI noise reduction control to provide more effective noise reduction and system efficiency improvement. The system switches operate in conjunction with interactive look ahead control to predict and correct for operational profiles in which noise generation or switching loss events exist.

While the present invention has been described in connection with specific embodiments, many other variations and corrections and other uses are apparent to those skilled in the art. Thus, the invention is not only described herein. It is preferred to be defined by the claims.

The present invention provides a closed loop power control system that reduces EMI and switching losses and can control the rate of change of the gate drive signal.

Claims (5)

As the gate driver for the power switch: A gate drive circuit coupled to the gate of the power switch for at least one of turning on and off the power switch; A gate voltage control circuit in the gate drive circuit for controlling a voltage applied to the gate of the power switch during at least one of turning on and turning off the power switch; And And a signal indicative of a rate of change in voltage per unit time, the signal being applied to the gate voltage control circuit, the signal being applied when the at least one of turning on and turning off the power switch is performed. Gate driver for the switch. The method of claim 1, And a level shifting circuit for shifting the reference of the gate driver to a high voltage reference. The method of claim 2, A variable pulse width generator coupled to the level shifting circuit for providing pulses indicative of the beginning and end of the gate command for the power switch to the level shifting circuit; Wherein the pulses vary in width depending on the required dv / dt control parameter. The method of claim 2, A pulse / voltage converter coupled to the level shifting circuit for providing an analog voltage level based on the width of an input pulse, Wherein the analog voltage level is applied to the gate voltage control circuit. As a way to control the motor drive system to reduce noise: Providing a signal relating to a required rate of change per unit time for a gate of a power switch in said motor drive system; Applying the signal to the power switch gate driver; Varying the turn on or turn off time of the power switch based on the signal; And Correcting the signal based on an adaptive trade-off between noise reduction and switching loss in the power switch by varying the turn on or turn off time of the power switch. How to control your system.

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