KR100720479B1 - Method for fabricating an CMOS image sensor - Google Patents

Abstract

The present invention relates to a method for manufacturing a CMOS image sensor which improves the reliability and yield of a device by forming a pad opening after forming a microlens and preventing progressive corrosion occurring on the metal pad. Forming a metal pad in a pad area on the substrate divided into regions, and forming a protective film on the front surface of the substrate including the metal pad and selectively removing the protective film to expose the surface of the metal pad to form a pad open portion And forming an insulating film on the front surface of the substrate including the pad opening, forming a color filter layer on the insulating film in the active region, forming a microlens on the color filter layer, and the substrate. The insulating film formed on the pad area of the film is selectively removed by the CDE method. And it characterized in that it is formed by a step.

Image Sensors, Metal Pads, Microlenses, CDE, Plasma

Description

Method for fabricating an CMOS image sensor

1 is an equivalent circuit diagram of one pixel of a general CMOS image sensor

2 is a layout view of one pixel of a general CMOS image sensor

3A to 3F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art.

4 is a SEM image showing a microlens of a CMOS image sensor according to the prior art

5A through 5F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention.

6a and 6b show the results of comparing the roughness of the surface of the conventional microlenses of the present invention with SEM analysis.

Description of the main parts of the drawing

200 semiconductor substrate 201 first insulating film

202: metal pad 203: protective film

204: photosensitive film 205: pad opening portion

206: second insulating film 207: first planarization layer

208, 209, 210: R, G, B color filter layer 213: Microlens

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly, to a method for manufacturing a CMOS image sensor which improves device characteristics and improves yield.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally a charge coupled device (CCD) and CMOS metal (Complementary Metal Oxide Silicon) image. It is divided into Image Sensor.

In the charge coupled device (CCD), a plurality of photo diodes (PDs) for converting a signal of light into an electrical signal are arranged in a matrix form, and the photo diodes in each vertical direction arranged in the matrix form. A plurality of vertical charge coupled device (VCCD) formed between the plurality of vertical charge coupled devices (VCCD) for vertically transferring charges generated in each photodiode, and horizontally transferring charges transferred by the respective vertical charge transfer regions; A horizontal charge coupled device (HCCD) for transmitting to the sensor and a sense amplifier (Sense Amplifier) for outputting an electrical signal by sensing the charge transmitted in the horizontal direction.

However, such a CCD has a disadvantage in that the manufacturing method is complicated because the driving method is complicated, the power consumption is large, and the multi-step photo process is required.

In addition, the charge coupling device has a disadvantage in that it is difficult to integrate a control circuit, a signal processing circuit, an analog / digital converter (A / D converter), and the like into a charge coupling device chip, which makes it difficult to miniaturize a product.

Recently, CMOS image sensors have attracted attention as next generation image sensors for overcoming the disadvantages of the charge coupled device.

The CMOS image sensor uses CMOS technology that uses a control circuit, a signal processing circuit, and the like as peripheral circuits to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby forming the MOS transistors of each unit pixel. The device adopts a switching method that sequentially detects output.

That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor has advantages, such as a low power consumption, a simple manufacturing process according to a few photoprocess steps, by using CMOS manufacturing technology.

In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into the CMOS image sensor chip, the CMOS image sensor has an advantage of easy miniaturization.

Therefore, the CMOS image sensor is currently widely used in various application parts such as a digital still camera, a digital video camera, and the like.

On the other hand, CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors. An equivalent circuit and layout of the unit pixels of the 3T-type CMOS image sensor will be described as follows.

FIG. 1 is an equivalent circuit diagram of a general 3T CMOS image sensor, and FIG. 2 is a layout diagram illustrating unit pixels of a general 3T CMOS image sensor.

As shown in FIG. 1, a unit pixel of a general 3T CMOS image sensor includes one photodiode (PD) and three nMOS transistors T1, T2, and T3. The cathode of the photodiode PD is connected to the drain of the first nMOS transistor T1 and the gate of the second nMOS transistor T2.

The sources of the first and second nMOS transistors T1 and T2 are all connected to a power supply line supplied with a reference voltage VR, and the gate of the first nMOS transistor T1 has a reset signal RST. It is connected to the reset line supplied.

Further, the source of the third nMOS transistor T3 is connected to the drain of the second nMOS transistor, the drain of the third nMOS transistor T3 is connected to a read circuit (not shown in the drawing) via a signal line, The gate of the third nMOS transistor T3 is connected to a column select line to which a selection signal SLCT is supplied.

Accordingly, the first nMOS transistor T1 is referred to as a reset transistor Rx, the second nMOS transistor T2 is referred to as a drive transistor Dx, and the third nMOS transistor T3 is referred to as a selection transistor Sx.

As shown in FIG. 2, in the unit pixel of a general 3T CMOS image sensor, an active region 10 is defined so that one photodiode 20 is formed in a wide portion of the active region 10. Gate electrodes 120, 130, and 140 of three transistors that overlap each other in the active region 10 of the remaining portion are formed.

That is, the reset transistor Rx is formed by the gate electrode 120, the drive transistor Dx is formed by the gate electrode 130, and the selection transistor Sx is formed by the gate electrode 140. Is formed.

Here, impurity ions are implanted into the active region 10 of each transistor except for lower portions of the gate electrodes 120, 130, and 140 to form source / drain regions of each transistor.

Therefore, a power supply voltage Vdd is applied to a source / drain region between the reset transistor Rx and the drive transistor Dx, and a source / drain region on one side of the select transistor Sx is shown in a read circuit (not shown). Not used).

Although not illustrated in the drawings, the gate electrodes 120, 130, and 140 described above are connected to respective signal lines, and each of the signal lines has a pad at one end thereof and is connected to an external driving circuit.

As described above, each signal line including the pad and the processes proceeding thereafter are described below.

3A to 3F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art.

First, as shown in FIG. 3A, an insulating film 101 such as a gate insulating film or an interlayer insulating film is formed on the semiconductor substrate 100, and metal pads 102 of respective signal lines are formed on the insulating film 101. In this case, the metal pad 102 may be formed on the same layer as the same material as each of the gate electrodes 120, 130, and 140 as described with reference to FIG. 2, and may be formed of a different material through separate contacts. It is mostly formed of aluminum (Al). A protective film 103 is formed on the entire surface of the insulating film 101 including the metal pad 102. The protective film is formed of an oxide film or a nitride film.

As shown in FIG. 3B, a photosensitive film 104 is formed on the passivation film 103, and exposed and developed using photolithography to expose an upper portion of the metal pad 102. After the protective film 103 is selectively etched using the photosensitive film 104 as a mask to form the pad opening portion 105 on the metal pad 102, the photosensitive film 104 is removed.

As shown in FIG. 3C, a pad protective layer 113 is formed on the entire surface of the substrate on which the pad opening 105 is formed.

Here, the pad protective film 113 is formed of a plasma emhancement (PE) oxide film, PE TEOS or PE nitride film, and the thickness thereof is about 200 kPa to 600 kPa.

As shown in FIG. 3D, the first planarization layer 106 is deposited on the entire surface of the pad protection layer 113, and the photo planar etching process using a mask is used to leave only portions except the metal pad portion.

A blue color filter layer 107, a green color filter layer 108, and a red color filter layer 109 are sequentially formed on the first planarization layer 106 corresponding to each photodiode region (not shown in the figure).

Here, in each of the color filter layer forming methods, the color photosensitive material is coated and the color filter layers are formed by a photolithography process using a separate mask.

As shown in FIG. 3E, the second planarization layer 111 is formed on the entire surface of the substrate including the color filter layers 107, 108, and 109, and the photo-etching process using a mask remains only in the region excluding the metal pad portion. do.

As shown in FIG. 3F, a dielectric material is deposited on the second planarization layer 111, and the dielectric material is selectively removed by a photolithography process to correspond to each color filter layer 107, 108, and 109. The lens 112 is formed.

In this case, the pad opening layer 105 is exposed by removing the pad protection layer 113 on the upper side of the metal pad 102 by RIE or the like without adding a separate mask.

Then, after the probe test of each metal pad 102 of the CMOS image sensor manufactured as described above to check the contact resistance, if there is no abnormality, the external driving circuit and the metal pad are electrically connected.

However, in the manufacture of the CMOS image sensor according to the prior art as described above, the protection of the metal pad is an important factor.

In FIG. 3B, after the metal pad 102 is opened, a process of forming the first flattening layer 106 → the color filter layers 107, 198, 109 → the second flattening layer 111 → the microlens 112 is performed. The photo process is continued.

Exposure and development processes are involved in the photo process, and the pads are subjected to chemical attack by the developer used in the development process to be damaged.

This damage appears in the form of corrosion and contamination and degrades the electrical properties of the product. In order to solve this problem, a pad protective layer 113 is formed on the entire pad and the wafer.

The reason is that after forming the microlens 112, the pad protection layer 113 must be etched to open the metal pad 102. If too thick, the microlens 112 also damages the pad protection layer 113 during etching. This is because the shape of the film is changed or roughness is formed on the surface, thereby degrading the function of the microlens.

In addition, after the color filter layers 107, 108, and 109 are formed, a second planarization layer 111 is formed. The thickness of the color filter layers 107, 108, and 109 is generally 0.5 to 1.5㎛ based on 0.25㎛.

Meanwhile, when the color filter layers 107, 108, and 109 are formed, some color loss is generated in the subsequent developing process, and the degree of loss of the color filter is different depending on the color filter. Thus, a step is formed between the color filters. If the microlens is formed directly on the color filter in which the step is present, the depth of focus (DOF) is changed and the thickness of the microlens layer is locally generated due to the step. gap), which in turn hinders the device's electrical characteristics.

In order to prevent such a phenomenon, the second planarization layer 111 is formed to cover the color filter layers 107, 108, and 109 sufficiently. In general, the thickness is 1 to 2 mu m thicker than that of the color filter layer.

Meanwhile, in the process of etching the pad protective layer 113 in FIG. 3F, the microlens 112 is also etched in a predetermined amount. In most cases, in order to etch the pad protective layer 113, an Ar-added gas for improving uniformity is generally used for the F-based CxFy and O ₂ mixed gas.

In addition, since the RIE method is used, roughness may occur on the surface of the microlens by ion bombardment.

This roughness can be analyzed simply by SEM.

That is, FIG. 4 is an SEM image showing a microlens of a CMOS image sensor according to the prior art.

As in FIG. 4, it can be seen that the surface of the microlens is rough. Such roughness causes diffuse reflection of light, thereby weakening the intensity of light incident on the photodiode and causing signal degradation.

That is, the signal processing capability of the image sensor is reduced.

The present invention is to solve the above problems, forming a pad open portion after forming the microlens, and prevents the progressive corrosion occurring on the metal pad to improve the reliability and yield of the device of the CMOS image sensor The purpose is to provide a manufacturing method.

According to another aspect of the present invention, there is provided a method of manufacturing a CMOS image sensor. Forming a pad opening by forming a protective film on the entire surface and selectively removing the protective film to expose the surface of the metal pad, forming an insulating film on the front surface of the substrate including the pad opening, and the active region Forming a color filter layer on the insulating film, forming a microlens on the color filter layer, and selectively removing the insulating film formed on the pad region of the substrate by a CDE method. do.

Hereinafter, a method of manufacturing the CMOS image sensor according to the present invention will be described in detail with reference to the accompanying drawings.

5A to 5F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 5A, a first insulating film 201 such as a gate insulating film or an interlayer insulating film is formed on the semiconductor substrate 200, and the metal pads 202 of each signal line are formed on the first insulating film 201. To form.

In this case, the metal pad 202 may be formed on the same layer as the same material as each of the gate electrodes 120, 130, and 140 as described with reference to FIG. 2, and may be formed of a different material through a separate contact. It is mostly formed of aluminum (Al).

A protective film 203 is formed on the entire surface of the first insulating film 201 including the metal pad 202. The protective film is formed of an oxide film or a nitride film.

As shown in FIG. 5B, a photosensitive film 204 is formed on the passivation film 203 and exposed and developed using photolithography to expose an upper portion of the metal pad 202. The protective film 203 is selectively etched using the photosensitive film 204 as a mask to form a pad opening 205 in the metal pad 202, and then the photosensitive film 204 is removed.

As shown in FIG. 5C, a second insulating layer 206 is formed on the entire surface of the substrate on which the pad opening 205 is formed.

Here, the second insulating film 206 is formed of a PE (plasma emhancement) oxide film, PE TEOS or PE nitride film, the thickness is about 400 ~ 1000Å.

As shown in FIG. 5D, the first planarization layer 207 is deposited on the entire surface of the second insulating layer 206, and the photo planar etching process using a mask is used to leave only portions except the metal pad portion.

A blue color filter layer 208, a green color filter layer 209, and a red color filter layer 210 are sequentially formed on the first planarization layer 207 corresponding to each photodiode region (not shown in the figure).

Here, in each of the color filter layer forming methods, the color photosensitive material is coated and the color filter layers are formed by a photolithography process using a separate mask.

As shown in FIG. 5E, the second planarization layer 212 is formed on the entire surface of the substrate including each of the color filter layers 208, 209, and 210, and remains only in a region except the metal pad part by a photolithography process using a mask. do.

As shown in FIG. 5F, a microlens material layer is deposited on the second planarization layer 212, and then selectively patterned, and a reflow process is performed on each of the color filter layers 208, 209, and 210. Corresponding hemispherical microlenses 213 are formed.

In this case, the pad opening 205 is exposed by removing the second insulating film 206 on the upper portion of the metal pad 202 by a chemical downstream (or dry) etching (CDE) method without adding a separate mask. Let's do it.

Then, the probe resistance of each metal pad 202 of the CMOS image sensor manufactured as described above is checked to check contact resistance. If there is no abnormality, the external driving circuit and the metal pad are electrically connected to each other.

In the present invention, unlike the RIE in which the plasma is formed and maintained inside the chamber, the CDE method for exposing the pad opening portion 205 is formed through the tube leading to the inside of the chamber and forming the plasma. (etchant) is introduced and etching proceeds.

Therefore, since plasma is formed outside the chamber, plasma damage due to the build-up of ions or electrons is small.

In addition, since the etching occurs by the flow of the pure etchant, the etching method is characterized in that it exhibits isotropic etching characteristics.

A preferred embodiment in the present invention proceeds at 25 ° C., 480 sccm O ₂ , 80 sccm N ₂ , 50 Pa, 700 W.

The plasma source of the present invention is a micro-wave (micro-wave) is generally used for ashing (resin) of the resin (ash).

In the present invention, the embodiment is the same as 25 ℃, 480sccm O ₂ , 350sccm CF ₄ , 50Pa, 700W.

On the other hand, CF ₄ is added to ashing the first planarization layer 207.

6A and 6B are results obtained by comparing the roughness of the surface of the microlens of the conventional and the present invention through SEM analysis.

As shown in FIG. 6A, the conventional method of exposing the pad openings using the RIE method is rough in the surface of the microlens, but as in FIG. 6B, the method of the present invention which exposes the pad openings using the CDE method is micro It can be seen that the surface roughness of the lens is significantly relaxed.

It is determined that the conventional method is caused by a kind of damage caused by ion collision. The surface roughness of the microlens is closely related to the diffuse reflection of incident light. In other words, if the roughness is high, the reflectance is high and the intensity of light transmitted to the photodiode is weakened, thereby degrading the activity of electrons, thereby inhibiting the intensity of the signal, thereby preventing image realization.

Another effect of the present invention is to reduce plasma damage potential by applying equipment with low plasma damage.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

As described above, the method of manufacturing the CMOS image sensor according to the present invention has the following effects.

First, the second insulating film is etched by the CDE method to expose the pad opening, thereby reducing surface roughness of the microlens, thereby reducing diffuse reflection of light.

Second, the plasma damage potential can be reduced by applying a device having a low plasma damage.

Claims (5)

Forming a metal pad in a pad area on the substrate divided into an active area and a pad area; Forming a pad opening by forming a protective film on the entire surface of the substrate including the metal pad and selectively removing the protective film to expose the surface of the metal pad; Forming an insulating layer on a front surface of the substrate including the pad open part using a PE (Plasma Emhancement) oxide film, a PE TEOS (Plasma Emhancement Tetra Ethyl Ortho Silicate) or a PE (Plasma Emhancement) nitride film; Forming a color filter layer on the insulating film in the active region; Forming a microlens on the color filter layer; Plasma formation takes place outside the chamber and induces an etchant through a tube leading into the chamber, whereby microwave is used as a plasma source in a chemical downstream (CDE: Chemical Downstream (or Dry) Etch) method. And selectively removing the insulating film formed on the pad region of the substrate. delete The method of claim 1, wherein the insulating layer is formed to a thickness of 400 μs to 1000 μs. The method of claim 1, wherein the etching of the insulating film by the CDE method is performed under conditions of 25 ° C., 480 sccm O ₂ , 80 sccm N ₂ , 50 Pa, and 700 W. ₃ . delete

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