KR100720233B1 - Semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, which extends a fuse box open area to a center and an edge in the layout of a fuse box of a semiconductor device, thereby preventing the occurrence of an air trap. Disclosed is a technique for enabling it. The present invention is connected to the semiconductor chip and the epoxy process and formed on top and bottom of the substrate region on the plane, and the epoxy region formed in the epoxy region, respectively, from the center region to the upper and lower edges of the semiconductor chip than the epoxy region. It includes a fuse box open region extending in the long axis direction.

Description

Semiconductor device

1 and 2 are a plan view showing a fuse box in a conventional semiconductor device.

3 is an enlarged view of the fuse of FIGS. 1 and 2;

4 is an enlarged view of the fuse open area of FIG. 3;

Fig. 5 is a diagram for explaining a problem in the fix open region of a conventional semiconductor device.

6 is a plan view showing a fuse box of a semiconductor device according to the present invention.

7 is a view showing a fixed open region of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and in particular, a technology for preventing an air trap of a fuse box during die attach in an assembly process of a semiconductor device.

In general, in the manufacture of a semiconductor device, especially a memory device, if any one of a number of fine cells is defective, the semiconductor device does not function as a memory and thus is treated as a defective product. However, even though only a few cells in the memory have failed, discarding the entire device as defective is an inefficient method of processing in terms of yield.

Therefore, the current yield is improved by replacing a defective cell in which a defect has occurred by using a redundancy cell previously installed in the memory device.

A repair method using a spare cell typically includes a defective cell in which defects are generated by preliminarily providing a spare word line provided to replace the normal word line and a spare bit line provided to replace the normal bit line for each cell array. The normal word line or the normal bit line is replaced with a spare word line or a spare bit line.

In detail, when a defect cell is selected through a test after wafer processing is completed, a program is executed in an internal circuit to replace an address corresponding to the defective cell with an address of a spare cell. Therefore, when the address signal corresponding to the defective cell is input in actual use, the data of the spare cell replaced in correspondence with the defective cell is accessed.

The most widely used method as described above is to blow the fuse with a laser beam and blow to replace the path of the address. Accordingly, a conventional memory device includes a fuse unit capable of replacing an address path by irradiating a blown laser with a fuse. Here, the fuse part is constituted by a fuse which is a wiring broken by laser irradiation, and a fuse box which is a region surrounded by the broken part.

The fuse part includes a plurality of fuse sets, and one fuse set may replace one address path. The number of fuse sets provided in the fuse unit is determined corresponding to the number of spare word lines or spare bit lines included in the memory device.

1 and 2 are plan views illustrating a fuse box in a conventional semiconductor device.

An epoxy area 3 is formed at an upper portion and a lower portion of the semiconductor chip with respect to the substrate region 4, and a fuse box 1 is formed at an intermediate region of the epoxy region 3. Here, each fuse box 1 includes a plurality of fuses 2.

3 is an enlarged view of each fuse 2 in the fuse box 1 of FIG. 2, and FIG. 4 is an enlarged view of an open area of each fuse 2 in the fuse box 1 of FIG. 3.

The semiconductor device mainly includes a fabrication (FAB) process of repeatedly forming a circuit pattern set on a silicon substrate to form cells having an integrated circuit, and an assembly for packaging the substrate on which the cells are formed in chips. (Assembly) process. In addition, an electrical die sorting (EDS) process is performed between the fabrication process and the assembly process to inspect the electrical characteristics of the cells formed on the substrate.

However, in the conventional semiconductor device, the fuse box 1 is isolated in the middle of a chip in a DC (Diamond Chip) technology. That is, the fuse box 1 is formed in the inner center region of the epoxy region 3 so as not to contact the upper and lower regions of the chip.

Accordingly, since a path through which air escapes to the outside of the chip is not formed when a void occurs during die attach in the above-described assembly process of the chip, a portion of the fuse box 1 as shown in FIG. Air trap is generated in the air.

If a small impact or environmental change occurs due to the air trap, there is a problem that a crack occurs in the package solder resist in the progress of reliability (T / C).

SUMMARY OF THE INVENTION The present invention was created to solve the above problems, and extends a fuse box open area to a center and an edge when a fuse box is laid out in a semiconductor device, thereby allowing air to escape. The purpose is to prevent the generation of air traps by forming a path.

The semiconductor device of the present invention for achieving the above object is an epoxy region which is connected to the semiconductor chip by the epoxy process and formed on the top and bottom with respect to the substrate region on a plane; And a fuse box open region formed in the epoxy region and extending in the long axis direction longer than the epoxy region from the center region to the upper and lower edges of the semiconductor chip.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

6 is a plan view illustrating a fuse box in the semiconductor device according to the present invention.

In the present invention, an epoxy region 30 is formed on the upper and lower portions of the semiconductor chip, based on the substrate region 40.

The open area of the fuse box 10 extends from the middle region of the epoxy region 30 to the center connected to the substrate region 40 of the chip and the upper / lower edge region of the chip. Is formed.

Here, each fuse box 10 includes a plurality of fuses 20, and the fuses 20 are opened to the same width as the fuse box 10. At this time, the width of the fuse box 10 may be set to such an extent that a problem does not occur when trimming the fuse 20. In the formation of the open area of the fuse box 10, it is preferable to lay out a range from the center area of the chip to the range where the substrate area 40 is not opened.

Accordingly, when the fuse box 10 or the fuse open area is extended to the edge of the chip, air generated during the epoxy process may escape from the chip. Done.

7 is a view showing a fix open region of a semiconductor device according to the present invention.

Therefore, in the present invention, as shown in FIG. 7, epoxy voids are generated by forming a path through which the fuse box 10 opens in the long axis to the edge region of the chip so that air escapes to the outside of the chip. To improve.

Accordingly, in the assembly process of packaging the semiconductor substrate on which the cells are formed, the air trap is prevented from occurring in the fuse box 10 during the die attach process. Do it. Here, the die attach is a process for attaching the chip and the substrate region 40, and the material used as the adhesive is epoxy.

As described above, the present invention extends a fuse box open area to a center and an edge in the layout of a fuse box in a semiconductor device to form a path through which air escapes, thereby forming an air trap. Provides the effect of preventing the generation of voids by (Air Trap).

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (3)

An epoxy region connected to the semiconductor chip by an epoxy process and formed on the top and the bottom of the substrate region on a plane; And And a fuse box open region formed in each of the epoxy regions and extending in a long axis direction from the center region of the semiconductor chip to an upper edge and a lower edge than the epoxy region. The semiconductor device of claim 1, wherein the fuse box open area is opened to a range where the substrate area is not opened in the center area. The semiconductor device of claim 1, wherein the fuse box open area includes a plurality of fuses that are open to the same width as the fuse box.

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