KR100718997B1 - Electrostatic discharge protection circuits - Google Patents

Abstract

The present invention relates to an electrostatic discharge protection circuit, and more particularly, to an electrostatic discharge protection circuit for protecting an integrated circuit from electrostatic discharge.

The present invention is connected between a first power supply line for supplying a first voltage to the integrated circuit and a second power supply line for supplying a second voltage less than the first voltage and the electrostatic detection unit for detecting the static electricity, and the static electricity An electrostatic discharge control unit providing a discharge path of the electrostatic discharge shunt unit, and connected between the electrostatic detection unit and the electrostatic discharge shunt unit to control on and off of the electrostatic discharge shunt unit according to an output signal of the electrostatic detection unit; And an active resistor connected between the first power line and the electrostatic discharge control unit to keep the electrostatic discharge shunt off while the first voltage is applied to the first power line.

According to the present invention, while reducing the size of the integrated circuit, it is effective to protect the integrated circuit from electrostatic discharge, to ensure the stability of the operation of the integrated circuit, and to reduce the power consumption for driving the integrated circuit. .

Static electricity detector, electrostatic discharge shunt, electrostatic discharge controller, active resistor

Description

Electrostatic Discharge Protection Circuits. {Electrostatic Discharge Protection Circuits}

1 is a view showing a conventional electrostatic discharge protection circuit using the snapback characteristics.

2 is a view for explaining the snapback characteristic of FIG.

3 is a view showing another conventional electrostatic discharge protection circuit.

4 is a diagram showing an electrostatic discharge protection circuit using a conventional active resistance element.

5 is a view showing a problem of the electrostatic discharge protection circuit of FIG.

6 is a view showing an electrostatic discharge protection circuit according to an embodiment of the present invention.

***** Brief description of the drawings *****

Static electricity detector 61, electrostatic discharge shunt 62

Electrostatic discharge control unit 63, active resistor unit 64

The present invention relates to an electrostatic discharge protection circuit, and more particularly, to an electrostatic discharge protection circuit for protecting an integrated circuit from electrostatic discharge.

Electrostatic discharges are caused by electrostatic charges that occur when two different electrical objects come into contact with each other to exchange charges, and then separate and fall while generating a potential difference.

Electrostatic discharge in everyday life can be unpleasant to humans, but it can cause serious problems for semiconductor integrated circuits. Electrostatic discharge (ETM) in the integrated circuit may occur due to the electrostatic discharge generated in the integrated circuit, and the high voltage and high current generated may cause a short or low impedance state between the transistor terminals. In particular, a MOSFET (metal-oxide semiconductor field effect transistor) has a high risk of dielectric breakdown, so a method of minimizing the effects of electrostatic discharge is required.

Considering the trend of high integration and complexity of integrated circuits, it is essential to protect the integrated circuits from electrostatic discharge. One of such protection means is provided between the power line and the ground line of the integrated circuit to prevent overcurrent caused by electrostatic discharge. It is common to use a power clamping method that shunts.

1 is a diagram illustrating a conventional electrostatic discharge protection circuit using a snapback characteristic, and FIG. 2 is a diagram for explaining the snapback characteristic of FIG. 1.

Briefly, the operation of FIG. 1 is as follows.

First, in a normal state in which the pulse is not applied due to the electrostatic discharge, the voltage Vg applied to the gate terminal of the NMOS transistor MN becomes 0 volt (V) so that the NMOS transistor MN is turned off. In this state, no current flows through the NMOS transistor MN.

Next, when a pulse due to electrostatic discharge is applied to the VDD line, the power line, the VDD line, which is the power line, makes an AC transition in the DC state. When a voltage of 1000V and a current of about 1A are instantaneously introduced through the power supply line VDD line due to electrostatic discharge, the gate terminal voltage (Vg) of the NMOS transistor (MN) is RC Time Constant and RC. The transition is caused by the impedance ratio of. As the voltage of the VDD line, which is the power line, is transitioned, when the NMOS transistor MN is weakly turned on by the voltage applied to the capacitor C, the snapback of the NMOS transistor MN is performed. ) Occurs at a low Vds voltage (see Figure 2). That is, as the voltage of the VDD line increases, the Vds increases accordingly, and when Vds becomes the same as the snapback voltage Vsnapback of the NMOS transistor MN, the NMOS transistor MN lowers Vds and increases more current. It enters a snapback mode that can flow, and withstands voltage and current from electrostatic discharge.

3 is a view showing another conventional electrostatic discharge protection circuit.

The operation of FIG. 3 is not significantly different from the operation of FIG. However, there is an inverter between the connection terminal of the resistor R and the capacitor C and the gate terminal of the NMOS transistor MN, and when the pulse due to the electrostatic discharge is applied to the VDD line, the inverter (Inverter) ), The output voltage of the NMOS transistor MN is strongly turned on while following the voltage of the VDD line. In this case, since the voltage Vg applied to the gate terminal of the NMOS transistor MN is much higher than that of FIG. 1, a similar amount of current can be obtained without using the snapback characteristic of the NMOS transistor MN. The advantage is that it can flow at low Vds voltage.

An important factor in the design of the conventional static discharge protection circuit described above is to determine the RC Time Constant value and to determine how many static discharge protection circuits to integrate.

If the RC Time Constant value is too small, the NMOS transistor (MN) does not flow enough current through the electrostatic discharge, which damages the internal circuit of the integrated circuit due to the voltage and current caused by the electrostatic discharge. Will receive.

On the contrary, if the RC Time Constant value is too large, it reacts to low frequency noise generated during normal operation of the integrated circuit, that is, when voltage is applied to the VDD line, which is a power line. Positive current flows through the NMOS transistor MN, making the integrated circuit unstable in normal operation.

On the other hand, if the width of the pulse applied to the power supply line VDD line is 150 nsec, the RC Time Constant value is 20 μsec, and the capacitance of the capacitor C is 10 pF. ) Should be 2M Ohm.

In addition, assuming that 5 mA flows through one NMOS transistor (MN) when a pulse due to electrostatic discharge is applied to the VDD line, which is a power line, 200 NMOS transistors (MN) are required to flow a current of 1A momentarily. Do. Even when using an NMOS transistor with four fingers, 50 multi-finger NMOS transistors are required, and each requires 50 capacitors and resistors. Accordingly, there is a problem that the chip size of the integrated circuit becomes large.

In order to reduce the chip size of the integrated circuit, a method of using an active resistor as shown in FIG. 4 may be devised.

4 is a diagram illustrating an electrostatic discharge protection circuit using a conventional active resistor.

As shown in FIG. 4, it is possible to reduce the size of the entire integrated circuit by using the first PMOS transistor MP1 which is an active resistor.

However, as shown in FIG. 5, in the normal operation of the integrated circuit, that is, a driving voltage for driving the integrated circuit is applied to the VDD line, which is a power line, so that the voltage of the VDD line is changed from ground to a desired voltage level. During the transition, when the voltage difference Vgs between the gate terminal and the source terminal of the first PMOS transistor MP1 is not greater than the threshold voltage Vth of the first PMOS transistor MP1, the first PMOS transistor MP1 is turned off. Vrc continues to remain at the ground level even though the voltage of the VDD line rises from ground.

When Vrc is the ground level, the output voltage Vg of the inverter rises, as shown in FIG. 5. In this case, the first NMOS transistor MN1 is weakly turned on so that the leakage current Ids flow.

When the number of first NMOS transistors MN1 is 50 per one integrated circuit chip, the total leakage current may be several mA in the process of driving one integrated circuit chip, resulting in a problem of unstable driving of the integrated circuit. will be.

SUMMARY OF THE INVENTION The present invention for solving this problem aims at providing an electrostatic discharge protection circuit for an integrated circuit that reduces the size of the integrated circuit and efficiently protects the integrated circuit from electrostatic discharge.

It is also an object of the present invention to provide an electrostatic discharge protection circuit of an integrated circuit which ensures the stability of the operation of the integrated circuit.

In addition, an object of the present invention is to provide an electrostatic discharge protection circuit which reduces power consumption for driving an integrated circuit.

An electrostatic discharge protection circuit according to an embodiment of the present invention for achieving the technical problem is a first power line for supplying a first voltage to the integrated circuit and a second for supplying a second voltage less than the first voltage. An electrostatic detector for detecting static electricity connected between power lines, an electrostatic discharge shunt for providing a discharge path of the static electricity, and a connection between the electrostatic detector and the electrostatic discharge shunt, according to an output signal of the electrostatic detector. An electrostatic discharge control unit for controlling the on / off of the electrostatic discharge shunt unit and connected between the first power line and the electrostatic discharge control unit to hold the electrostatic discharge shunt unit off while the first voltage is applied to the first power line. It includes an active resistor unit.

The electrostatic detector includes a first PMOS transistor and a capacitor, a source terminal of the first PMOS transistor is connected to the first power line, a gate terminal of the first PMOS transistor is connected to the second power line, A drain end of the first PMOS transistor is connected to one end of the capacitor, and the other end of the capacitor is connected to the second power line.

The electrostatic discharge controller is an inverter in which the second PMOS transistor and the first NMOS transistor are connected in parallel.

The gate terminal of the second PMOS transistor and the first NMOS transistor are commonly connected to the drain terminal of the first PMOS transistor and one end of the capacitor, and the drain terminal of the second PMOS transistor and the first NMOS transistor are the electrostatic discharge. It is characterized in that the common connection with the shunt portion.

The active resistor unit is a third PMOS transistor, a source terminal of the third PMOS transistor is connected to the first power line, and gate and drain terminals of the third PMOS transistor are commonly connected to a source terminal of the second PMOS transistor. It is characterized by.

The electrostatic discharge shunt portion is a second NMOS transistor, a gate end of the second NMOS transistor is commonly connected with a drain end of the second PMOS transistor and the first NMOS transistor, and a drain end of the second NMOS transistor is connected to the first NMOS transistor. And a source terminal of the second NMOS transistor is connected to the second power line.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention;

6 is a view showing an electrostatic discharge protection circuit according to an embodiment of the present invention.

As shown in FIG. 6, an electrostatic discharge protection circuit according to an embodiment of the present invention may include a first power line for supplying a first voltage to an integrated circuit and a second voltage for supplying a second voltage smaller than the first voltage. A static electricity detector 61 connected between two power lines to detect static electricity, an electrostatic discharge shunt 62 for providing a discharge path of the static electricity, and a connection between the static electricity detector and the static electricity discharge shunt The first voltage is applied to the first power line by being connected between the electrostatic discharge control unit 63 for controlling the on / off of the electrostatic discharge shunt part and the first power line and the electrostatic discharge control unit according to the output signal of the detector. And an active resistor portion 64 to keep the electrostatic discharge shunt portion off.

The static electricity detector 61 is connected between the first power line VDD for supplying a first voltage to the integrated circuit and the second power line VSS for supplying a second voltage smaller than the first voltage, thereby discharging the static electricity. Due to the detection of static electricity flowing from the outside.

The static electricity detector 61 includes a first PMOS transistor MP1 and a capacitor C. The source terminal of the first PMOS transistor MP1 is connected to the first power line VDD and the first PMOS transistor MP1 The gate terminal of the MP1 is connected to the second power line VSS, the drain terminal of the first PMOS transistor MP1 is connected to one end of the capacitor C, and the other end of the capacitor C is connected to the second power line (VSS). VSS) is preferably to be connected.

When an excessive amount of current flows into the first power line VDD instantaneously due to the electrostatic discharge, the static electricity detector 61 passes to the first PMOS transistor MP1 and the capacitor C serving as active resistors. The capacitor C is momentarily shorted by the configured low pass filter, and the voltage at the common connection terminal of the drain terminal of the first PMOS transistor MP1 and the one end of the capacitor C is connected to the second power line VSS. Transition to a low level, i.e.

The electrostatic discharge control unit 63 is connected between the electrostatic detection unit 61 and the electrostatic discharge shunt unit 62 to be described later to control the on / off of the electrostatic discharge shunt unit 62 according to the output signal of the static electricity detection unit 61. .

The electrostatic discharge control unit 63 is an inverter in which the second PMOS transistor MP2 and the first NMOS transistor MN1 are connected in parallel, and the gate terminal of the second PMOS transistor MP2 and the first NMOS transistor MN1 has a first terminal. The drain terminal of the PMOS transistor MP1 is connected in common with one end of the capacitor C, and the drain terminals of the second PMOS transistor MP2 and the first NMOS transistor MN1 are connected in common with the electrostatic discharge shunt part 62. It is preferable.

In this configuration, when the low level output signal is input from the static electricity detector 61, the second PMOS transistor MP2 is turned on so that the drain terminal of the second PMOS transistor MP2 is connected to the first power line VDD. The high level is caused by the current caused by the electrostatic discharge.

The active resistor unit 64 is connected between the first power line VDD and the electrostatic discharge control unit 63 so that the static electricity discharge shunt is applied to the first power line VDD while the first voltage for the normal driving of the integrated circuit is applied. The portion 62 is kept off to prevent leakage current through the electrostatic discharge shunt portion 62.

The active resistor unit 64 is a third PMOS transistor MP3, a source terminal of the third PMOS transistor MP3 is connected to the first power line VDD, and a gate terminal and a drain of the third PMOS transistor MP3 are connected to each other. It is preferable that the stage be connected to the source terminal of the second PMOS transistor MP2 in common.

In this manner, the gate terminal of the electrostatic discharge shunt part 62, which will be described later, is used by using the third PMOS transistor MP3 while the first voltage for the normal driving of the integrated circuit is applied to the first power line VDD. Lower the voltage level of

That is, in the electrostatic discharge protection circuit according to the present invention, the threshold voltages Vth and MP3 of the third PMOS transistor MP3 and the saturation voltages Vdsat and MP3 are compared with the conventional case shown in FIG. 4. The voltage having the voltage level lowered by this is applied to the gate terminal of the electrostatic discharge shunt part 62. This will be described in more detail when describing the static discharge shunt unit 62.

The electrostatic discharge shunt part 62 provides a discharge path of static electricity.

The electrostatic discharge shunt part 62 is the second NMOS transistor MN2, and the gate terminal of the second NMOS transistor MN2 is commonly connected to the drain terminals of the second PMOS transistor MP2 and the first NMOS transistor MN1. The drain terminal of the second NMOS transistor MN2 may be connected to the first power line VDD, and the source terminal of the second NMOS transistor MN2 may be connected to the second power line VSS.

As described above, when an excessive amount of current flows into the first power line VDD instantaneously due to electrostatic discharge, a high level signal is applied to the gate terminal of the second NMOS transistor MN2 as described above. As the second NMOS transistor MN2 is turned on, a communication path of the current according to the electrostatic discharge is formed from the first power line VDD to the second power line VSS, thereby shunting the current according to the electrostatic discharge. Protect the internal circuit of the circuit.

Meanwhile, while the first voltage for the normal driving of the integrated circuit is applied to the first power line VDD, the threshold voltage of the third PMOS transistor MP3 is applied to the gate terminal of the second NMOS transistor MN2 at the first voltage. The second NMOS transistor MN2 is maintained in an off state by supplying a voltage obtained by subtracting Vth, MP3, the saturation voltages Vdsat, MP3, and the threshold voltages Vth, MP2 of the second PMOS transistor MP2.

Therefore, the flow of the leakage current through the second NMOS transistor MN2 is prevented while the first voltage for the normal driving of the integrated circuit is applied.

As described in detail above, the present invention reduces the size of the integrated circuit, while efficiently protecting the integrated circuit from electrostatic discharge, ensuring the stability of the operation of the integrated circuit, and reducing the power consumption for driving the integrated circuit. To provide an electrostatic discharge protection circuit.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be construed as being included in the scope of the present invention.

According to the present invention as described in detail above, while reducing the size of the integrated circuit, there is an effect of efficiently protecting the integrated circuit from electrostatic discharge.

In addition, there is an effect of ensuring the stability of the operation of the integrated circuit.

In addition, there is an effect of reducing the power consumption for driving the integrated circuit.

Claims (6)

A static electricity detector connected between a first power supply line for supplying a first voltage to an integrated circuit and a second power supply line for supplying a second voltage smaller than the first voltage to detect static electricity; An electrostatic discharge shunt to provide a discharge path for the static electricity; An electrostatic discharge control unit connected between the static electricity detection unit and the electrostatic discharge shunt unit to control on / off of the electrostatic discharge shunt unit according to an output signal of the static electricity detection unit; And An active resistor connected between the first power line and the electrostatic discharge controller to hold the electrostatic discharge shunt off while the first voltage is applied to the first power line; Electrostatic discharge protection circuit comprising a. According to claim 1, The static electricity detector includes a first PMOS transistor and a capacitor, A source terminal of the first PMOS transistor is connected to the first power line, A gate terminal of the first PMOS transistor is connected to the second power line, The drain terminal of the first PMOS transistor is connected to one end of the capacitor, And the other end of the capacitor is connected to the second power line. The method of claim 2, The electrostatic discharge control circuit is an electrostatic discharge protection circuit, characterized in that the inverter including a second PMOS transistor and the first NMOS transistor. The method of claim 3, wherein A gate terminal of the second PMOS transistor and the first NMOS transistor are commonly connected to a drain terminal of the first PMOS transistor and one end of the capacitor, And a drain terminal of the second PMOS transistor and the first NMOS transistor are commonly connected to the electrostatic discharge shunt unit. The method of claim 4, wherein The active resistor unit is a third PMOS transistor, A source terminal of the third PMOS transistor is connected to the first power line, And a gate terminal and a drain terminal of the third PMOS transistor are commonly connected to a source terminal of the second PMOS transistor. The method according to any one of claims 1 to 5, The electrostatic discharge shunt portion is a second NMOS transistor, A gate terminal of the second NMOS transistor is commonly connected to a drain terminal of the second PMOS transistor and the first NMOS transistor, The drain terminal of the second NMOS transistor is connected to the first power line, And a source terminal of the second NMOS transistor is connected to the second power line.

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