KR100718800B1 - Method for procuring contact area of flash device - Google Patents
Method for procuring contact area of flash device Download PDFInfo
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- KR100718800B1 KR100718800B1 KR1020050131545A KR20050131545A KR100718800B1 KR 100718800 B1 KR100718800 B1 KR 100718800B1 KR 1020050131545 A KR1020050131545 A KR 1020050131545A KR 20050131545 A KR20050131545 A KR 20050131545A KR 100718800 B1 KR100718800 B1 KR 100718800B1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 abstract description 6
- 238000010849 ion bombardment Methods 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000015654 memory Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 반도체소자의 컨택영역을 확보하는 방법에 관한 것으로서, 본 발명은 기판상에 평행하게 복수의 게이트폴리를 형성하는 단계와, 상기 게이트폴리 양측에 게이트측벽을 형성하는 단계 및 상기 게이트측벽을 CDE(chemical dry etching:화학적건식식각)로 등방성식각하는 단계를 포함하는 것을 특징으로 하고, 본 발명에 의하면 CDE를 이용하여 게이트측벽을 등방성 식각을 함으로써 게이트폴리 간의 공간을 확보할 수 있고, 이온 충격이 없는 CDE 기법을 이용함으로써 이온 충격에 의한 데미지가 없으므로 게이트절연막의 열화에 영향을 주지 않는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for securing a contact region of a semiconductor device. Forming a sidewall and isotropically etching the gate sidewall by chemical dry etching (CDE). According to the present invention, the gate sidewall isotropically etched using the CDE. Interstitial Since the space can be secured and the CDE technique without ion bombardment is used, there is no damage caused by ion bombardment, and thus there is no effect on deterioration of the gate insulating film.
CDE(chemical dry etching), 반도체소자, 컨택영역 CDE (chemical dry etching), semiconductor device, contact area
Description
도 1은 종래기술에 의한 반도체소자의 평면도이다.1 is a plan view of a semiconductor device according to the prior art.
도 2는 본 발명의 실시예에 따른 반도체소자의 평면도이다.2 is a plan view of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 설명>Description of the main parts of the drawing
120: 활성영역 130: 게이트측벽120: active area 130: gate side wall
140: 게이트폴리 200: 반도체소자140: gate poly 200: semiconductor device
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 반도체소자의 컨택영역을 확보하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for securing a contact region of a semiconductor device.
일반적으로 반도체소자는 드라이브 전원이 공급되지 않아도 셀에 기록된 데이터가 소멸하지 않고 남아 있다. 비휘발성 메모리들 중에서도 플래시 EEPROM(Electrically Erasable Programmable Read Only Memory)는 전기적으로 셀의 데이터를 일괄적으로 또는 섹터 단위로 소거하는 기능이 있기 때문에 컴퓨터 및 메모리 카드에 널리 사용되고 있다. In general, a semiconductor device remains without disappearing data written in a cell even when a drive power is not supplied. Among nonvolatile memories, flash electrically erasable programmable read only memory (EEPROM) is widely used in computers and memory cards because it electrically erases data in a cell or sectorally.
이러한 반도체소자는 셀과 비트 라인의 연결 상태에 따라 NAND형과 NOR형으로 구분되며 NOR형 플래시 메모리는 1개의 비트 라인에 2개 이상의 셀 트랜지스터가 병렬로 연결된 형태이며, 상기 NAND형 플래시 메모리는 1개의 비트 라인에 2개 이상의 셀 트랜지스터가 직렬로 연결된 형태이다.Such semiconductor devices are classified into NAND and NOR types according to a connection state between a cell and a bit line. A NOR flash memory has a form in which two or more cell transistors are connected in parallel to one bit line. Two or more cell transistors are connected in series to four bit lines.
도 1은 종래기술에 의한 반도체소자(100)의 평면도이다.1 is a plan view of a
종래기술에 의한 반도체소자(100)는 활성화영역(20), 게이트폴리(40) 및 게이트측벽(30)을 포함한다.The
그런데, 종래기술에 의할 경우 반도체소자의 집적도가 증가함에 따라 활성화영역(20)과 컨택플러그(미도시)간의 공간의 부족으로 인해 컨택영역(contact area)(A)의 감소로 인한 반도체소자의 전기적 특성이 저하하는 문제가 발생한다.However, according to the related art, as the degree of integration of the semiconductor device increases, the semiconductor device may be reduced due to a decrease in the contact area A due to the lack of a space between the
또한, 종래기술에 의할 경우, 반도체소자 제품의 수율 및 신뢰성에 영향을 미칠 수 있는 중요한 인자인 컨택영역의 확보하기 위해 게이트폴리(40)간의 공간(space)을 증가시키면 집적도가 떨어지기 때문에 기판의 크기가 커지며 생산성이 떨어지는 문제점이 있다.In addition, according to the related art, if the space between the
본 발명은 게이트폴리 사이의 공간을 넓히지 않으면서 컨택영역을 확보할 수 있는 플래시메로리의 컨택영역 확보방법을 제공함에 그 목적이 있다.An object of the present invention is to provide a method for securing a contact region of a flash memory capable of securing a contact region without increasing the space between the gate polys.
상기의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 컨택영역 확보방법은 기판상에 평행하게 복수의 게이트폴리를 형성하는 단계와, 상기 게이트폴리 양측에 게이트측벽을 형성하는 단계 및 상기 게이트측벽을 CDE(chemical dry etching:화학적건식식각)로 등방성식각하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method for securing a contact region of a semiconductor device, the method comprising: forming a plurality of gate polys on a substrate in parallel, forming gate side walls on both sides of the gate polys, and forming the gate side walls. And isotropic etching with chemical dry etching (CDE).
또한, 상기 CDE 식각하는 단계는 20~30℃ 온도 및 50~80Pa의 압력에서 600~800W의 전력을 가하고, CF4 가스를 300~500sccm, N2가스를 50~100sccm, O2 가스를 300~400sccm을 각각 공급하는 조건에서 진행할 수 있다.In addition, the CDE etching step is applied to the power of 600 ~ 800W at a temperature of 20 ~ 30 ℃ temperature and 50 ~ 80Pa, CF 4 300 to 500 sccm for gas, N 2 50 to 100 sccm for gas, O 2 The gas may be carried out under the conditions of supplying 300 to 400 sccm, respectively.
또한, 상기 게이트측벽을 형성하는 단계는 상기 게이트폴리 양측에 질화막을 형성할 수 있다.In the forming of the gate side wall, a nitride film may be formed on both sides of the gate poly.
이와 같은 본 발명에 의하면 CDE를 이용하여 게이트측벽을 등방성 식각을 함으로써 게이트폴리 간의 공간을 확보할 수 있고, 이온 충격이 없는 CDE 기법을 이용함으로써 이온 충격에 의한 데미지가 없으므로 게이트절연막의 열화에 영향을 주지 않는 장점이 있다.According to the present invention, the gate side wall isotropically etched by using CDE, so that Since the space can be secured and the CDE technique without ion bombardment is used, there is no damage due to ion bombardment, which does not affect the deterioration of the gate insulating layer.
이하, 본 발명의 실시예에 따른 반도체소자의 컨택영역 확보방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method for securing a contact region of a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 실시예에 따른 반도체소자의 평면도이다.2 is a plan view of a semiconductor device according to an embodiment of the present invention.
본 발명의 실시예에 따른 반도체소자의 컨택영역 확보방법(200)은 게이트폴리를 형성하는 단계와, 게이트측벽을 형성하는 단계 및 상기 게이트측벽을 식각하는 단계를 포함할 수 있다.The
우선, 게이트폴리를 형성하는 단계는 기판상에 평행하게 복수의 게이트폴리(140)를 형성하는 단계이다.First, forming the gate poly is forming the plurality of
다음으로, 게이트측벽을 형성하는 단계는 상기 게이트폴리(140) 양측에 게이트측벽(130)을 형성하는 단계이다.Next, forming the gate side wall is a step of forming the
이때, 상기 게이트측벽(130)을 형성하는 단계는 상기 게이트폴리(140) 양측에 질화막을 형성할 수 있다.In this case, in the forming of the
다음으로, 상기 게이트측벽(130)을 식각하는 단계는 상기 게이트측벽(130)을 CDE에 의해 등방성식각하는 단계이다.Next, the etching of the
이때, 상기 CDE 식각하는 단계는 20~30℃ 온도 및 50~80Pa의 압력에서 600~800W의 전력을 가하고, CF4 가스를 300~500sccm, N2가스를 50~100sccm, O2 가스를 300~400sccm을 각각 공급하는 조건에서 진행할 수 있다.At this time, the step of etching the CDE applying a power of 600 ~ 800W at a temperature of 20 ~ 30 ℃ temperature and 50 ~ 80Pa, CF 4 300 to 500 sccm for gas, N 2 50 to 100 sccm for gas, O 2 The gas may be carried out under the conditions of supplying 300 to 400 sccm, respectively.
예를 들어, 상기 CDE 식각하는 단계는 25℃ 온도 및 70Pa의 압력에서 700W의 전력을 가하고, CF4 가스를 400sccm, N2가스를 80sccm, O2 가스를 320sccm을 각각 공급하는 조건에서 진행하였다.For example, the CDE etching may be performed by applying 700 W of power at a temperature of 25 ° C. and a pressure of 70 Pa, and CF 4 400sccm for gas, N 2 80sccm for gas, O 2 The gas was run under the conditions of feeding 320 sccm, respectively.
상기 예의 조건에서 CDE 식각이 진행된 경우, 게이트측벽인 실리콘 나이트라이드(SiN)의 식각속도는 1500Å/m 이고, 균일도는 1% 내외로 상당히 안정적인 결과를 보였다.In the case of CDE etching under the conditions of the above example, the etching rate of silicon nitride (SiN), which is the gate sidewall, was 1500 mW / m, and the uniformity was about 1%.
본 발명에 따른 실시예에서 게이트측벽을 약 500 ~ 700 Å만 식각해도 충분한 컨택영역(B)을 확보할 수 있는 효과가 있다. In the embodiment of the present invention, even if the gate side wall is etched by only about 500 to 700 mm, sufficient contact area B can be secured.
또한, 본 발명의 실시예에 따른 반도체소자의 컨택영역 확보방법은 게이트측벽의 식각 공정시 화학적 건식 식각(CDE) 공정을 적용하기 때문에 종래 플라즈마에 의한 건식식각공정 또는 습식용액을 이용한 습식식각시 발생되는 문제점을 방지한다. In addition, in the method of securing a contact region of a semiconductor device according to an embodiment of the present invention, a chemical dry etching (CDE) process is applied during an etching process of a gate side wall, so that a dry etching process using a plasma or a wet etching process using a wet solution occurs. Prevent problems.
즉, CDE 공정은 플라즈마 발생 부분과 기판과의 거리가 일반적인 플라즈마 건식식각 방법에 비해 멀고, 기판에 바이어스 전원을 걸어주지 않기 때문에 플라즈마에 포함된 래디컬(radical)만이 실질적으로 기판에 도달하게 되고 실제의 게이트측벽의 식각작용은 래디컬의 화학 작용에 의존하므로, 등방성식각이 이루어진다. That is, in the CDE process, the distance between the plasma generating part and the substrate is far greater than that of the general plasma dry etching method, and since only the radicals included in the plasma actually reach the substrate since the bias power is not applied to the substrate. Since the etching of the gate sidewall depends on the chemical action of the radical, isotropic etching is performed.
따라서, 플라즈마에 함유되는 여기된 이온 등에 의한 기판상에 도달하는 것이 억제되므로 플라즈마 이온에 의한 식각손상이 많이 줄어들면서 반도체소자의 컨택영역을 확보하는 효과가 있다.Therefore, since reaching of the substrate by the excited ions or the like contained in the plasma is suppressed, the etching damage caused by the plasma ions is greatly reduced, thereby securing the contact region of the semiconductor device.
이상에서 설명한 본 발명은 전술한 실시예 및 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경할 수 있다는 것은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and drawings, and it is common knowledge in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those who have
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 컨택영역 확보방법에 의하면, CDE를 이용하여 게이트측벽을 등방성 식각을 함으로써 게이트폴리 간의 공간을 확보할 수 있는 효과가 있다.As described above, according to the method for securing a contact region of a semiconductor device according to the present invention, an isotropic etching of a gate side wall using a CDE is performed between gate polys. It is effective to secure space.
또한, 본 발명에 따르면 이온 충격이 없는 CDE 기법을 이용함으로써 이온 충격에 의한 데미지가 없으므로 게이트절연막의 열화에 영향을 주지 않는 효과가 있다.In addition, according to the present invention, since there is no damage caused by ion bombardment by using the CDE technique without ion bombardment, there is an effect of not affecting the deterioration of the gate insulating film.
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| JP2000349074A (en) * | 1999-06-09 | 2000-12-15 | Matsushita Electric Ind Co Ltd | Dry etching and manufacture of semiconductor device |
| KR20030053588A (en) * | 2001-12-22 | 2003-07-02 | 삼성전자주식회사 | Method of manufacturing semiconductor device including contact pad |
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| JP2000349074A (en) * | 1999-06-09 | 2000-12-15 | Matsushita Electric Ind Co Ltd | Dry etching and manufacture of semiconductor device |
| KR20030053588A (en) * | 2001-12-22 | 2003-07-02 | 삼성전자주식회사 | Method of manufacturing semiconductor device including contact pad |
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