KR100714930B1 - High performance embedded dram technology with strained silicon - Google Patents

Abstract

Semiconductor devices are fabricated in tensile layer- and tensile layer-free regions of the same substrate. For example, a first semiconductor device, such as a memory cell that is a deep trench storage cell, is formed in a tensile layer-free region of a substrate. Tensile layer regions are selectively formed on the same substrate. Second semiconductor devices 66, 68, 70, such as FETs, for example MOSFET logic devices, are formed in the tensile layer region.

Description

High-performance embedded DDR technology with tensile silicon {HIGH PERFORMANCE EMBEDDED DRAM TECHNOLOGY WITH STRAINED SILICON}

The field of the invention relates to semiconductor processing. In particular, the present invention relates to the formation of a semiconductor device in a strained layer region and a strained layer-free region of the same substrate.

Semiconductor devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs) formed in tensile silicon channels, have been shown to provide significant improvements in mobility and performance. Because of the need to maintain high quality defect-free silicon in the DRAM array area while providing tensile silicon in the logic support areas, dense, low-density on the same semiconductor chip for embedded-DRAM applications. Successful integration of high performance tensile silicon logic type MOSFETs with memory such as low-leakage DRAM arrays has not been achieved. Inherently the tensile silicon and the substrate required to create the strain result in very increased silicon dislocation, making it incompatible with low-leak DRAM cells. In addition, semiconductor processes that exceed the predetermined temperature required for DRAM cell formation may not be suitable for the current formation of tensile silicon.

It is desirable to form a high-performance tensile silicon support MOSFET on the same substrate as a low-leakage high-density DRAM cell.

Accordingly, it is an object of the present invention to form a high-performance tensile silicon support MOSFET on the same substrate as a low-leakage high-density DRAM cell.

The present invention discloses a first semiconductor device, such as a low-leakage DRAM cell, formed in a tensile layer-free region of a semiconductor substrate. On the same semiconductor substrate, a tensile layer region is selectively formed in the semiconductor substrate separately from the tensile layer-free region, and a second semiconductor device such as, for example, a high-performance MOSFET is formed in the tensile layer region.

The foregoing and other features of the present invention will become more apparent upon a review of the detailed description given below. In the following description, several drawings will be referenced in the accompanying drawings.

1 through 8 are cross-sectional views of a semiconductor structure appearing during a step according to the method of the present invention.

Referring to FIG. 1, a p-type silicon substrate 10 is provided having memory cells 12 formed in a strained layer-free region of the substrate 10. In FIG. 1, memory cell 12 is a DRAM cell having a trench storage capacitor 14 and a vertical MOSFET 16, which is, for example, commonly assigned US Patent No. 6,225,158 B1, which is incorporated herein by reference. As described in. Although memory cell 12 is shown with trench storage capacitors and vertical MOSFETs 16, memory cells use other types of capacitors and FETs, such as stacked capacitors or planar MOSFETs. It should be noted that it may be formed. In this example, the trench storage capacitor 14 includes a deep trench 18, an n + buried plate 20, a nitride / oxide node dielectric 22, n + polysilicon 24, 26, color Oxide (collar oxide) 28 and n + buried strap diffusion (30). The vertical MOSFET 16 also includes a trench top oxide 32, a gate oxide 34 formed on the sidewalls of the deep trench 18, and an n + polysilicon gate conductor 36. It should be noted that two cells 12 are shown in the array region throughout FIGS. 1-8. However, it should be understood that one or more of any number of memory cells 12 may be formed in the array region.

After forming the memory 12 in the tensile layer-free region of the substrate 10, a tensile layer region is formed in the substrate 10 for subsequent formation of a high performance MOSFET. Thus, because the tensile layer region and the MOSFET are formed after the memory cell is formed, there are no process incompatibility problems such as the high temperature used in the formation of the memory cell.

A thin layer 40 (such as silicon oxide) may comprise a pad film 38 (such as a pad nitride and a pad oxide layer) and the gate conductor 36 shown in FIG. 2. Is laminated to the exposed part of the. Oxide layer 40 acts as an etch stop layer in subsequent processing. Another layer 42 (eg, silicon nitride) is then laminated to oxide layer 40 and a hard mask layer 44 (eg, silicon oxide) is deposited on silicon nitride layer 42.

In order to form the trench 46 as shown in FIG. 2, a block resist (not shown) is patterned into the oxide hard mask layer 44 and the exposure of the layers 38, 40, 42, 44. Reactive ion etching is used to dig into the portion to be etched into the substrate 10 to a desired depth of about 100 nm to 400 nm, more preferably to a depth of about 200 nm. Any residual block resist is removed from the oxide hard mask layer 44 after forming the trench 46.

Referring to FIG. 3, the oxide hard mask layer 44 is removed by standard processes such as reactive ion etching, selective to the silicon and silicon nitride layer 42 exposed by the trench 46. The sidewall surface 50 of the trench 46 has a spacer 48 comprising a material such as silicon oxide or nitride in which silicon or silicon germanium (SiGe) does not agglomerate thereon, as by conventional lamination and RIE. Is formed. A linear graded buffer layer technique can be used to grow SiGe layer 52 with low displacement density (˜10 ⁵ cm −2) in trench 46. Growth conditions are advantageous for selectively forming the SiGe layer 52 on the substrate 10 rather than the spacer 48. Preferably, the SiGe layer 52 epitaxially upwards from the exposed bottom plane 54 of the trench 46 until the SiGe layer 52 is over the top surface of the silicon nitride layer 42. To grow. The overgrown SiGe layer 52 is planarized to the top surface of the silicon nitride layer 42 by a process such as chemical mechanical polishing (CMP). Silicon CMP processes known in the art may be used to planarize the SiGe layer 52.

Optionally, the spacer 48 may be omitted, but the spacer 48 grows epitaxially, with the SiGe layer 52 agglomerated out from the sidewall face 50, thereby leaving both in the SiGe layer 52. Prevents the dog's growth front. Spacer 48 also isolates the strain produced by the SiGe layer 52 of substrate 10 to the support region of the chip to isolate the storage capacitor cells of the array from strain.

Next, as shown in FIG. 4, the top surface 56 of the SiGe layer 52 is subjected to a silicon nitride layer 42 by an etching process such as oxidation leading to reactive ion etching or HF wet etching using SF6 gas. It is selectively recessed to a depth below the upper surface of the. Optionally, the recesses in the SiGe layer 52 can be omitted because the tensile layer that is subsequently grown is very thin.

Referring to FIG. 5, a thin layer 58 of epitaxial silicon is selectively grown on the top surface 56 of the SiGe layer 52. The epitaxial silicon layer 58 is grown to a thickness that is preferably less than about 50 nm, more preferably 2.5 nm to 10 nm. Due to the lattice mismatch between the SiGe layer 52 and the thin silicon layer 58, the epitaxial silicon layer 58 experiences a tensile lattice strain that improves the mobility of the FETs that are subsequently formed. do. After the growth of the epitaxial silicon layer 58, the silicon nitride layer 42 is etched into the oxide layer 40 and epi by a process known in the art, such as a wet etch comprising hot phosphoric acid. It is selectively removed with respect to the technical silicon layer 58. Tensile layer 58 may also be used, for example, by depositing titanium (Ti) or cobalt (Co) on top 56 of SiGe layer 52 and forming a thin layer of titanium silicide or cobalt silicide. It should be noted that it may be formed by the method. Another example of forming the tensile layer 58 is to inject a component having a lattice constant different from SiGe, such as, for example, carbon (C) or germanium (Ge), to the top surface 56 of the SiGe layer 52. It includes.

Referring to FIG. 6, silicon nitride layer 60 is deposited on oxide layer 40 and tensile silicon layer 58 and then patterned to expose the support while the array is warmed. The active area of the support is patterned to form Shallow Trench Isolations (STI: 62), which are filled and then planarized using known methods such as TEOS CVD oxide or HDP oxide. A sacrificial oxide (not shown) grows on the support and a well implant (not shown) is formed. The support gate dielectric 64 is formed in the tensile silicon layer 58 by removing the sacrificial oxide and growing a thin dielectric film, such as a thermal oxide or nitride oxide. A support gate conductor 66 is formed in the tensile layer region (support), and a portion of the gate conductor 66 remaining in the tensile layer region (array) is removed using a block mask.

With reference to FIG. 7, silicon nitride layer 60 is selectively removed from the array for oxide layer 40 by processes known in the art, such as wet etching with hot phosphoric acid. Oxide layer 40 is then selectively removed relative to silicon nitride layer 38. Wordline conductors, such as tungsten / tungsten silicide, and cap layers, such as silicon nitride 70, are deposited in the support and array regions.

Referring to FIG. 8, the support gate 66, the word line 68 and the cap layer 70 are simultaneously patterned and etched with a common mask. Optionally, two masks may be used to form the support gate 66 and the wordline 68. For example, one mask may be used to form the support gate 66 while another mask may be used to form the wordline 68 to individually optimize each unique property, such as line width for performance considerations. Can be.

Subsequent standard processing then includes support S / D expansion, halo and contact implants; Gate sidewall oxidation to heal any damage due to gate etching; Spacer formation; Support and bitline contact studs; Interlevel dielectrics; And stacking and patterning an upper layer of wiring including bitline conductors.

Also, if the propagation of silicon displacement from the tensile layer SiGe region to the tensile layer-less memory array is a problem, a dummy deep storage trench may be formed between the tensile layer (support) and the tensile layer-free (array) region. Can be used as a buffer.

While the invention has been described above with reference to preferred embodiments, it should be understood that the spirit and scope of the invention is not limited thereby. Instead, various modifications may be made to the invention as described above without departing from the full scope of the invention as set forth above and in the appended claims.

Claims (16)

A semiconductor substrate having a strained layer-free region and a strained layer region; A first device formed in said tensile layer-free region of said semiconductor substrate; And A second device formed in the tensile layer region of the semiconductor substrate Including; The tensile layer region includes a trench that is selectively formed in the substrate, and includes a SiGe layer formed in the trench and an epitaxial silicon layer formed in the SiGe layer, Wherein the tensile layer region further comprises a spacer formed in the sidewalls of the trench, wherein the spacer isolates the strain generated in the tensile layer region from the tensile layer-free region. The method of claim 1, And the first device comprises a memory cell and the second device comprises a FET. The method of claim 2, Wherein the memory cell is a low-leakage DRAM cell and the FET is a MOSFET logic device. delete The method of claim 1, Wherein the epitaxial silicon layer is about 2.5 to about 10 nm thick. The method of claim 1, And the SiGe layer is epitaxially grown. delete The method of claim 1, The trench is about 100 nm to about 400 nm deep. In the method of manufacturing a semiconductor structure, a) providing a semiconductor substrate having a tensile layer-free region; b) forming a first device in said tensile layer-free region of said semiconductor substrate; c) selectively forming a tensile layer region in said semiconductor substrate; And d) forming a second device in the tensile layer region Including; Step (c) is i) forming a trench having a bottom surface and a sidewall surface; ii) forming a SiGe layer in the trench; And iii) forming a silicon layer on the SiGe layer More, After step (i), forming a spacer on the sidewall surface. delete delete The method of claim 9, wherein step (iii) Epitaxially growing the silicon layer. delete delete delete delete

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