KR100714452B1 - Parallel processing structured equalizer for ds-cdma uwb system, and its method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an equalizer of a parallel processing structure for a DS-CDMA UWB system and a method thereof.

2. The technical problem to be solved by the invention

The present invention uses only one filter tap coefficient update unit (WUB), unlike the conventional method of individually updating the filter tap coefficients for each ( L ) filter tap coefficient update unit (WUB) in the parallel processing structure. By updating the filter tap coefficients and passing the updated values to L filter units (FBs) to estimate transmission symbols, the complexity and power consumption of the equalizer used in the DS-CDMA UWB modem receiver can be significantly reduced. The purpose of the present invention is to provide an equalizer and a method of parallel processing for DS-CDMA UWB systems.

3. Summary of Solution to Invention

In the equalizer of the parallel processing structure for the DS-CDMA UWB system, the present invention performs filtering on any one input signal (training input signal) among a plurality of input signals when the equalizer operates in the training mode. Filter means for performing filtering on all input signals in parallel when the equalizer operates in a symbol determination mode; In the training mode, the symbol error value is obtained from the output value of the filter means and the training symbol. In the symbol determination mode, the corresponding transmission symbol value is estimated from the output value of the filter means for each input signal, and the transmission symbol value is estimated. Symbol determination means for obtaining an error (symbol error value) of the estimated transmission symbol value with respect to any one of the estimated input signals (signal error calculation input signal); And a filter tap coefficient updating means for updating the filter tap coefficients of the filter means using the training input signal or the symbol error calculation input signal and the symbol error value obtained from the symbol determining means, and transmitting the filter tap coefficients to the filter means. Included.

4. Important uses of the invention

The present invention is used for equalizers in DS-CDMA UWB systems.

DS-CDMA, UWB, parallel processing structure, equalizer, filter tap coefficient update unit, WUB (Weight Update Blcok), filter unit, FB (Filter Block)

Description

PARALLEL PROCESSING STRUCTURED EQUALIZER FOR DS-CDMA UWB SYSTEM, AND ITS METHOD}

1 is a configuration diagram of a conventional general DS-CDMA UWB modem receiver;

2 is a detailed configuration diagram of a conventional parallel processing structure equalizer applied to a DS-CDMA UWB modem receiver;

3 is a configuration diagram of an equalizer of a parallel processing structure for a DS-CDMA UWB system according to the present invention;

4 is a flowchart illustrating a filter tap coefficient adaptation and a transmission symbol determination method in a parallel processing structure equalizer according to the present invention.

* Explanation of symbols on the main parts of the drawings

21, 31: delay section 22, 32: filter section (FB)

23, 33: symbol determiner 24, 34: filter tap coefficient update unit (WUB)

The present invention relates to an equalizer and a method of a parallel processing structure for a direct sequence-code division multiple access (DS-CDMA) ultra wide-band system. More particularly, the present invention relates to a plurality of equalizers in a parallel processing structure. Unlike the conventional method of updating the filter tap coefficients individually for each of the ( L ) filter tap coefficient updating units (WUB), only one filter tap coefficient updating unit (WUB) is used to update the filter tap coefficients and the updated value. Is transmitted to the L filter units (FB) to estimate the transmission symbol, which can significantly reduce the complexity and power consumption of the equalizer used in the DS-CDMA UWB modem receiver. The equalizer of the structure and a method thereof.

Since DS-CDMA Ultra Wide-Band (UWB) system transmits signals using ultra-wideband frequencies, it is used not only for multipath fading and phase offset by multipath of transmission channel, but also for transmission and reception. The synchronization error of the signal is severely generated due to frequency offset occurring between clocks.

In order to solve this synchronization problem, a receiver is designed and equipped with a module for matching packet synchronization with symbol synchronization, and a channel estimator and a rake receiver are used to efficiently cope with changing channel conditions during data frame transmission. Restores the data sent by the transmitter.

However, due to the UWB channel characteristics, the multipath fading delay time due to the multipath is more than 150 to 200 nsec or more, so the inter-symbol interference (ISI) generated during data transmission cannot be eliminated by the rake receiver alone. The performance of the UWB modem receiver is degraded.

Therefore, to overcome this problem, the equalizer must be additionally designed in the DS-CDMA UWB modem receiver.

In the DS-CDMA data frame structure of a UWB modem to the normal preamble (Normal Premable) intervals are assigned approximately 15μ s, among these in order to remove interference that occurs between the symbols, the equalizer using training symbols (Training Symbol) group the period allocated to converge the filter tap coefficients is an interval corresponding to 15μ μ s after 10 s from the first preamble (preamble) is sent sequence. As such, in the UWB system, the equalizer must be converged by using a training symbol within a relatively short preamble transmission period, and high-speed data processing is required. Therefore, it is required to design the equalizer of the receiver in a parallel processing structure.

In general, the Filter Tap Coefficient (Filter Tap Weight) of the Symbol Rate Linear Equalizer (SRLE) that performs parallel processing is the opposite direction of the Noise Error Gradient. It is adapted by Least Mean-Square (LMS) algorithm. The adaptation (optimization) of the l- th equalizer filter tap coefficient is shown in Equation 1 below.

이고,

은 n 번째 심볼전송 시간에 심볼결정기(slicer)의 출력단에서 얻은 값이며, d 는 송신부에서 수신부까지 심볼이 전송될 때의 전체적인 심볼 지연시간을 나타낸다.

는 필터탭 계수 갱신시 사용되는 스텝크기(Step Size)를 나타내고,

는

의 전치행렬을 의미한다. 그리고, l번째 등화기 필터탭 계수에 대한 실수벡터와 l번째 등화기의 입력값에 대한 실수 벡터는 각각 다음 [수학식 2]와 같다.Where the error error rate is

ego,

Is the value obtained at the output of the symbol determiner at the nth symbol transmission time, and d represents the overall symbol delay time when the symbol is transmitted from the transmitter to the receiver.

Indicates the step size used when updating the filter tap coefficients.

Is

Means transpose of. Then, the real vector for the input vector of the real and l th equalizer for the l-th equalizer filter tap coefficients is equal to each of the following Equation (2).

Where N represents the number of filter tap coefficients of the SRLE,

1 is a block diagram of a conventional general DS-CDMA UWB modem receiver.

A radio frequency (RF) processing stage of a DS-CDMA UWB receiver receives an RF transmission signal sent from a transmitter and converts the signal into a baseband signal, which is a DS-CDMA UWB modem as shown in FIG. It is input to the analog-to-digital converter (ADC) 10 of the receiver.

Then, the analog-to-digital converter (ADC) 10 receives the analog baseband signal 101 and converts it into a digital signal 102, and the correlation detector 11 is an analog-to-digital converter (ADC) ( A correlation detection operation is performed on the M received signals 102 inputted from 10), and the M result values (complex correlation detection values) 103 are output to the rake receiver 12.

The rake receiver 12 receives L real symbol inputs 104 to be input to the parallel processing equalizer 13 from the M complex correlation detection inputs 103 transmitted from the correlation detector 11. Outputs Then, the L- Parallel Equalizer 13 removes the inter-symbol interference of the channel from the L real symbol input values 104 input from the rake receiver 12 and then L L decision values 105 )

).Then, the Viterbi Decoder 14 obtains the coding gain by using the output of the parallel processing structure equalizer 13, which is L 'designed for the receiver for the convolutional encoder of the transmitter. Is a decoder with two outputs 106 (where

).

Fig. 2 is a detailed configuration diagram of a conventional parallel processing structure equalizer, and shows a parallel processing structure equalizer 13 ( L- Parallel Equalizer) 13 which is generally applied to a DS-CDMA UWB modem receiver.

As shown in FIG. 2, the equalizer used in the DS-CDMA UWB modem receiver includes L filter tap coefficient updating units (WUB) for updating the filter tap coefficients using the equalizer input value and the symbol error value obtained from the symbol determiner. Weight Update Block) 24; Delay section 21 (shown as a separate functional section in the drawing) for obtaining N input values to be used in the filter section (FB) 22 and the symbol decision section 23 by delaying the equalizer input value, Unit 22 and the filter tap coefficient updating unit WUB; L filter blocks (FBs) 22 for obtaining a symbol determiner input value from the filter tap coefficients obtained from the filter tap coefficient updating unit (WUB) 24 and the equalizer input values; It consists of L symbol determiners 23 which determine the transmission symbol from the filter result FB or obtain a symbol error value.

Of the L equalizer input values output from the rake receiver 12, the first input value r _n 201 is an input value of the first filter part FB, and the second input value r _n-1 205 is As the input value of the second filter part FB, the L- th input value r _{n- (L-1)} 207 is used as the input value of the L- th filter part FB. The conventional parallel processing structure equalizer is composed of L equalizers having the same structure, the first equalizer of which is as described below, and the remaining L -1 equalizers are implemented in the same way.

As shown in FIG. 2, the equalizer input value r _n passes through the N-1 D flip-flops 240 to 242 to filter FB 22 and filter tap coefficients. N input values r _n , r _nL , ..., r _{nL (N-1)} 201 to 204 to be used in the update unit (WUB) 24.

The filter unit (FB) 22 is composed of N filter tap coefficients (c _{n , 0,0} , c _{n , 0,1} ..., c _{n, 0,} ) obtained from the filter tap coefficient update unit (WUB) 24 _{. N-1} ) 290 to 293 and N equalizer input values r _n , r _nL , ..., r _{nL (N-1)} ) 201 to 204 respectively output from the delay unit 21. N multipliers 230 to 233 to multiply; The adders 221 to 223 add the result values of the multipliers, and the result values of the adders 221 to 223 are transmitted to the symbol determiner 225 via the bit number adjuster 224.

First, when the equalizer is operated in the 'training mode', the training symbol S _n 299 is input to the subtractor 226 as the switch 227 moves downward. That is, in this case, the training symbol is taken as a symbol value. Subtractor 226. The training symbols (S _n) and the symbol determiner input value (y _{n, 0),} the symbol error value (e _{n, 0)} is determined to 229 from 228.

)(295)이 감산기(226)로 입력된다. 따라서, 감산기(226)에서는 심볼 결정기(225)에서 구한 심볼값(

)(295)과 심볼 결정기 입력값(y_n,0)(228)으로부터 심볼 오류값(e_{n, 0})(229)이 출력된다.On the other hand, in the case where the equalizer is operated in the 'symbol determination mode', the switch 227 moves upward so that the symbol value obtained by the symbol determiner 225 (

) 295 is input to the subtractor 226. Therefore, in the subtractor 226, the symbol value (obtained from the symbol determiner 225) (

) (295 a) and the symbol determiner input value (y _{n, 0),} (228) the symbol error value (e _{n, 0),} (229) from the outputs.

Hereinafter, the filter tap coefficient update unit WUB will be described. The parallel processing structure equalizer is composed of L filter tap coefficient update units (WUB) having the same structure.

The filter tap coefficient updating unit (WUB) 24 includes N multipliers 250 to 253, N multipliers 260 to 263, N D flip-flops 280 to 283, and N additions. Groups 270 to 273, and N number of bit adjusters 285 to 288, which will be described below.

)(265 내지 268)를 곱하는 연산을 수행한다. 이처럼 도 2에서의 곱셈기(260 내지 263)는 실제 구현시에는 오른쪽 혹은 왼쪽 쉬프트(shift) 연산을 수행하는 쉬프트(shift) 연산기가 될 것이다.The N multipliers 250 to 253 are symbol error values (e _{n, 0} ) 229 obtained from the symbol determiner 23 and N equalizer input values r _n , r _nL , ..., r _{nL ( N-1)} multiplying) 201 to 204, and multipliers 260 to 263 perform step size and step values of the multipliers 250 to 253 to update the filter tap coefficient every symbol interval. ) (

Multiply by 265 through 268. As such, the multipliers 260 to 263 in FIG. 2 may be shift operators that perform right or left shift operations in actual implementation.

Each of the N adders 270 to 273 stores the previous filter tap coefficient values stored in the D flip-flops 280 to 283 and the result values of the corresponding multipliers (shift operators) 260 to 263. In addition, a new filter tap coefficient value is obtained. Here, the D flip-flops 280 to 283 perform a function of storing the result value for one input symbol period in order to continuously update the filter tap coefficient value. The bit number adjusters 285 to 288 perform a function of adjusting the number of bits of the filter tap coefficient value.

The filter tap coefficient value obtained through the above process is determined by the filter unit (FB) 22 when the next symbol is input, and the filter tap coefficient update unit (WUB) 24 determines the filter tap value. It is reused to update the count value.

In the conventional parallel processing structure equalizer as described above, in order to obtain filter tap coefficients, L filter tap coefficient updating units (WUB) 24 update filter tap coefficients each time, and L filter unit (FB) 22 are updated. In order to estimate the signal (transmitted signal) sent by the transmitter to transmit to the system, there is a problem in that the system is complicated and power consumption is high.

On the other hand, UWB systems generally use the ultra-wide frequency band of 500MHz or more, and since most of the applications are installed in the home, there is little mobility. Therefore, because the Doppler Frequency Spread of UWB channels is close to "0" and the coherence time is long, the channel change during several symbol transmission periods in UWB systems operating from tens to hundreds of Mbps Almost no. In addition, the UWB chipset will be used in various digital video devices, PC products, and digital personal devices in the future, and to realize this, it is urgent to reduce the power and size of the UWB modem chip (CHIP) by improving the complexity of the modem receiver. It is required.

That is, there is a need for a 'low complexity equalizer structure' suitable for a modem receiver for a WPAN (Wireless Personal Area Network) in which a wide channel frequency is used, such as a UWB system.

The present invention has been proposed to solve the above problems, unlike the conventional method of individually updating the filter tap coefficients for each ( L ) filter tap coefficient update unit (WUB) in an equalizer of a parallel processing structure. The filter tap coefficient is updated using only one filter tap coefficient updating unit (WUB), and the updated value is transmitted to the L filter units (FB) to estimate the transmission symbol, which is used for the DS-CDMA UWB modem receiving unit. It is an object of the present invention to provide an equalizer and a method of a parallel processing structure for a DS-CDMA UWB system, which can significantly reduce the complexity and power consumption of the equalizer.

Other objects and advantages of the present invention can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. It will also be appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

The present invention for achieving the above object, in the equalizer of the parallel processing structure for the DS-CDMA UWB system, when the equalizer operates in the training mode any one of a plurality of input signals (training input signal) Filtering means for performing a filtering operation and performing filtering on all input signals in parallel when the equalizer operates in a symbol determination mode; In the training mode, the symbol error value is obtained from the output value of the filter means and the training symbol. In the symbol determination mode, the corresponding transmission symbol value is estimated from the output value of the filter means for each input signal, and the transmission symbol value is estimated. Symbol determination means for obtaining an error (symbol error value) of the estimated transmission symbol value with respect to any one of the estimated input signals (signal error calculation input signal); And a filter tap coefficient updating means for updating the filter tap coefficient of the filter means by using the training input signal or the symbol error calculation input signal and the symbol error value obtained by the symbol determining means and transmitting the filter tap coefficient to the filter means. It includes.

On the other hand, the present invention, in the parallel processing equalization method applied to the equalizer of the parallel processing structure for the DS-CDMA UWB system, performing filtering on any one input signal (training input signal) of a plurality of input signals A training step of obtaining a first symbol error value from the filtered training input signal and a predetermined training symbol; Until the filter tap coefficients converge, the first filter tap that updates the filter tap coefficients used for filtering in the training step by using the first symbol error value and the training input signal and feeds back to the training step. An update step; When the filter tap coefficients in the first filter tap updating step converge, the filtering process is performed in parallel on each of the input signals using the filter tap coefficients finally updated in the first filter tap updating step as initial filter tap coefficients. Performing a symbol determination step of estimating a corresponding transmission symbol value from each filtered input signal; Until the data frame transmission is completed, an error (second symbol) of the estimated transmission symbol value with respect to one of the input signals (signal error calculation input signal) among the input signals whose transmission symbol value is estimated in the symbol determination step (second symbol). Calculating a symbol error value; And updating a filter tap coefficient used for filtering in the symbol determining step by using the second symbol error value and the input signal for calculating the symbol error, and then feeding back to the symbol determining step. Include.

The present invention relates to a parallel processing equalizer suitable for a high speed DS-CDMA UWB modem receiver and a method for adapting filter tap coefficients of the equalizer. That is, to provide a 'low complexity equalizer structure' suitable for a modem receiver for a WPAN (Wireless Personal Area Network) which does not have a large channel change as using a UWB system.

In the present invention, when designing an equalizer with L parallel processing structures, one filter tap is used without using the conventional method of updating the filter taps every time in the L filter tap coefficient updating unit (WUB) to obtain filter tap coefficients. The filter tap coefficients are updated using only the coefficient updater WUB and the values are transmitted to the L filter units FB to estimate transmission symbols.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an equalizer of a parallel processing structure for a DS-CDMA UWB system according to the present invention, and shows a parallel processing structure equalizer with improved complexity suitable for a DS-CDMA UWB modem receiver.

The parallel processing structure equalizer used in the DS-CDMA UWB modem receiver is one for updating the filter tap coefficients using the equalizer input value transmitted from the rake receiver 12 and the symbol error value obtained from the first symbol determiner 33. A 'filter tap coefficient update unit (WUB)'34; Delay section 31 (shown as a separate functional section in the figure) for obtaining N input values to be used in the filter section (FB) 32 and the symbol determination section 33 by delaying the equalizer input values. (22) and the filter tap coefficient updating unit (WUB); L filter units (FB) 32 for obtaining a symbol determiner input value from the filter tap coefficient and the equalizer input value obtained from the filter tap coefficient updater (WUB) 34; The filter unit (FB) 32 is composed of L symbol determination units 33 which determine transmission symbols from the result values or obtain symbol error values.

Of the L equalizer input values output from the rake receiver 12, the first input value r _n 301 is an input value of the first filter part FB, and the second input value r _n-1 305 is As the input value of the second filter part FB, the L th input value r _{n- (L-1)} 307 is used as the input value of the L th filter part FB.

When the equalizer operates in the training mode, only the first filter unit FB of the L filter units FB operates, and when the equalizer switches to the symbol determination mode, all L filter units FB operate.

The parallel processing structure equalizer according to the present invention is composed of L equalizing units having the same structure, the first equalizing unit is the same as described below, and the remaining L -1 equalizing units are implemented in the same manner.

As shown in FIG. 3, the equalizer input value r _n is passed through the N-1 D flip-flops 340 to 342 to thereby filter the FB 32 and filter tap coefficients. N input values r _n , r _nL ,..., And r _{nL (N-1)} 301 to 304 to be used in the update unit (WUB) 34. In this case, when the equalizer operates in the training mode, only the first filter unit FB operates, so a signal input to the first filter unit FB in the training mode, that is, r _n, is referred to as a 'training input signal'. . On the other hand, when the equalizer operates in the symbol determination mode, the L filter units FB operate, but only the first filter unit FB is involved in calculating the symbol error value used for updating the filter tap coefficients. In the mode, a signal input to the first filter unit FB, that is, r _n, is referred to as an input signal for calculating a symbol error.

The filter unit (FB) 32 is composed of N filter tap coefficients (c _{n , 0,0} , c _{n , 0,1} ..., c _{n, 0,} ) obtained from the filter tap coefficient update unit (WUB) 34 _{. N-1} ) 390 to 393 and N equalizer input values r _n , r _nL , ..., r _{nL (N-1)} ) 301 to 304 respectively output from the delay unit 31. N multipliers 330 to 333 to multiply; The adders 321 to 323 add the result values of the multipliers, and the result values of the adders 321 to 323 are passed to the symbol determiner 325 via the bit number adjuster 324.

)(395)을 결정하는 기능을 수행하고, 나머지 L-1개의 심볼 결정부는 '심볼 결정모드'에서만 동작하며, 심볼 오류값은 구하지 않고 단지 송신 심볼값(396 내지 398)을 결정하는 기능만 수행한다.In the parallel processing structure equalizer according to the present invention, the first symbol determiner 33 obtains a symbol error value (e _{n, 0} ) 329 and passes it to the filter tap coefficient update unit (WUB) 34 or transmits a symbol value. (

(395), the remaining L -1 symbol determiner operates only in the 'symbol determination mode', and does not obtain a symbol error value but merely determines a transmission symbol value (396 to 398). do.

First, when the equalizer is operated in the 'training mode', the switch 327 of the first symbol determiner 33 moves downward so that the training symbol S _n 399 moves to the subtractor 326. Is entered. In this case, the training symbol is taken as a symbol value. The subtractor 326 obtains a symbol error value (e _{n, 0} ) 329 from the training symbol S _n and the symbol determiner input values y _{n, 0} 328.

)(395)이 감산기(326)로 입력된다. 따라서, 감산기(326)에서는 심볼 결정기(325)에서 구한 심볼값(

)(395)과 심볼 결정기 입력값(y_n,0)(328)으로부터 심볼 오류값(e_{n, 0})(329)이 출력된다.On the other hand, when the equalizer is operated in the 'symbol determination mode', the switch 327 is moved upward so that the symbol value obtained from the symbol determiner 325 (

395 is input to the subtractor 326. Therefore, in the subtractor 326, the symbol value obtained by the symbol determiner 325 (

395 and a symbol determiner input value (y _{n, 0} ) 328 output a symbol error value (e _{n, 0} ) 329.

Hereinafter, the filter tap coefficient update unit WUB will be described. In order to improve the complexity, the parallel processing structure equalizer according to the present invention uses only one filter tap coefficient updating unit (WUB) 34, unlike the conventional equalizer (see FIG. 2).

The filter tap coefficient updating unit (WUB) 34 includes N multipliers 350 to 353, N multipliers 360 to 363, N D flip-flops 380 to 383, and N adders. 370 to 373, and N number of bit adjusters 385 to 388, each of which is described below.

)(365 내지 368)를 곱하는 연산을 수행한다. 이처럼 도 3에서의 곱셈기(360 내지 363)는 실제 구현시에는 오른쪽 혹은 왼쪽 쉬프트(shift) 연산을 수행하는 쉬프트(shift) 연산기가 될 것이다.The N multipliers 350 to 353 are symbol error values (e _{n, 0} ) 329 obtained from the first symbol determiner 33 and N equalizer input values (r _n , r _nL , ..., r _{nL). (N-1)} multiplying (301 to 304), the multipliers (360 to 363) is a result of the multipliers (350 to 353) and step size (step) to update the filter tap coefficient every symbol interval size) (

Multiply by (365 to 368). As such, the multipliers 360 to 363 in FIG. 3 may be shift operators that perform right or left shift operations in actual implementation.

Each of the N adders 370 to 373 stores the previous filter tap coefficient values stored in the D flip-flops 380 to 383 and the result values of the corresponding multipliers 360 to 363. In addition, a new filter tap coefficient value is obtained. Here, the D flip-flops 380 to 383 store a result value for one input symbol period in order to continuously update the filter tap coefficient value. The bit number adjusters 385 to 388 perform a function of adjusting the number of bits of the filter tap coefficient value.

When the 'next symbol' is input, the filter tap coefficient value obtained through the above process is determined by the filter unit (FB) 32, and the filter tap coefficient update unit (WUB) 34 determines the filter tap value. It is reused to update the count value.

4 is a flowchart illustrating an embodiment of a method for adaptive filter tap coefficient adaptation and transmission symbol determination in a parallel processing structure equalizer according to the present invention, in which a filter tap coefficient of a parallel processing structure equalizer suitable for a DS-CDMA UWB modem receiver is adapted. (Optimization) shows the process of obtaining the symbol value sent from the transmitter. That is, the process of determining the symbol value by using one filter tap coefficient update unit WUB and L filter units FB in the equalizer.

First, the equalizer operates in a training mode during a preamble transmission period, in which a training symbol is used (400). That is, the training mode is input to the (Training Mode) In the first symbol determining unit being a switch 327 in the 23 switching down, training symbols (S _n) (399), the subtractor 326 as the symbol values.

During the training mode, only the filter tap coefficient updating unit (WUB) 34 and the first filter unit (FB) 32 are operated to adapt the filter tap coefficients, and the remaining L- 1 filter units FB are operated. Do not let (401). Further, in the first symbol determiner 33, the training symbol (S _n ) 399 is taken as a symbol value, and this value and the symbol determiner input value (y _{n, 0} ) obtained from the first filter unit (FB) 32 are obtained. The symbol error value (e _{n, 0} ) 329 is extracted from the block 328 and transmitted to the filter tap coefficient update unit (WUB) 34 (402).

Then, the filter tap coefficient updating unit (WUB) 34 receives the symbol error value 329 received from the first filter unit (FB) 32, the equalizer input values 301 to 304, and the step size ( The filter tap coefficient values are updated using 365 to 368, the number of bits is optimized through the bit number adjusters 385 to 388, and the filter tap coefficient values are transferred to the first filter unit (FB) 32 ( 403).

Then, it is checked whether the WUB filter tap coefficients have sufficiently converged (410). If the filter tap coefficients have sufficiently converged, the equalizer is operated in the 'symbol determination mode' (420). Otherwise, the symbol error value is extracted and the filter taps are extracted. The process of transmitting to the coefficient updating unit WUB (402) and updating the filter tap coefficients (403) is repeated.

Here, whether or not the equalizer filter tap coefficients are converged is determined by comparing the magnitude of the symbol error value (e _{n, 0} ) obtained by the symbol determiner with the magnitude of the threshold value previously obtained through the simulation, or a simulation. After calculating in advance the time (K) that the equalizer filter tap coefficients sufficiently converge, there is a method of checking whether or not the time for adapting the equalizer filter tap coefficients exceeds the previously calculated time (K).

In the present invention, it is assumed that the filter tap coefficient value of the filter tap coefficient updating unit (WUB) sufficiently converges during the preamble transmission period, and the equalizer is operated in the 'training mode' during the preamble transmission period and data frame transmission is performed. During the interval the equalizer is put into the 'symbol determination mode'. Therefore, in the present invention, the equalizer converges or not, and the overall scheme is designed so that the preamble transmission period can be varied according to the convergence time of the equalizer filter tap coefficients.

The filter tap coefficient finally updated in the above training mode is used as the initial filter tap coefficient in the symbol determination mode.

On the other hand, when the equalizer filter tap coefficients converge, that is, when the equalizer operates in the data frame transmission mode, the symbol determination takes the symbol value 395 obtained from the symbol determination unit 33 by switching the switch 327 upward. Operate in mode (420). In addition, the filter tap coefficient updating unit WUB as well as the L filter units FB are operated in operation 421 to adapt the filter tap coefficients and obtain a symbol determiner input value. The value 329 is obtained and transmitted to the filter tap coefficient updating unit (WUB) 34. Subsequently, the L parallel symbol determiners estimate the transmission symbols using the symbol determiner input values respectively transmitted from the L parallel filter units FB, and then transfer the estimated transmission symbols to the Viterbi decoder (423). .

The filter tap coefficient value is updated by using the symbol error value 329, the equalizer input values 301 to 304, and the step sizes 365 to 368 received from the first symbol determiner 33. After optimizing the number of bits via the bit number regulators 385 to 388, the filter tap coefficient values are transmitted to the L filter units FB (424).

Next, it is checked whether the data frame transmission is completed (430). If the data frame transmission is completed, the equalizer operation is terminated. Otherwise, the symbol error value is extracted from the first symbol determination unit to update the filter tap coefficient (WUB). In step 422, the transmission symbols estimated by the L symbol determiner are transmitted to the Viterbi decoder (423), and the filter tap coefficient value is updated (424).

In short, the present invention relates to a parallel processing structure equalizer suitable for a DS-CDMA UWB modem receiver as described above, wherein the equalizer is operated in a training mode using a training symbol during a preamble transmission period, and a data frame transmission mode. In this case, the equalizer is operated in a symbol determination mode to obtain a symbol value sent from the transmitter according to the method shown in FIG.

As described above, the method of the present invention may be implemented as a program and stored in a recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, magneto-optical disk, etc.) in a computer-readable form. Since this process can be easily implemented by those skilled in the art will not be described in more detail.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by the drawings.

The present invention as described above has the effect of reducing the hardware complexity of 40% or more, and the power consumption significantly compared to the conventional equalizer design method.

That is, the present invention is composed of L filter tap coefficient updating units (WUB) and L filter units (FB), unlike the conventional equalizer, one filter tap coefficient updating unit (WUB) and L filter units (FB). During the symbol preamble transmission period, the training symbol is used and one filter tap coefficient update unit (WUB) and one filter unit (FB) are operated to converge the equalizer filter taps, and the data transmission mode Reduces the complexity of the receiving system by switching the equalizer operation to the symbol decision mode and operating both the filter tap coefficient updating unit (WUB) and the L filter units (FB) to estimate the signal transmitted from the transmitter. This has the effect of significantly reducing the power consumption.

Hereinafter, the hardware complexity of the parallel processing structure equalizer (see FIGS. 3 and 4) and the conventional parallel processing structure equalizer (see FIG. 2) according to the present invention will be described in detail.

In general, the equalizer according to the present invention is designed in that the number of bits of the multiplier used in the filter tap coefficient updating unit WUB is designed to be larger than the number of bits of the multiplier used in the filter unit FB. The structure significantly reduces the complexity by more than 40% compared to the conventional equalizer. In addition, since the present invention operates only one filter unit FB and one symbol determiner when the equalizer is operated in the training mode, power consumption is also significantly reduced.

Claims (9)

In the equalizer of parallel processing structure for DS-CDMA UWB system, When the equalizer operates in the training mode, the filtering is performed on any one input signal (training input signal) among a plurality of input signals. When the equalizer operates in the symbol determination mode, filtering is performed in parallel on all of the input signals. Filter means for performing; In the training mode, the symbol error value is obtained from the output value of the filter means and the training symbol. In the symbol determination mode, the corresponding transmission symbol value is estimated from the output value of the filter means for each input signal, and the transmission symbol value is estimated. Symbol determination means for obtaining an error (symbol error value) of the estimated transmission symbol value with respect to any one of the estimated input signals (signal error calculation input signal); And Filter tap coefficient updating means for updating the filter tap coefficient of the filter means by using the training input signal or the symbol error calculation input signal and the symbol error value obtained by the symbol determination means and transmitting the filter tap coefficient to the filter means. Equalizer of parallel processing structure for DS-CDMA UWB system comprising a. The method of claim 1, The training mode, A mode in which the equalizer operates during a period in which a preamble of an input signal is transmitted; The symbol determination mode, Equalizer of the parallel processing structure for a DS-CDMA UWB system, characterized in that the equalizer operation mode during the data frame of the input signal transmission period. The method according to claim 1 or 2, The filter means, A plurality of filter units are included to perform filtering on a plurality of input signals in parallel. When the equalizer operates in a training mode, only one filter unit (the first filter unit) operates to operate the training input. When the filter is performed and the equalizer operates in the symbol determination mode, all of the filter units operate to perform filtering on each input signal in parallel to the DS-CDMA UWB system. Equalizer of parallel processing structure. The method of claim 3, wherein The symbol determination means, A plurality of symbol determination units are included, and in the training mode, a symbol error value is obtained from an output value and a training symbol of the first filter unit, and in the case of the symbol determination mode, a corresponding transmission symbol value is estimated from an output value of each filter unit. And a symbol error value is obtained from the estimated transmission symbol value for the symbol error calculation input signal inputted to the first filter unit and the output value of the first filter unit, and equalization of the parallel processing structure for the DS-CDMA UWB system. group. The method of claim 4, wherein The filter tap coefficient updating means is  In case of the training mode, the updated filter tap coefficient is transmitted to the first filter unit, and in the case of the symbol determination mode, the filter unit is transmitted to all the filter units. Equalizer. The method of claim 4, wherein The training input signal and the input signal for symbol error calculation, Equalizer of parallel processing structure for DS-CDMA UWB system, characterized in that the first input signal of the plurality of input signals. A parallel processing equalization method applied to an equalizer of a parallel processing structure for a DS-CDMA UWB system, A training step of performing filtering on one input signal (a training input signal) among a plurality of input signals, and obtaining a first symbol error value from the filtered training input signal and a predetermined training symbol; Until the filter tap coefficients converge, the first filter tap that updates the filter tap coefficients used for filtering in the training step by using the first symbol error value and the training input signal and feeds back to the training step. An update step; When the filter tap coefficients in the first filter tap updating step converge, the filtering process is performed in parallel on each of the input signals using the filter tap coefficients finally updated in the first filter tap updating step as initial filter tap coefficients. Performing a symbol determination step of estimating a corresponding transmission symbol value from each filtered input signal; Until the data frame transmission is completed, an error (second symbol) of the estimated transmission symbol value with respect to one of the input signals (signal error calculation input signal) among the input signals whose transmission symbol value is estimated in the symbol determination step (second symbol). Calculating a symbol error value; And A second filter tap updating step of feeding back to the symbol determining step after updating the filter tap coefficients used for filtering in the symbol determining step by using the second symbol error value and the input signal for calculating the symbol error; Parallel processing equalization method for a DS-CDMA UWB system comprising a. The method of claim 7, wherein The first filter tap updating step may include: And determining that the filter tap coefficients converge when a preamble transmission interval of an input signal has passed. The method of claim 7, wherein The training input signal and the input signal for symbol error calculation, Parallel processing equalization method for a DS-CDMA UWB system, characterized in that the first of the plurality of input signals.

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