KR100712677B1 - Spur reduction method with a plurality of local oscillator frequency and transceiver using the spur reduction method - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention relates to a method for reducing spurs in a transceiver having a phase locked loop (PLL) that generates an oscillation frequency input to a mixer for up or down cover before, due to a reference clock frequency of the phase locked loop. A plurality of LOs in the phase locked loop to keep the LO frequency of the phase locked loop away from the harmonics of a predetermined reference clock frequency such that the resulting spurs can be sufficiently suppressed by loop filtering of the phase locked loop. There is provided a method of reducing spurs in a transceiver, comprising selectively using a frequency.

Spur, PLL, VCO

Description

SPUR REDUCTION METHOD WITH A PLURALITY OF LOCAL OSCILLATOR FREQUENCY AND TRANSCEIVER USING THE SPUR REDUCTION METHOD}

FIG. 1 is a diagram illustrating a structure of a zero-IF receiver 100 and a down-conversion process of a frequency in the zero-IF receiver 100.

2 is a view for explaining the structure of a low-IF receiver and the entire process of down-covering the frequency in the low-IF receiver,

FIG. 3 shows a typical transceiver comprising mixer sections 42, 44 and LO generation circuit 50,

FIG. 4 is a more detailed view of the phase-locked loop (PLL) circuit 60 of FIG. 3.

FIG. 5 is a diagram schematically showing a LO generator circuit 50 that is commonly used, and shows an example in which two dividers are used.

FIG. 6 is a diagram schematically showing a LO generation circuit 50 that is commonly used.

7 shows the frequency components of the F _{LO in} the frequency domain,

FIG. 8 illustrates a case where a spur problem that occurs when one frequency plan is used is applied to a personal handyphone system (PHS) system, which is one of mobile communication systems.

9 is a view showing that the spur problem is solved when a plurality of frequency plans are used in the mobile communication system according to the present invention.

* Description of the symbols for the main parts of the drawings *

100 zero IF receiver

200 low-IF receiver

300 transceiver

10 antenna

20 filters

30 Low Noise Amplifier (LNA)

40, 42, 44 mixer

50 LO generation circuit

60 Phase-Locked Loop (PLL) Circuits

The present invention relates to a method for reducing spurs using a plurality of LO frequencies and a transceiver using the same. More particularly, spurs generated due to a reference clock frequency are generated by loop filtering of a phase locked loop (PLL). A method of reducing spurs by selectively using a plurality of LO frequencies so that the LO frequency f _vco (PLL output frequency) is far from the harmonics of a predetermined reference clock frequency to be sufficiently suppressed and a transceiver using the same It is about.

In general, an RF receiver refers to a device that processes a radio frequency (RF) signal received through an antenna through amplification, frequency conversion, and filtering, and is a super-heterodyne or zero eye. It has a zero-IF or low-IF structure.

Among the RF receiver structures, since the zero-IF receiver and the low-IF receiver can reduce the number of component elements, most of the RF receivers adopt a zero-IF receiver and a low-IF receiver in recent years.

FIG. 1 is a view for explaining a structure of a zero-IF receiver 100 and a down-conversion process of frequencies in the zero-IF receiver 100, and FIG. 2 is a low-IF receiver 200. A diagram for explaining the structure of the and the entire process of down-covering the frequency in the low-IF receiver 200.

The difference between the structure of the zero-IF receiver 100 and the low-IF receiver 200 and the two receivers will be described with reference to FIGS. 1 and 2, and the zero-IF receiver 100 and the low-IF receiver are described. The reference numeral 200 is distinguished according to the center frequency (F _IF ) of the converted base-band signal during the frequency conversion process. In particular, the case where F _IF = 0 Hz is called a zero _IF receiver.

Meanwhile, in the case of the low-IF receiver 200, as shown in FIG. 2, two types of frequencies may be implemented according to the relative positions of the RF signal and the local oscillator (LO) signal. In other words, | F _LO | <| F _RF | and | F _LO | > | F _RF | enables two frequency implementations.

The selectivity of the frequency at the receiving end of such a mobile communication system includes the linearity of the RF front end, phase noise of a voltage-controlled oscillator (VCO), analog and digital. It depends on the filtering characteristics of the circuit and various spurious characteristics in the device. In addition, the sensitivity of the receiver is affected not only by the noise figure of the entire receive path, but also by the spurious characteristics present in the desired signal band.

As described above, in the sensitivity and frequency selectivity at the receiving end of the mobile communication system, the spurious characteristic is not a big problem in the conventional super-heterodyne method, but a zero-eye in which many functional blocks are integrated therein In implementing an integrated RF circuit including a zero-IF structure, an RF receiver suffers from a lot of problems due to the spurious signal generated from a crystal oscillator, which is a reference frequency and an operation of a digital circuit existing inside a receiver. It became.

Meanwhile, FIG. 3 shows a typical transceiver 300 including mixer sections 42 and 44 and LO generating circuit 50. FIG. 4 shows a phase-locked loop of FIG. Loop) circuit 60 is shown in more detail. The transceiver 300 having the structure of FIGS. 3 and 4 may be applied to the zero eye and the low eye.

3 and 4, a phase-locked loop (PLL) circuit 60 for generating an LO signal has an output frequency generated from an external crystal oscillator 70, and generally The value is determined from the equation below.

F _PLL = (P + N / M) (S / R) F _REF

Where all variables are constants, given F _REF Each depends on and F _PLL . The output signal of the PLL 60 is applied to the LO input to the mixers 42 and 44 via an additional LO generating circuit 50. The mixers 42 and 44 may be up-converted or down-converted according to the frequency conversion process, and the present invention may also be applied to both cases. Has

However, a spur characteristic to be dealt with in the present invention is generally more important in the case of the receiver, and for convenience of description, only the receiver will be described.

In the case of the LO generation circuit 50, since the performance of the VCO is the same as the input signal or the output signal of the mixer, there is a deterioration in performance due to pulling or pushing. .

5 and 6 illustrate a commonly used LO generation circuit 50 in FIG. 5, wherein two dividers are used in FIG. 5 and four dividers are used in FIG. 6.

Referring to FIG. 5, a signal is obtained through a PLL having F _PLL = 2 * F _LO , and a signal of the F _LO is applied to the mixer through a two-division cycle. Can be generated. 6, F _PLL = (4/5) F _LO and applying a signal after four divisions to the mixer, (4/5 + 1/5) F _LO = F _{LO is applied} to the mixer. Will be authorized. In addition, like the two-division, it is possible to easily generate the I / Q signal through the four-division process.

The spur signal to be dealt with by the present invention may be derived from the VCO itself, or may be caused by leakage of spurs from the spurs by a low noise amplifier (LNA) or a mixer. Among these, spurs appearing in LNAs and mixers can be greatly attenuated by constructing a differential structure of the entire signal. Therefore, the biggest influence on the source of the spur is the signal applied to the phase / frequency detector (PFD) of the PLL circuit and the external crystal oscillator. In addition, their harmonic signals (harmonics) are affected.

For example, assume that the frequency of a crystal oscillator is 19.2 MHz. In addition, when the RF signal application frequency is 1900 MHz and the frequency of the VCO 64 is 4/5 of the RF frequency (f _vco = (4/5) F _C ) Will be described in detail with reference to FIG. 7.

7 shows the frequency components of the F _{LO in} the frequency domain.

Due to the influence of the LO generating circuit 50, spurs corresponding to the harmonic of (1/5) Fc exist on the LO side of the mixers 42 and 44. The main carrier, Fc, is the largest, but the harmonic (4/5) Fc point of the VCO (64) and (3/5) Fc, the image frequency, and (1/5) It can be seen that there are a myriad of harmonic components in Fc and the like. When the components causing various spurs present in the transceiver 300 are mixed with the remaining spur components except for the carrier component present in these LO signals, the performance of the transceiver will be degraded.

FIG. 8 applies this problem to a personal handyphone system, which is one of the mobile communication systems. As above, here, the frequency of the crystal oscillator is assumed to be 19.2 MHz. It is assumed that the frequency of the VCO, that is, the output frequency of the PLL is 4/5 of the Fc, and the reference clock harmonic is applied to the VCO, which is particularly vulnerable to the reference clock harmonic, in particular channel 2 and channel 81 The position of the spurs relative to the burn is close to the frequency of the VCO.

More specifically, the spur's position is the 79th harmonic (19.2MHz * 79 = 1516.8MHz) and the 80th harmonic component (19.2MHz * 80 = 1536MHz) of the crystal oscillator's frequency (19.2MHz). Since they are located very close to the frequency (the second channel and the 81st channel) by 560 kHz and 800 kHz, spurs are not loop filtered by the PLL's loop filter 63, that is, the suppression is reduced, so the actual LO In the output signal of the generating circuit, there are relatively large spurs unlike other channels.

In the case of PHS system, there is an in-band blocking signal that is 50 dB larger than the desired signal at 600 KHz away from the carrier, and the in-band signal-to-noise ratio (SNR) may drop due to the mixing of spurs and blockers. Can be. In this case, in order to satisfy the performance of the whole system, the spur should be about 70 dBc smaller than the output power of the VCO. However, as described above, the size of a spur is very difficult to predict because it is influenced by coupling between signals and coupling at the board level, and making a very small spur is a very big problem. Becomes

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and the harmonics of a predetermined reference clock frequency such that a spur generated due to the reference clock frequency can be sufficiently suppressed by loop filtering of the phase locked loop (PLL). It is an object of the present invention to provide a method of reducing spurs by selectively using a plurality of LO frequencies so that the LO frequency f _vco (the output frequency of the PLL) is far from.

Other objects and advantages of the present invention will be described below, and will be appreciated by the embodiments of the present invention. In addition, the objects and advantages of the present invention can be realized by means and combinations indicated in the claims.

In order to achieve the above object, the present invention provides a method for reducing spurs in a transceiver having a phase locked loop (PLL) for generating an oscillation frequency input to a mixer for up-covering or down-covering. Keep the LO frequency of the phase locked loop away from the harmonics of the predetermined reference clock frequency so that the spurs generated by the reference clock frequency of the phase locked loop can be sufficiently suppressed by the loop filtering of the phase locked loop. And selectively using a plurality of LO frequencies in the phase locked loop to provide a method for reducing spurs in a transceiver.

Here, the plurality of LO frequencies can be obtained through an LO having a wide operating frequency range. In addition, multiple LO frequencies may be obtained through one or more LOs.

In addition, selectively using the plurality of LO frequencies may include a predetermined reference clock frequency such that a spur generated due to the reference clock frequency of the phase locked loop can be sufficiently suppressed by loop filtering of the phase locked loop. Selecting the LO frequency of the phase locked loop away from the harmonics of and matching the output frequency of the phase locked loop to the input of the mixer by frequency division, corresponding to the selected LO frequency. It may include.

Further, when the LO frequency is selected in the phase locked loop so that the LO frequency of the phase locked loop is far from the harmonics of a predetermined reference clock frequency, the spur has a magnitude of about 70 dBc compared to the output power of the phase locked loop. Choose to be small.

In addition, the mixer may be an I / Q mixer.

In addition, the transceiver may have a zero IF structure, the transceiver may have a low IF structure, or the transceiver may have a super heterodyne structure.

In addition, the transceiver may be used only as a transmitter or as a receiver.

In addition, the transceiver may have a table for selecting the best LO frequency among a plurality of LO frequencies in advance.

The phase locked loop is further separated from the harmonics of a predetermined reference clock frequency so that the spur is small by about 70 dBc relative to the output power of the phase locked loop. It is also possible to adaptively select the LO frequency at.

The present invention also includes an antenna for transmitting and receiving an RF signal, a mixer for up-covering or down-covering, and a phase locked loop (PLL) for generating an oscillation frequency input to the mixer, the reference clock of the phase locked loop. The phase so that the spur due to frequency can be sufficiently suppressed by loop filtering of the phase locked loop so that the LO frequency of the phase locked loop is far from the harmonics of a predetermined reference clock frequency. The selective use of multiple LO frequencies in a fixed loop provides a transceiver that reduces spurs.

Also, the LO frequency of the phase locked loop from harmonics of a predetermined reference clock frequency such that the spurs generated due to the reference clock frequency of the phase locked loop can be sufficiently suppressed by loop filtering of the phase locked loop. Is selected to be far apart, between the phase locked loop and the mixer, in response to the selected LO frequency, the frequency of the output of the phase locked loop is divided by dividing, before up cover or down cover. It may further include an LO generation circuit to obtain a frequency that matches the input.

In addition, the LO frequency in the phase locked loop is separated from the harmonics of a predetermined reference clock frequency so that the spur is as small as 70 dBc relative to the output power of the phase locked loop. It may further comprise a controller for adaptive selection.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the present specification and claims should not be construed as being limited to the common or dictionary meanings, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention.

Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various equivalents that may be substituted for them at the time of the present application It should be understood that there may be water and variations.

The present invention utilizes LO generation circuits and VCOs having different frequency plans from each other to prevent characteristic degradation due to spurious signals in highly integrated transceivers. In other words, it can be seen from the foregoing description that a series of spurious signal components, including the frequency from the crystal oscillator and the reference frequency of the PLL, can be predetermined early in the design.

In addition, the desired frequency band and channel frequency can be known in advance by the RF designer, so the position of the frequency where the mixing or leakage components by the spurs described above can be calculated in advance.

It should be noted that one LO frequency plan is not a problem at other frequencies, although spurious or liquidity may be a problem if it is separated by a certain frequency unit. In addition, in the case of different frequency plans, problems such as spurious and liquidity occur at different frequencies from before, and thus, by focusing on this, by forming a desired LO frequency by using two or more frequency plans, This will reduce or eliminate the spurs.

For example, in the case of a channel frequency where spurs are a problem by the A frequency plan, the spurious problem is solved by switching to the B frequency plan. If the B frequency plan is also a problem, the C frequency plan is solved again. In some cases, two frequency plans may be satisfied according to a predetermined frequency width, but in some cases, three or more frequency plans may be required.

What is needed at this time is the design of the LO generation circuit for the I / Q signal generation and the design of the VCO with a wide operating frequency range to support different frequency plans.

As a VCO covering a wide operating frequency range, a VCO that oscillates a wideband frequency signal by switching a plurality of varactor diodes may be used, as described in US Pat. No. 5,739,730 (filed Dec. 22, 1995). As described in Korean Patent Laid-Open Publication No. 2004-48439 (filed December 3, 2002), a technique for extending a frequency tuning range through various dividers to a frequency signal oscillated in one VCO may be used. As described in 2004-0075736 (filed September 22, 2004), a frequency oscillation method may be used that selectively oscillates a particular frequency in a wide frequency band.

In some cases, more than one VCO may be required. For example, a method of using multiple VCOs with various frequency bands to extend the tuning range has been proposed (Shinichiro Azuma et al., "International solid state circuit conference 2004", pages 278-279).

Such a method of the present invention can be applied to both the zero-IF and low-IF structures, and is also applicable to conventional methods such as the super heterodyne method.

9 illustrates an example of applying such a structure, and illustrates a case where a plurality of frequency plans are used in a mobile communication system according to the present invention. As described in the prior art, the present invention selects a frequency plan that does not have one frequency plan, has two or more frequency plans, and minimizes the spur component according to a desired frequency. As shown in Fig. 9, the LO generation circuit can be divided into two types, for example, an LO generation circuit (normal channel) using four dividers, and an LO using six dividers. It may be a generation circuit (a spurious channel).

As described above, since the frequency of the crystal oscillator used (assuming 19.2 MHz) or desired channel information is known in advance, the frequency plan to be used is also determined at the time of implementation of the receiver or transmitter. Such information is made into a table to determine a frequency plan to be used according to each case. In the present embodiment, two types of normal channels and spurious channels are determined.

More specifically, in the case of using a VCO having a frequency of 4/5 Fc, the spurs are located at a considerable distance from the VCO's frequency by 800 kHz in the 81th channel. Less suppression causes problems such as the presence of relatively large spurs in the actual LO generated output signal unlike other channels.

However, as shown in FIG. 9, when the design is changed to have a VCO frequency corresponding to 6 / 7Fc (a spurious channel), the position of the spur (the 86th harmonic component, 19.2MHz * 86 = 1651.2MHz) is the 81st channel. Since the distance from (1644.857 MHz) to 6.34 MHz, the spurs are loop filtered by the loop filter, thereby eliminating the problem of frequency selectivity.

As a result, as can be seen in Figs. 8 and 9, when the 81st channel is made through the normal channel among the LO generation circuits, f _LO = (7/6) f _vco = (5/4) * 1535.2 MHz = 1919 MHz If the 81th channel is made through the spurious channel among the LO generation circuits, f _LO = (7/6) f _vco = (7/6) * 1644.857 MHz = 1919 MHz, so the same f _LO frequency is obtained, but the spurious channel is Unlike the normal channel, has the effect of significantly reducing the effect of spurs. However, as described above, in the LO generation circuit, a six-division period is separately required to implement a desired f _LO .

In the above embodiment, two frequency plans have been described with reference to FIG. 9, but the present invention is not limited to two frequency plans, and two or more frequency plans may be used to implement the core technical idea of the present invention. It will be obvious to those skilled in the art.

As described above, a method for reducing spurs in a transceiver according to the present invention, or a transceiver for reducing spurs, is provided so that the LO frequency f _vco (the output frequency of the PLL) is far from the harmonics of a predetermined reference clock frequency. By selectively using the LO frequency, the spurs generated due to the reference clock frequency can be made to be sufficiently suppressed by loop filtering of the phase locked loop (PLL).

In addition, in implementing a highly integrated RF circuit including a zero-IF or low-IF structure in which many functional blocks are integrated therein, the RF transceiver is a crystal oscillator which is an operation and reference frequency of a digital circuit existing inside a transceiver. The spurious signal that can be generated in the circuit can be reliably eliminated in advance. Therefore, performance degradation of the transceiver can be prevented.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalent claims.

Claims (26)

A method of reducing spurs in a transceiver having a phase locked loop (PLL) that generates an oscillation frequency input to a mixer for up or down cover, The phase is selected such that the LO frequency away from the harmonics of a predetermined reference clock frequency is selected such that the spur generated due to the reference clock frequency of the phase locked loop can be sufficiently suppressed by loop filtering of the phase locked loop. Selectively using a plurality of LO frequencies in a fixed loop. The method of claim 1, Wherein the plurality of LO frequencies is obtained through an LO having a wide operating frequency range. The method of claim 1, A method of reducing spurs, wherein a plurality of LO frequencies are obtained through one or more LOs. The method of claim 1, Selectively using the plurality of LO frequencies, Keep the LO frequency of the phase locked loop away from the harmonics of a predetermined reference clock frequency such that the spurs generated by the reference clock frequency of the phase locked loop can be sufficiently suppressed by loop filtering of the phase locked loop. Choosing to fall and Corresponding to the selected LO frequency, matching the output frequency of the phase locked loop to the input of the mixer via division. The method of claim 1, When the LO frequency is selected in the phase locked loop so that the LO frequency of the phase locked loop is far from the harmonics of a predetermined reference clock frequency, the spur is as small as 70 dBc relative to the output power of the phase locked loop. How to reduce spurs, characterized by the choice. The method of claim 1, And said mixer comprises an I / Q mixer. The method of claim 1, And said transceiver has a zero IF structure. The method of claim 1, And the transceiver has a low eyef structure. The method of claim 1, And said transceiver has a super heterodyne structure. The method of claim 1, And said transceiver is used only as a transmitter. The method of claim 1, And the transceiver is used only by the receiver. The method of claim 1, And the transceiver has a table for selecting the best LO frequency among a plurality of LO frequencies in advance. The method of claim 1, Through a controller, the LO in the phase locked loop is separated from the harmonics of a predetermined reference clock frequency so that the spur is as small as 70 dBc relative to the output power of the phase locked loop. A method of reducing spurs, characterized by the adaptive selection of frequencies. An antenna for transmitting and receiving RF signals, A mixer for up or down cover; and A phase locked loop (PLL) for generating an oscillation frequency input to the mixer, The LO frequency distant from the harmonics of the predetermined reference clock frequency is selected so that spurs generated due to the reference clock frequency of the phase locked loop can be sufficiently suppressed by loop filtering of the phase locked loop. And a spur to reduce spurs by selectively using a plurality of LO frequencies in said phase locked loop. The method of claim 14, And a plurality of LO frequencies are obtained through an LO having a wide operating frequency range. The method of claim 14, A spur reducing transceiver, wherein the plurality of LO frequencies are obtained through one or more LOs. The method of claim 14, Keep the LO frequency of the phase locked loop away from the harmonics of a predetermined reference clock frequency such that the spurs generated by the reference clock frequency of the phase locked loop can be sufficiently suppressed by loop filtering of the phase locked loop. If you choose to fall, Between the phase locked loop and the mixer, an LO for obtaining a frequency suitable for the input of the mixer for up-covering or down-covering, by dividing the output frequency of the phase-locking loop, corresponding to the selected LO frequency. Further comprising a generating circuit. The method of claim 14, When the LO frequency is selected in the phase locked loop so that the LO frequency of the phase locked loop is far from the harmonics of a predetermined reference clock frequency, the spur is about 70 dBc smaller than the output power of the phase locked loop. Transceiver to reduce spurs, characterized by the choice. The method of claim 14, And the mixer comprises an I / Q mixer. The method of claim 14, And the transceiver has a zero IF structure. The method of claim 14, And the transceiver has a low eyef structure. The method of claim 14, And the transceiver has a super heterodyne structure. The method of claim 14, And the transceiver is used only as a transmitter. The method of claim 14, And the transceiver is used only as a receiver. The method of claim 14, And the transceiver has a table for selecting the best LO frequency among a plurality of LO frequencies in advance. The method of claim 14, Adaptively adjusts the LO frequency in the phase locked loop so that the spur is as small as 70 dBc relative to the output power of the phase locked loop away from the harmonics of the predetermined reference clock frequency A transceiver for reducing the spurs, characterized in that it further comprises a controller for selecting.

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