KR100701066B1 - User interface system which user can control common voltage for diminishing flicker in liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a user interface system in a driving circuit of a liquid crystal display device, in which a user can reduce flicker by adjusting a common electrode voltage level.

The user interface system of the present invention includes a user input unit provided with an input unit so that a user can select one of the levels of the common electrode voltage having a plurality of levels, and a user input unit selected by the user from the user input unit. A counter unit for counting and outputting a common electrode voltage as a counter signal, a voltage divider for generating a plurality of primary reference voltages using an electrostatic source, and a plurality of 1s using the counter signal output from the counter unit A D / A converter converts the difference reference voltage into an analog signal, and a buffer unit for generating a common electrode voltage by buffering an output signal of the D / A converter.

Description

USER INTERFACE SYSTEM WHICH USER CAN CONTROL COMMON VOLTAGE FOR DIMINISHING FLICKER IN LIQUID CRYSTAL DISPLAY}

1 is a schematic diagram showing a liquid crystal panel and a driving circuit of a liquid crystal display device;

2 is an electrical equivalent circuit diagram of a pixel of a thin film transistor liquid crystal display device;

3 is a waveform diagram showing a relationship between a gate driving signal, a data signal, and a gate-on control signal;

4 is a block diagram of a user interface system according to an embodiment of the present invention;

5 is a block diagram of a voltage divider, a D / A converter, and a buffer unit in a user interface system according to an exemplary embodiment of the present invention;

6 is an internal block diagram of a D / A conversion unit in a user interface system according to an embodiment of the present invention.

(Name of the code for the main part of the drawing)

100: user input unit 200: counter unit

300: voltage divider 400: D / A converter

500: buffer part

410: first selector 420: second selector

430: reference voltage divider 440: third selector

411: First decoder 412: First delivery means

421 second delivery means 441 second decoder

442: third delivery means

OP: OP amplifier R1, ..., R6: resistor

C1: capacitors T11, ..., T164: transfer gate

Vcom: Common electrode voltages Vout1, ..., Vout5: Primary reference voltage

V1, V2: Secondary Reference Voltage UserIN: User Input Signal

CounterOUT: Counter output signal D / A OUT: D / A converter output signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor liquid crystal display (TFT-LCD). More specifically, a user who can improve a flicker phenomenon by adjusting a common electrode voltage Vcom. It relates to an interface system (User Interface System).

Cathode Ray Tube (CRT) cathode ray tube (CRT), which is the most widely used display device, has been spotlighted as a display device including TV and computer monitor because of its easy color and fast operation speed. However, the cathode ray tube has a disadvantage in that it is not only thick, due to the structural characteristics of securing a certain distance between the electron gun and the screen, but also has high power consumption and is considerably heavy, resulting in poor portability.

In order to overcome the disadvantages of the cathode ray tube as described above, various various display devices have been devised. Among them, the most practical device is a liquid crystal display (LCD).

Although the LCD is darker in screen and somewhat slower in operation than the cathode ray tube, each pixel may be operated according to a signal scanned on a plane without having an electron gun. It can be used as a very thin display device such as a wall-mounted TV. In addition, since the liquid crystal display device is light in weight and consumes considerably less power than the cathode ray tube, it is recognized that the liquid crystal display device is most suitable as a portable display device such as being used as a display of a battery operated notebook computer.

As described above, a liquid crystal display that is in the spotlight as a next generation display device is briefly shown in FIG. 1. Referring to FIG. 1, the liquid crystal display includes a liquid crystal panel 10, a gate driving circuit 15 and a source driving circuit 14 capable of driving the liquid crystal panel 10. The liquid crystal panel 10 has a structure in which a plurality of gate lines 12 and a plurality of data lines 11 cross each other in a matrix form on a substrate, and a thin film transistor 13 and a pixel are provided at the intersections thereof. It is. In addition, the gate driving circuit 15 sequentially applies a gate signal for turning on the thin film transistor 13 to the gate line 12, and the source driving circuit 14. The data signal is applied to the data line 11 so that the data signal can be transferred to the pixel through the thin film transistor driven by the scan signal.

In the liquid crystal display as described above, all the thin film transistors connected to the gate line 12 are turned on by a gate signal sequentially applied to the gate line 12 of the liquid crystal panel 10 in the gate driving circuit 15. When turned on, the data signal applied to the data line 11 of the liquid crystal panel 10 operates on the principle that the data signal is transferred to the pixel through the source and the drain of the turned-on thin film transistor.

2 illustrates an electrical equivalent circuit diagram of a pixel of the thin film transistor liquid crystal display device as described above. Referring to FIG. 2, in the thin film transistor liquid crystal display, individual pixels are divided into gate lines Gn-1 and Gn and data lines Dn and Dn-1, and applied to the drain electrodes of the thin film transistor TFT through the data lines. The data signal is charged in the pixel electrode and the storage capacitor (Cst) when the gate signal through the gate line is applied to the gate electrode of the thin film transistor. In the above, the pixel electrode is represented by the liquid crystal capacitor Clc, and the common electrode voltage is represented by Vcom. The data signal charged in the pixel electrode is lowered by the parasitic capacitance Cgd between the gate electrode and the drain electrode of the thin film transistor TFT, which is called a kick back voltage.

The thin film transistors connected to the respective pixel electrodes on the liquid crystal panel are not turned on or off independently, but all the thin film transistors connected to one gate line are turned on or off at the same time so that the data signal is applied to the pixel electrodes. Control what is applied. As described above, a data signal is applied to each gate line. This period is referred to as a horizontal line period, and a voltage in a saturation region must be applied to the gate line to turn on the thin film transistor. The gate signal becomes the turn-on voltage of the thin film transistor, and has a value of about 16 volts or more, and is generally referred to as a gate driving signal Von.

The gate driving signal as described above is distorted by the self-resistance and parasitic capacitance of the gate line and distorts the data signal charged in the pixel electrode, thereby using a gate on enable signal that controls the application of the gate driving signal. Therefore, the width of the gate driving voltage is reduced and applied to the pixel electrode.

3 is a waveform diagram illustrating a relationship between the gate driving voltage Von, the data voltage Vdata, and the gate-on control signal OE for one pixel. 2 and 3, when the gate driving voltage Von is applied, the thin film transistor TFT is turned on so that the data voltage is applied to the liquid crystal capacitor Clc, the storage capacitor Cst, and the parasitic capacitor Cgd. Is charged. The gate driving voltage Von is turned off by the gate on control signal OE and remains on-state only for a period shorter than the horizontal line period 1H. At this time, when the gate driving voltage Von is turned off, the applied data voltage is maintained at the pixel electrode at a value distorted by the kickback voltage due to the parasitic capacitor Cgd.

In order to prevent deterioration of the liquid crystal, the data signal applied to the pixel electrode is alternately applied with the positive and negative voltages with respect to the common electrode voltage Vcom. Therefore, the voltage charged in each pixel is applied with the polarity changed every frame. At this time, the effective value of the voltage actually applied to the liquid crystal is determined by the area between the data voltage and the common electrode voltage Vcom. Therefore, a constant voltage can be applied to the pixel electrode only when the area around the common voltage is symmetrical. have. However, since the kickback voltage Vk always acts in the direction of pulling down the data signal regardless of the polarity of the data signal, the positive data signal and the negative data signal have different values. This eventually causes the flicker to flicker.

The above-described flicker phenomenon has various causes, among which flicker occurs on the left and right sides of the panel according to the delay of the gate driving signal applied to the gate line at the input terminal and the output terminal, and the leakage current of the thin film transistor. By this, it can be divided into the flicker phenomenon which arises in the whole panel and the flicker phenomenon of the whole panel which arises by the leakage of liquid crystal.

In particular, in order to solve the flicker phenomenon on the left and right of the panel, conventionally, by adjusting the variable resistor inside the liquid crystal display module, the common electrode voltage is adjusted so that the positive data signal and the negative data signal are symmetric to the kickback voltage. Flicker caused is reduced.

However, since the dielectric constant of the liquid crystal constituting the pixel electrode changes depending on the applied voltage, it is difficult to accurately adjust the variable resistor, and because the accuracy of the variable resistor is limited, it is difficult to accurately compensate the kickback voltage.                         

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a user interface system that allows a user to more accurately improve flicker by adjusting the level of the common electrode voltage.

In order to achieve the above object, the user interface system of the present invention, the user input unit is provided with an input means to enable the user to select one of the level of the common electrode voltage having a plurality of levels, and A counter unit for counting and outputting the level of the common electrode voltage selected by the user from the user input unit as a counter signal, a voltage divider for generating a plurality of primary reference voltages using an electrostatic source, and in the counter unit A D / A converter converting a plurality of primary reference voltages into analog signals using the output counter signal, and a buffer unit for generating a common electrode voltage by buffering an output signal of the D / A converter. It is done.

The user input unit may use an input means such as a keyboard or a mouse.

The voltage divider may include a plurality of resistors connected in series with a constant voltage to generate a plurality of primary reference voltages at nodes between the resistors.

The D / A converter may include a first selector configured to generate a first voltage among secondary reference voltages from the plurality of primary reference voltages by using some bit signals among counter signals of the counter, and the first selector A second selector for generating a second secondary reference voltage from a plurality of primary reference voltages by using the counter signal of the counter used in the and a plurality of resistors are connected in series to output the first and second selectors A reference voltage divider for dividing and outputting a signal to a plurality of output voltages, and a plurality of output signals of the reference voltage divider using the remaining bit signals not used in the first and second selectors among the counter signals. And a third selector for selecting one output voltage.

The first selector converts a portion of the bit signal of the counter signal into a plurality of bit signals for selecting one voltage signal among a plurality of primary reference voltages, and the plurality of bit signals are output by the output signal of the first decoder. And a first transfer means for transferring a voltage signal selected from among primary reference voltages.

The first transfer means includes a plurality of transfer gates having two N-channel metal oxide semiconductor transistors or two P-channel metal oxide semiconductor transistors connected in parallel to the plurality of primary reference voltages. Characterized in that each is configured to be connected.

The second selector may include second transfer means for transferring a voltage signal selected from a plurality of primary reference voltages by an output signal of the first decoder.

The second transfer means may be configured such that a plurality of transfer gates in which two NMOS transistors or two PMOS transistors are connected in parallel are respectively connected to the plurality of primary reference voltages.

A second decoder for selecting one voltage signal from among a plurality of output voltages of a reference voltage divider by using an output signal of a counter unit not used in the first and second selectors; And third transmission means for outputting the voltage signal selected by the output signal.

The third transfer means is characterized in that a plurality of transfer gates in which two NMOS transistors or two PMOS transistors are connected in parallel are each connected to a plurality of output voltages of the reference voltage divider.

The buffer unit is provided with an output signal of the D / A converter to a non-inverting input terminal, an OP amplifier (feedback amplifier) for feeding back an output signal to the inverting input terminal, and a capacitor connected to the output terminal of the OP amplifier, characterized in that do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 shows a block diagram of a user interface system according to an embodiment of the invention. In FIG. 4, an example in which a 256-level common electrode voltage Vcom is generated using an 8-bit counter signal will be described.

Referring to FIG. 4, the user interface system of the present invention counters a user input unit 100 to which a user applies a signal to adjust a common electrode voltage and a user input input by the user input unit 100. A plurality of primary parts using the counter unit 200, a voltage divider 300 generating a plurality of primary reference voltages using the constant voltage VIN, and an output signal CounterOUT of the counter unit 200. A digital-to-analog converter 400 converting a reference voltage into an analog signal and a common electrode voltage Vcom by buffering the output signal D / A OUT of the D / A converter 400. It consists of a buffer unit 500 for generating a.

The user input unit 100 is an input means for the user to adjust the common electrode voltage Vcom. The user input unit 100 may include various input means such as a keyboard, a mouse, and a joystick.

The signal UserIN input from the user input unit 100 counts the level input by the user in the counter unit 200. In this case, in order to generate the 256-level common electrode voltage Vcom, the counter 200 counts an 8-bit digital signal.

The user input unit 100 and the counter unit 200 are parts configured in a part of a user system that allows a user to input a signal to a liquid crystal display.

On the other hand, the voltage divider 300, the D / A converter 400, and the buffer 500 are formed inside the module of the liquid crystal display.

The voltage divider 300 generates a plurality of primary reference voltages using the input voltage and transfers the primary reference voltages to the D / A converter 400. The D / A converter 400 uses the counter 200 to generate the first reference voltage. The primary reference voltage is converted into an analog signal by using the counter signal CounterOUT.

FIG. 5 illustrates a block diagram of a voltage divider 300 and a D / A converter 400 formed in a module of a liquid crystal display according to an exemplary embodiment of the present invention. . Referring to FIG. 5, the voltage divider 300 divides the electrostatic source VIN into five primary reference voltages Vout1, Vout5, and six resistors R1, ..., R6. This is connected in series.

As described above, the generation of the five primary reference voltages Vout1, ..., Vout5 is performed by using the two-bit signal among the eight bits of the output signal CounterOUT of the counter 200. This is to select the secondary reference voltage among Vout1, ..., Vout5). That is, two secondary reference voltages are generated by using a 2-bit signal among the counter output signals CounterOUT, and the first secondary of any four reference voltages in the primary reference voltages Vout1, ..., Vout5 is generated. Select the reference voltage and select the second secondary reference voltage from four reference voltages, including the remaining fifth reference voltage and the other three reference voltages.

The D / A converter 400 uses the output signal CounterOUT of the counter 200 to output an analog signal (D / A OUT) corresponding to a level corresponding to a signal UserIN input from 256 levels. Occurs.

The generated analog signal D / A OUT outputs a stable common electrode voltage Vcom through the buffer unit 500.

The buffer unit 500 includes an amplifier having a unit gain in order to output the correct common electrode voltage Vcom. That is, the OP amplifier OP which the analog signal D / A OUT output from the D / A converter 400 is provided to the non-inverting input terminal (+) and the output signal is fed back to the inverting input terminal (-). And a capacitor C1 connected to the output terminal of the OP amplifier OP to generate a stable common electrode voltage Vcom.

6 illustrates an internal block diagram of the D / A converter 400. Referring to FIG. 6, the D / A converter 400 uses the two-bit output signal of the 8-bit output signal CounterOUT of the counter 200 to output the primary reference voltages Vout1,..., Vout5. The first selector 410 for selecting the first secondary reference voltage (V1) from the four reference voltage (Vout2, ..., Vout5) of the four, and the other four primary reference voltages (Vout1, ...) , A second selector 420 for selecting a second secondary reference voltage V2 from Vout4, and a plurality of resistors connected in series (here, 64 resistors are connected in series to generate 64 output voltages). 6 other than the counter output signal CounterOUT used by the reference voltage divider 430 and the first and second selectors 410 and 420 for distributing the secondary reference voltages V1 and V2. One of 64 output voltages of the reference voltage divider 430 using a bit output signal It comprises a third selection unit 440 for selecting a pressure signal.

The first selector 410 selects one output voltage from the second primary reference voltage Vout2 to the fifth primary reference voltage Vout5, and selects the upper two of the eight bit counter output signals CounterOUT. A first decoder (2-4 decoder) 411 for converting a bit signal into a 4-bit signal and a fifth primary reference voltage from a second primary reference voltage Vout2 according to an output signal of the first decoder 411. First transmission means 412 for outputting one of the voltage signals from Vout5.

The first transfer means 412 is composed of a plurality of transfer gates (T11, ..., T14) in which two NMOS transistors having gate terminals connected to respective output terminals of the first decoder 411 in parallel. Each transfer gate T11, ..., T14 is connected to the second primary reference voltage Vout2 to the fifth primary reference voltage Vout5, respectively. Therefore, when the transfer gate selected by the first decoder 411 is turned on, the primary reference voltage connected thereto is output as the first secondary reference voltage V1.

The second selector 420 also has the same configuration as the first selector 410. Since the first decoder 411 output signal of the first selector 410 is used as it is, a separate decoder is required. Not. In addition, the first selector 410 selects one voltage signal from the second primary reference voltage Vout2 to the fifth primary reference voltage Vout5, but the second selector 420 selects the first one. One voltage signal is selected from the primary reference voltage Vout1 to the fourth primary reference voltage Vout4.

In this case, in addition to the arrangement illustrated in FIG. 6, the primary reference voltages Vout1,..., And Vout5 respectively selected by the first selector 410 and the second selector 420 are equally selected. The primary reference voltages Vout1, ..., Vout5 can be arranged so that they do not.

The third selector 440 includes a second decoder 441 and a third transfer means 442 to select one voltage signal from the 64 output voltages output from the reference voltage divider 430.

The second decoder (6-64 decoder: 441) is a 64-bit by using a lower 6-bit signal not used in the first and second selectors 410 and 420 among the 8-bit counter output signal CounterOUT. By converting into a signal of, one voltage signal from 64 output voltages generated by the reference voltage generator 430 can be selected.

The third transfer means 442 includes 64 transfer gates T101,..., T164 connected to the output terminal of the second decoder 441, respectively, of the reference voltage divider 430. It is connected to the output terminal, respectively, and outputs one signal by the output signal of the second decoder 441. The 64 transfer gates T101,..., And T164 have a structure in which two PMOS transistors or two NMOS transistors are connected in parallel like the first and second transfer means 412 and 421.

Therefore, the 8-bit counter outputs four levels of the 2-bit secondary reference voltages V1 and V2 and 256-level signals (4 × 64 = 256) by the 64 output signals of the reference voltage divider 430. One level signal D / A OUT may be selected using the signal CounterOUT.

Since one signal D / A OUT of the 256 levels selected in this way is output as the common electrode voltage Vcom through the buffer unit 500, the common electrode voltage Vcom can be adjusted to 256 levels, so that the signal D / A OUT is more precise. The flicker phenomenon can be adjusted accurately.

In the above example, the case in which the common electrode voltage of 256 levels is adjusted by using the counter output signal of 8 bits, more precise adjustment is possible.

As described in detail above, according to the user interface system of the present invention, the flicker phenomenon can be efficiently improved from the user's point of view of the display by adjusting the common electrode voltage.

In addition, since the system can be configured using a series connected resistor, there is an advantage that the chip size can be reduced and power consumption can be reduced.                     

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (11)

In the driving circuit of the liquid crystal display device, A user input unit provided with input means for allowing a user to select one level of the common electrode voltage among the levels of the common electrode voltage having a plurality of levels; A counter unit for counting the level of the common electrode voltage selected and input by the user from the user input unit and outputting the counter signal as a counter signal; A voltage divider for generating a plurality of primary reference voltages using an electrostatic source; A D / A converter converting a plurality of primary reference voltages into analog signals using the counter signal output from the counter unit; And a buffer unit configured to generate a common electrode voltage by buffering the output signal of the D / A converter. The method of claim 1, wherein the user input unit A user interface system comprising an input means such as a keyboard or a mouse. The method of claim 1, wherein the voltage divider Consists of a number of resistors connected in series to an electrostatic source, A user interface system generating a plurality of primary reference voltages at the nodes between each resistor. The method of claim 1, wherein the D / A converter A first selector for generating a first voltage among secondary reference voltages from the plurality of primary reference voltages by using some bit signals among the counter signals of the counter unit; A second selector for generating a second secondary reference voltage from a plurality of primary reference voltages using a counter signal of the counter used in the first selector; A reference voltage divider for connecting a plurality of resistors in series to divide and output the output signals of the first and second selectors to a plurality of output voltages; And a third selector for selecting one output voltage from among a plurality of output signals of the reference voltage divider by using the remaining bit signals not used in the first and second selectors among the counter signals. Interface system. The method of claim 4, wherein the first selector A first decoder for converting some bit signals of the counter signals into a plurality of bit signals for selecting one voltage signal among a plurality of primary reference voltages; And first transfer means connected to a plurality of primary reference voltages, respectively, for transferring a voltage signal selected from among the plurality of primary reference voltages by an output bit signal of the first decoder. 6. The method of claim 5 wherein said first delivery means is Two NMOS transistors and Two PMOS transistors consist of multiple transfer gates connected in parallel, And transmit a voltage signal selected from a plurality of primary reference voltages by an output signal of the first decoder. The method of claim 5 or 6, wherein the second selection unit And second transfer means for transferring a voltage signal selected from a plurality of primary reference voltages by an output bit signal of the first decoder. 8. The method of claim 7, wherein said second delivery means is Two NMOS transistors, or Two PMOS transistors consist of multiple transfer gates connected in parallel, And transmit a voltage signal selected from the plurality of primary reference voltages by an output signal of the first decoder. The method of claim 4, wherein the third selector A second decoder for converting a bit signal not used in the first and second selectors among the output bit signals of the counter unit into a plurality of bit signals to select one voltage signal from among the plurality of output voltage signals of the reference voltage divider; , And third transmission means for outputting a voltage signal selected from an output voltage of a reference voltage divider by an output signal of the second decoder. 10. The method of claim 9, wherein the third delivery means is Two NMOS transistors, or Two PMOS transistors consist of multiple transfer gates connected in parallel, And a voltage signal selected from a plurality of output voltages of the reference voltage divider by an output signal of the second decoder. The method of claim 1, wherein the buffer unit OP amplifier with unity gain, Consists of a capacitor connected to the output terminal of the OP amplifier, And the OP amplifier feeds an output signal of the common electrode voltage to the inverting input terminal and receives the output signal of the D / A converter as a non-inverting input signal.

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