KR100696692B1 - Organic light emitting display - Google Patents

Abstract

The present invention relates to an organic light emitting display device, in particular, an organic light emitting display device in which a display unit for displaying a screen and a peripheral circuit for driving pixels of the display unit are formed on the same substrate.

In the organic light emitting diode display of the present invention, a plurality of pixels, a resistance ladder unit, a predetermined number of voltage selectors, a predetermined number of buffers, and a data driver are formed on the same substrate. The resistance ladder section includes a plurality of resistors connected in series between the highest reference voltage and the lowest reference voltage. The voltage selector includes a plurality of switches connected to the resistance ladder unit through a plurality of contacts, and selects one of the plurality of voltages input through the contact through one of the plurality of switches. The buffer receives a voltage output from a predetermined number of voltage selectors, and outputs each as a reference voltage. The data driver changes the gray level of the image signal corresponding to the pixel to the data voltage based on the reference voltage, and transfers the data voltage to the pixel.

 OLED display, SOP, data driver, gamma, thin film transistor

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY}

1 illustrates a schematic configuration of an organic light emitting diode display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention.

3 is a schematic configuration diagram of a data driver according to an exemplary embodiment of the present invention.

4 is a graph showing the output data voltage of the digital analog converter for the gradation level of the red image signal, FIG. 5 is a graph showing the output data voltage of the digital analog converter for the gradation level of the green image signal, and FIG. This graph shows the output data voltage of the digital-to-analog converter with respect to the gradation level of the video signal.

7 is a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present invention.

8 is a schematic configuration diagram of a resistance ladder and an LSB decoder of a digital analog converter.

9 is a schematic configuration diagram of a reference voltage generator according to an exemplary embodiment of the present invention.

10 is a circuit diagram of a buffer unit of a reference voltage generator according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display device, and more particularly, to a display device in which a peripheral circuit such as a driving unit and a display area are formed on one same substrate.

Background Art In recent years, flat panel display devices such as display devices using liquid crystals and display devices using electroluminescence of organic materials have been widely used.

In general, the liquid crystal display, the organic light emitting display, and the like have an active driving method. Here, the active driving method means a driving method using an active element.

Recently, attempts have been made to use thin film transistors formed by depositing a semiconductor layer on an insulating substrate as such an active element.

Thus, by forming the thin film transistor on the insulating substrate, it is possible to form a circuit such as a driver or the like in addition to the display region on the insulating substrate. Such a panel-based system in which peripheral circuits such as a display area and a driver are formed on an insulating substrate is particularly referred to as a system on panel (SOP).

Meanwhile, in the display device, gamma correction is performed on the input video signal in consideration of characteristics of a panel to which the video signal is input.

However, in the case of the SOP type organic light emitting display device, since polysilicon, which is manufactured by a low temperature polysilicon (LTPS) process and varies in characteristics from each other, is used as a channel layer of the thin film transistor, a gamma required for each organic light emitting display device is required. The correction values may differ from one another. Therefore, the conventional gamma correction method using only one preset gamma correction circuit has a problem in that optimal gamma correction cannot be performed for each organic light emitting display device.

Meanwhile, the visibility of the image image of the light emitting display device may vary depending on the brightness of the surrounding environment. Specifically, when the surrounding environment is bright, the light emitting display device must output a brighter image image to obtain excellent visibility, and when the surrounding environment is dark, a darker image image must be output in order to achieve excellent contrast ratio. . As such, the output image image of the light emitting display device needs to be adjusted in a different manner according to the brightness of the surrounding environment. In that case, it may be necessary to perform gamma correction on each color.

As the SOP has been intensified, attempts have been made to form many circuits on the insulating substrate in addition to the driving unit. However, SOP type light emitting display devices in which an adjustable gamma correction circuit is formed on the same insulating substrate as the display area have not been attempted. It is not.

In order to solve the above technical problem, the present invention is to provide an organic light emitting display device in which a display area and adjustable R, G, and B gamma correction circuits are formed in one same substrate.

In addition, an aspect of the present invention is to provide an organic light emitting display device capable of outputting an image image having a luminance suitable for a change in brightness of a surrounding environment.

In an organic light emitting display according to an aspect of the present invention for solving this problem, a plurality of pixels, a resistance ladder unit, a predetermined number of voltage selectors, a predetermined number of buffers, and a data driver are formed on the same substrate. . The resistance ladder section includes a plurality of resistors connected in series between the highest reference voltage and the lowest reference voltage. The voltage selector includes a plurality of switches connected to the resistance ladder unit through a plurality of contacts, and selects one of the plurality of voltages input through the contact through one of the plurality of switches. The buffer receives a voltage output from a predetermined number of voltage selectors, and outputs each as a reference voltage. The data driver changes the gray level of the image signal corresponding to the pixel to the data voltage based on the reference voltage, and transfers the data voltage to the pixel.

According to another aspect of the present invention, an organic light emitting diode display includes a plurality of pixels, a first resistor, a second resistor, a third resistor, a first voltage selector, a second voltage selector, a third voltage selector, The first buffer portion, the second buffer portion, the third buffer portion, and the data driver are formed on the same substrate. The plurality of pixels each include a plurality of subpixels having respective colors. The first resistor unit is formed of a wire having a resistance value, and a first highest reference voltage and a first lowest reference voltage are applied to both ends thereof. The second resistor unit is formed of a wire having a resistance value, and the second highest reference voltage and the second lowest reference voltage are applied to both ends thereof. The third resistor unit is formed of a wire having a resistance value, and a third highest reference voltage and a third lowest reference voltage are applied to both ends thereof. The first voltage selector is connected to the first resistor through at least one first switch, and selects the first reference voltage through the first switch. The second voltage selector is connected to the second resistor through at least one second switch, and selects the second reference voltage through the second switch. The third reference voltage selector is connected to the third resistor through at least one third switch, and selects the third reference voltage through the third switch. The first buffer portions are each connected to a predetermined number of first voltage selection portions. The second buffer portions are each connected to a predetermined number of second voltage selection portions. The third buffer portions are each connected to a predetermined number of third voltage selection portions. The data driver changes the image signals corresponding to the subpixels of the first to third colors into data voltages based on the first to third reference voltages, and transfers the data voltages to the subpixels of the first to third colors, respectively. do.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

Hereinafter, an organic light emitting diode display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic plan view of an organic light emitting diode display according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display unit 100, a data driver 200, a reference voltage generator voltage generator 300, and a shift register formed on the same substrate. 400, a level shifter and an output buffer 500, and a DC / DC converter 600. Here, the shift register 400 and the level shifter and the output buffer 500 may be collectively referred to as a scan driver.

The display unit 100 includes a plurality of scan lines S _{1 to} S _n extending in a row direction and a plurality of data lines D1 to Dm extending in a column direction. At this time, a subpixel is formed at a point where one scan line S _{1 to} S _n and one data line D1 to Dm cross each other, and the subpixel is connected to the corresponding scan line and the data line. The subpixel includes a pixel driving circuit made of a thin film transistor and the like and an organic light emitting diode (OLED). The subpixels are selected according to the selection signals from the corresponding scanning lines to write the data signals from the data lines through the pixel driving circuit, and emit the OLEDs with brightness corresponding to the data signals. Subpixels emitting R color, subpixels emitting G color, and subpixels emitting B color may form one pixel, and the subpixels may have a stripe shape, a delta shape, or the like in the display unit 100. Can be arranged.

The data driver 200 is disposed on one side of the display unit 100 to transmit a data signal to the data lines D1 to Dm. In FIG. 1, the data driver 200 is disposed on only one side of the display unit 100, but the data driver 200 may be disposed on both sides of the display unit 100, respectively. In this case, the image signal is divided into odd and even image data and applied to the first data driver and the second data driver, respectively. In this case, the first data driver and the second data driver transmit odd and even image data signals to the display unit 100, respectively.

The reference voltage generator 300 is red (hereinafter referred to as 'R') and green (hereinafter referred to as 'G') to a digital to analog converter (hereinafter, referred to as 'DAC') of the data driver 200. ) And a blue reference voltage, a blue reference voltage, a blue reference voltage, and a blue reference voltage.

The shift register 400 sequentially outputs the selection signal to the level shifter and output buffer 500, and the level shifter and output buffer 500 receives the selection signal from the shift register 400 to set the voltage level of the selection signal. changes to be transmitted to the scan lines (S ₁ ~S _n) of the display section 100. the

The DC / DC converter 600 generates a negative voltage and transfers the negative voltage to the level shifter and the output buffer 500. This is because in general, the selection signal transmitted to the display unit 100 is a pulse signal swinging between the positive and negative voltages.

In such a pixel, for example, a pixel circuit as illustrated in FIG. 2 may be formed. 2 is an example of an equivalent circuit of a pixel according to an embodiment of the present invention. In FIG. 2, only the pixel circuit connected to the scan line Sn of the nth row and the data line Dm of the mth column is illustrated for convenience of description, and the pixel circuit of FIG. 2 is an analog voltage (hereinafter, referred to as a data voltage) as a data signal. Use In FIG. 2, the thin film transistor is illustrated as a PMOS transistor.

As shown in FIG. 2, the pixel circuit includes two thin film transistors SM and DM, a capacitor Cst, and an OLED. The switching transistor SM has a gate connected to the scan line Sm, a source connected to the data line Dm, and a drain of the switching transistor SM and a gate of the driving transistor DM connected. The source of the driving transistor DM is connected to the power supply voltage VDD, and the capacitor Cst is connected between the gate and the source of the driving transistor DM. The anode electrode of the OLED is connected to the drain of the driving transistor DM, and the cathode electrode of the OLED is connected to a power supply voltage VSS supplying a voltage lower than the power supply voltage VDD.

Next, the operation of the pixel circuit shown in FIG. 2 will be described in detail. First, when the selection signal is applied to the scan line Sn and the switching transistor SM is turned on, the data voltage is transferred to the gate of the driving transistor DM. . At this time, a voltage corresponding to the difference between the power supply voltage VDD and the data voltage V _DATA is stored in the capacitor Cst, so that the voltage V _GS between the gate and the source of the driving transistor DM is maintained for a predetermined period. The driving transistor DM applies a current I _OLED corresponding to the voltage V _GS between the gate and the source to the _OLED so that the OLED emits light. In this case, the current I _OLED flowing in the _OLED may be expressed as in Equation 1.

Here, the voltage between the gate and the source of the V _GS driving thin film transistor DM, V _TH represents a threshold voltage of the driving transistor DM, V _DATA represents a data voltage, and β represents a constant value.

It can be seen from Equation 1 that the amount of current I _OLED applied to the organic light emitting diode OLED is higher as the data voltage V _DATA is lower, and as the data voltage V _DATA is higher. Therefore, in the organic light emitting diode display, a lower grayscale image is displayed as the data voltage is lower, and a lower grayscale image is displayed as the data voltage is higher. However, Equation 1 is a case where the driving transistor DM is a PMOS, and when the driving transistor DM is an NMOS, a higher gray level image is displayed as the data voltage is higher, and a lower gray level image is as the data voltage is lower. Is displayed.

A manufacturing process of the SOP type organic light emitting diode display according to the exemplary embodiment of the present invention will be described below.

First, an amorphous silicon layer for forming a channel layer of a thin film transistor is deposited on an insulating substrate, the deposited amorphous silicon layer is converted into a polycrystalline silicon layer through a process such as low temperature polysilicon (LTPS), and the converted polycrystalline silicon The layers are patterned to form channels of all thin film transistors. The semiconductor channel layer formed as described above includes the display unit 100, the data driver 200, the reference voltage generator voltage generator 300, the shift register 400, the level shifter and the output buffer 500 according to an exemplary embodiment of the present invention. Form a channel of the thin film transistor included in. Next, an insulating film is formed in the formed channel, a gate electrode and a wiring metal layer are formed on the formed insulating film, an insulating film is formed in the formed metal layer, and then the metal layer for drain and source electrode and the organic light emitting element ( OLED) metal layer for anode electrode is formed sequentially. Next, an organic material layer is formed for each of R, G, and B as an organic light emitting diode (OLED), and a transparent cathode electrode is formed on the organic material layer.

The manufacturing process of the SOP-type organic light emitting diode display is described with an example of a thin film transistor having a top gate type structure in which a gate electrode is formed on the channel layer, but a thin film transistor having a bottom gate type structure in which the gate electrode is formed under the channel layer. Can also be used. The manufacturing process of the SOP type organic light emitting display device using the bottom gate type thin film transistor is described by the person skilled in the art of the SOP type organic light emitting display device using the thin film transistor of the top gate type structure described above. Since it can be easily configured from the manufacturing process, the detailed description of the present invention will be omitted.

Hereinafter, a data driver according to an exemplary embodiment of the present invention will be described in more detail with reference to FIG. 3.

3 is a schematic diagram of a data driver according to an exemplary embodiment of the present invention.

The shift register 210 generates a sampling signal from the start signal DSP according to the clocks DCLK and DCLKB, and sequentially shifts the sampling signal according to the clocks DCLK and DCLKB and outputs the sampling signal.

The sampling latch 220 includes a plurality of sampling circuits, and each sampling circuit sequentially samples the R, G, and B digital signals input according to the sampling signals sequentially transmitted from the shift register 210.

The holding latch 230 simultaneously outputs R, G, and B digital signals sequentially sampled from the sampling latch 220 according to the enable signal DENB.

The level shifter 240 changes the voltage level of the R, G, and B digital signals output from the holding latch 230 according to the input voltage LVDD to a level that can be used by the DAC 250.

The DAC 250 converts the input R, G, and B digital signals into R, G, and B data voltages respectively applied to the corresponding R, G, and B subpixels of the display unit 100. In this case, the DAC 250 uses R, G, and B reference voltages VR0 to VR8, VG0 to VG8, and VB0 to VB8 generated and input from the reference voltage generator 300 to output the R, G. , B Convert digital signal to data voltage of R, G, and B data.

Next, referring to FIGS. 4 through 10, the reference voltage generator 300 and the DAC 250 which perform gamma correction on the gamma characteristics of the R, G, and B subpixels and the input image data to be converted into the reference voltage are described in detail. Explain. 4 to 10, it is assumed that the input image data is a 6-bit digital signal.

First, the gamma characteristics of the R, G, and B subpixels will be described with reference to FIGS. 4 to 6. 4 to 6 are diagrams showing gamma characteristics of R, G, and B subpixels, respectively. 4 to 6, the horizontal axis represents the gray level of the input image data, and the vertical axis represents the data voltage applied to the R, G, and B subpixels so that the input image data is displayed at the corresponding gray level.

4 to 6, it can be seen that data voltages applied to the R, G, and B subpixels for the same gray level are different from each other. The difference in gamma characteristics according to R, G, and B colors is caused by different characteristics of the organic light emitting material used for each of R, G, and B.

Therefore, in the exemplary embodiment of the present invention, gamma correction is performed for each of R, G, and B to reflect the gamma characteristics of R, G, and B. In particular, the reference voltage supplied to the DAC 250 is determined for each of R, G, and B. do.

First, as shown in FIGS. 4 to 6, in the exemplary embodiment of the present invention, gamma correction is performed by dividing 6-bit image data into 8 sections based on the upper 3 bits. The reference voltage generator 300 supplies voltages corresponding to the minimum and highest gray levels of each section as reference voltages, and nine reference voltages are provided for each of R, G, and B in eight sections.

7 is a schematic diagram of a DAC 250 according to an embodiment of the present invention, and FIG. 8 schematically shows the resistance ladder unit 254 and the LSB decoder 253 of FIG. 7. The DAC 250 includes a plurality of DAC cells respectively corresponding to the plurality of data lines D1 to Dm. In FIG. 7, only the DAC cells corresponding to the three data lines D1 to D3 are illustrated for convenience of description. It is assumed that the three data lines D1 to D3 are connected to the R, G, and B subpixels respectively extending in the column direction.

As shown in FIG. 7, the DAC 250 includes a most significant bit (MSB) decoder 251, a reference voltage wiring unit 252, a least significant bit (LSB) decoder 253, and a resistance ladder unit 254. Include. Here, the MSB decoder 251 selects two consecutive reference voltages among the nine reference voltages VR0 to VR8, is responsible for the upper 3 bits, and the LSB decoder 253 is responsible for the lower 3 bits.

In the reference voltage wiring unit 252, nine horizontal wirings respectively transmitting the R reference voltages VR0 to VR8 input from the reference voltage generation unit 300, and nine nine transmissions of the G reference voltages VG0 to VG8, respectively. Nine horizontal wires that transmit the horizontal wires and the B reference voltages VB0 to VB8 respectively extend in the horizontal direction. The nine horizontal wires are connected to vertical wires extending in the vertical direction, respectively, and the vertical wires are connected to the MSB decoder 251.

Hereinafter, a detailed structure and operation of the MSB decoder 251, the reference voltage wiring unit 252, the LSB decoder 253, and the resistance ladder unit 254 will be described. Explain.

The MSB decoder 251 selects two consecutive horizontal lines from among nine horizontal lines in accordance with the upper three bits of the R digital data. In addition, two vertical wires for transferring the reference voltages VRH and VRL transferred to the two horizontal wires selected by the MSB decoder 251 extend in the vertical direction and are connected to the resistance ladder unit 254.

As shown in FIGS. 7 and 8, the resistance ladder unit 254 includes seven resistors R1 to R7 connected in series between two reference voltages VRH and VRL of the MSB decoder 251. The LSB decoder 253 includes eight thin film transistors SW1 to SW8 connected to the contacts of the reference voltage VRH and the resistor R1, the contacts of two adjacent resistors, and the contacts of the resistor R7 and the reference voltage VRL, respectively. ). The LSB decoder 253 selects one thin film transistor among the eight thin film transistors SW1 to SW8 according to the lower 3 bits of the R digital data and outputs the thin film transistor as an R data voltage. Although the detailed description of the detailed structure of the MSB decoder 251 has been omitted, the MSB decoder 251 may also be formed using a thin film transistor so as to be symmetrical to the LSB decoder 253.

Hereinafter, a method of generating data voltages for R, G, and B by the DAC 250 will be described in detail.

First, the DAC 250 receives a gamma corrected reference voltage from the reference voltage generator 300. Next, the DAC 250 divides the input image data at regular intervals according to the gradation level. As illustrated above, when the input image data is 6 bits, the MSB decoder 251 processes the upper 3 bits and the LSB decoder 253 processes the lower 3 bits. At this time, the input image data is first divided into upper 3 bits, that is, 8 gradation intervals. Therefore, the 6-bit input image data is separated into eight sections at eight gradation intervals. In this case, if the ends of two adjacent sections are the same, a total of nine boundary points are formed by adding seven contact points generated in eight sections and two end points of the first and last sections. The nine boundary points are set to nine reference voltages VR0 to VR8 input from the reference voltage generator 300 to the DAC 250, and the slope of each section is determined as the voltage difference between the nine boundary points. Then, as illustrated in FIGS. 4 to 6, a graph approximating a gamma correction curve may be formed in eight sections. As described above, the gray level in each section is generated by subdividing using the LSB decoder 253 and the resistance ladder unit 254.

9 is a diagram schematically illustrating a configuration of a reference voltage generator 300 according to an embodiment of the present invention.

As shown in FIG. 9, the reference voltage generator 300 includes an R resistor ladder 310, a G resistor ladder 320, a B resistor ladder 330, an R voltage selector 341 to 347, The G voltage selector 351 to 357, the B voltage selector 361 to 367, the R voltage buffer part 371 to 377, the G voltage buffer part 381 to 387, and the B voltage buffer part 391 to 397. Include.

The R resistance ladder part 310, the G resistance ladder part 320, and the B resistance ladder part 330 are formed by connecting a plurality of resistors in series, respectively, and are arranged in a vertical direction as shown in FIG. 9. Meanwhile, the R resistance ladder part 310, the G resistance ladder part 320, and the B resistance ladder part 330 may be arranged to overlap each other in the horizontal direction. When arranged in the horizontal direction as described above, the wiring of the circuit is complicated, and the circuit wiring space can be saved. The R resistance ladder part 310, the G resistance ladder part 320, and the B resistance ladder part 330 may be formed by adding a resistance material during the SOP manufacturing process, in which case the resistance ladder part is divided into a plurality of resistors. Rather, it may be a wiring to which a resistance material having a resistance value is added.

Highest reference voltages (VREFH-R, VREFH-G, VREFH-B) for each of R, G, and B and the lowest of the R resistor ladder 310, the G resistor ladder 320, and the B resistor ladder 330 Reference voltages VREFL-R, VREFL-G, and VREFL-B are applied, respectively. Here, the highest reference voltages (VREFH-R, VREFH-G, and VREFH-B) and the lowest reference voltages (VREFL-R, VREFL-G, and VREFL-B) are determined according to the characteristics of the organic light emitting materials of R, G, and B It may be set differently for each of R, G, and B according to gamma characteristics of R, G, and B separately obtained.

The R voltage selector 341 to 347, the G voltage selector 351 to 357, and the B voltage selector 361 to 367 are each an R resistor ladder 310, a G resistor ladder 320, and a B resistor. It is connected to the resistance ladder unit 330. do. The R voltage selectors 341 to 347, the G voltage selectors 351 to 357, and the B voltage selectors 361 to 367 are connected to a plurality of predetermined points of the resistor string connected in series, respectively, through a plurality of contacts. Generates a voltage between the highest reference voltage (VREFH-R, VREFH-G, VREFH-B) and the lowest reference voltage (VREFL-R, VREFL-G, VREFL-B) to generate the R voltage buffer unit 371 to 377, G It transfers to the voltage buffer parts 381-387 and B voltage buffer parts 391-397, respectively. Each voltage selector includes a plurality of switches respectively corresponding to a plurality of contacts connected to each resistor ladder unit, and selects one voltage among a plurality of voltages input through the plurality of contacts using the plurality of switches. do.

An R voltage selector 341 to 347, a G voltage selector 351 to 357, respectively connected to a resistance row of the R resistor ladder unit 310, the G resistor ladder unit 320, and the B resistor ladder unit 330, and As described above, the positions of the B voltage selectors 361 to 367 are positioned to correspond to boundary points obtained by dividing the input image data according to the gray level. The R voltage selector 341 to 347, the G voltage selector 351 to 357, and the B voltage selector 361 to 367 are each an R resistor ladder 310, a G resistor ladder 320, and a B resistor. The ladder unit 330 is separated into sections having a plurality of resistance values.

As shown in the previous example, if there are a total of nine boundary points, the remaining 7 The R voltage selectors 341 to 347, the G voltage selectors 351 to 357, and the B voltage selectors 361 to 367 are disposed at the generation positions of the two reference voltages. Arrangement positions of the R voltage selectors 341 to 347, the G voltage selectors 351 to 357, and the B voltage selectors 361 to 367 may be formed to have different resistance values from each other to generate different reference voltages. Can be. In this case, when the number of switches in each voltage selector is three, the R voltage selectors 341 to 347, the G voltage selectors 351 to 357, and the B voltage selectors 361 to 367 are input to three inputs. One of the voltages is selected and output.

In addition, since the reference voltages for R, G, and B are generated from the highest reference voltage and the minimum reference voltage for each of the R, G, and B, the highest reference voltage and the minimum reference for each of the R, G, and B inputted to the reference voltage generator 300. By adjusting the voltage, the data voltage output from the DAC 250 to the display unit 100 may be adjusted. Therefore, when the highest reference voltage and the minimum reference voltage for each of R, G, and B are increased, the data voltage applied to the display unit 100 is increased, so that the luminance of the image image output from the organic light emitting display device is lowered. On the other hand, when the highest reference voltage and the minimum reference voltage for each of R, G, and B are lowered, the data voltage is lowered, so that the brightness of an image image output from the organic light emitting diode display is increased.

The R voltage buffers 371 to 377, the G voltage buffers 381 to 387, and the B voltage buffers 391 to 397 are R voltage selectors 341 to 347 and G voltage selectors 351 to 357, respectively. And are connected to the outputs of the B voltage selectors 361 to 367. The R voltage buffers 371 to 377, the G voltage buffers 381 to 387, and the B voltage buffers 391 to 397 include an R voltage selector 341 to 347, a G voltage selector 351 to 357, And function as a buffer for the reference voltages for R, G, and B generated and output by the B voltage selectors 361 to 367.

10 shows an embodiment of the voltage buffer unit. As shown in FIG. 10, the voltage buffer unit includes the thin film transistors T1 -T5.

Here, transistors T1, T2, and T5 are shown as PMOS transistors, and transistors T3 and T4 are shown as NMOS transistors. In this case, the two transistors T1 and T2 have the same magnitude and the same threshold voltage Vth, and the sizes of the two transistors T3 and T4 are also the same.

As illustrated in FIG. 10, gates of two transistors T1 and T2 having a source connected to a power supply voltage VDD are connected to each other, so that the two transistors T1 and T2 form a mirror. In the transistor T1, a source is connected to the drain of the transistor T3, and a gate and a drain are connected to form a diode connection structure. The transistor T2 has a source connected to the drain and the input of the transistor T4. An input voltage is applied to a gate of the transistor T3, and a gate and a drain of the transistor T4 are connected to an output terminal. The transistors T3 and T4 have a source connected to each other, and are connected to a source of the transistor T5. The voltage VSS is connected to the drain of the transistor T5, and the gate and the drain of the transistor T5 are connected to form a diode connection structure.

When the voltage output from the R voltage selector 341 to 347, the G voltage selector 351 to 357, and the B voltage selector 361 to 367 is applied to the gate of the transistor T3, the transistor T3 is applied. It is turned on so that a current flows through the transistors T1, T3, and T5. At this time, since the two transistors T1 and T2 have the same size and are connected in a mirror form, currents having the same magnitude as those flowing through the transistors T1 and T3 also flow through the transistors T2 and T4. Since the sizes of the two transistors T3 and T4 are also the same, the gate of the transistor T4 receives the same voltage as the gate voltage of the transistor T3. Accordingly, the voltage buffers 371-377, 381-387, and 391-397 output voltages having the same magnitude as the voltages output from the voltage selectors 341 to 347, 351 to 357, and 361 to 367 as reference voltages.

As described above, the R voltage buffers 371 to 377 and the G voltage buffer are respectively provided at the output terminals of the R voltage selectors 341 to 347, the G voltage selectors 351 to 357, and the B voltage selectors 361 to 367. By connecting the sections 381 to 387 and the B voltage buffer sections 391 to 397, it is possible to improve the uniformity of the image image, the accuracy of the output voltage, and the TFT characteristic margin.

Hereinafter, a difference between an organic light emitting display device using the voltage buffer units 371 to 377, 381 to 387, and 391 to 397 and an organic light emitting display device not using the same will be described through a comparative example.

As a comparative example, the R voltage buffer unit (3) at the output terminals of the R voltage selectors 341 to 347, the G voltage selectors 351 to 357, and the B voltage selectors 361 to 367 of the reference voltage generator 300, respectively. 371 to 377, G voltage buffers 381 to 387, and B voltage buffers 391 to 397 without connecting the analog buffer to the output of the DAC 250, except that the configuration The element used was an organic light emitting display device constructed in the same manner as in the embodiment of the present invention.

Table 1 shows the uniformity of the image image, the accuracy of the output voltage, and the TFT characteristic margin of the organic light emitting display device of the embodiment of the present invention and the organic light emitting display market value of the comparative example.

As can be seen from Table 1, the organic light emitting display device of the embodiment using the voltage buffers 371 to 377, 381 to 387, and 391 to 397 is uniform in image image compared to the organic light emitting display device of the comparative example which does not use the same. It is excellent in terms of performance, accuracy of output voltage and acceptability of TFT characteristic margin.

In general, as described above, the SOP type organic light emitting diode display has a slight variation in characteristics since the amorphous silicon layer is converted to polycrystalline polysilicon through an LTPS process to form a thin film transistor. Therefore, one gamma correction circuit may not be suitable for all organic light emitting display devices having variations in characteristics from each other. However, the reference voltage generator 300 of the SOP type organic light emitting diode display according to an exemplary embodiment of the present invention includes an R voltage selector 341 to 347, a G voltage selector 351 to 357, and a B voltage selector. The gamma corrected reference voltages may be reselected for each color by using the units 361 to 367 to implement optimized gamma correction circuits even in an organic light emitting display device having variations in characteristics.

 In addition, since the reference voltages for R, G, and B are generated from the highest reference voltage and the minimum reference voltage for each of the R, G, and B, the highest reference voltage and the minimum reference for each of the R, G, and B inputted to the reference voltage generator 300. By adjusting the voltage, the data voltage output from the DAC 250 to the display unit 100 can be adjusted. Therefore, when the highest reference voltage and minimum reference voltage for each of R, G, and B are increased, the data voltage applied to the display unit 100 is increased, so that the luminance of the image image output from the organic light emitting display device is lowered. On the other hand, when the highest reference voltage and the minimum reference voltage for each of R, G, and B are lowered, the data voltage is lowered, thereby increasing the luminance of the image image output from the OLED display.

In the organic light emitting diode display according to the exemplary embodiment of the present invention, the reference voltage generator 300 generates gamma-corrected R reference voltages, G reference voltages, and B reference voltages for each of R, G, and B, and transmits them to the DAC 250. The DAC 250 generates an input gray level data voltage for each of R, G, and B based on the R, G, and B digital signals input based on the R reference voltage, the G reference voltage, and the B reference voltage. Supply to the data line of each pixel of 100). Therefore, the organic light emitting diode display according to the exemplary embodiment of the present invention can express the gamma-corrected optimized image for each of R, G, and B.

In addition, the organic light emitting diode display according to the exemplary embodiment of the present invention uses the highest reference voltage and the lowest reference voltage different for each of R, G, and B, so that the highest reference voltage and the lowest suitable for the characteristics of the light emitting material for each color used in the display unit 100 are provided. Using the reference voltage, gamma correction optimized for each color is possible. Specifically, by changing the reference voltage generated by the reference voltage generator 300 according to the brightness of the external environment of the organic light emitting diode display, the organic light emitting diode display according to the exemplary embodiment of the present invention outputs an image image suitable for the brightness of the external environment. can do.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

The organic light emitting diode display of the present invention may perform separate gamma correction according to each color displayed. Specifically, even when the organic light emitting materials used in the organic light emitting diode display have different characteristics for each color, and thus require gamma correction for different data voltages and colors, the organic light emitting diode display of the present invention is used for each color. By selecting and using the highest reference voltage and the lowest reference voltage suitable for the respective characteristics of the organic light emitting materials, gamma correction suitable for the gamma characteristic for each color can be performed.

The organic light emitting diode display of the present invention may configure a gamma correction circuit optimized for the organic light emitting diode display by adjusting a gamma correction circuit for each of R, G, and B. Therefore, the gamma correction circuit optimized for each organic light emitting display device may be configured by reflecting a deviation that may occur in the manufacturing process of the SOP type organic light emitting display device.

In addition, the organic light emitting diode display of the present invention can output an image image having visibility always suitable for a change in brightness of the surrounding environment. For example, it is difficult to recognize a display image in an environment having high brightness, such as outdoors, in which case the organic light emitting diode display of the present invention lowers the input reference data voltage and the lowest reference voltage, thereby lowering the input gray scale data voltage to give an image image. Can increase the luminance. On the contrary, in a dark room, a high contrast ratio is required for the image image. In this case, the organic light emitting diode display of the present invention adjusts the highest reference voltage and the lowest reference voltage upward to increase the input grayscale data voltage to increase the brightness of the image image. Can be lowered. As described above, the organic light emitting diode display of the present invention may dynamically adjust the brightness of the image image by monitoring the brightness of the surrounding environment. Therefore, by adjusting the brightness of the image image according to the brightness of the surrounding environment, it is possible to satisfy high visibility while minimizing power consumption.

Claims (14)

A plurality of pixels formed on the substrate, A resistance ladder unit formed on the substrate and including a plurality of resistors connected in series between a highest reference voltage and a lowest reference voltage; And a plurality of switches formed on the substrate and connected to the resistance ladder unit through a plurality of contacts, wherein one of the plurality of voltages input through the contact through one of the plurality of switches is applied. A predetermined number of voltage selection units to select, A predetermined number of buffers formed on the substrate, each receiving a voltage output from the predetermined number of voltage selection units, and outputting a respective voltage as a reference voltage; A data driver formed on the substrate and configured to change a gray level of an image signal corresponding to the pixel to a data voltage based on the reference voltage, and to transfer the data voltage to the pixel; The reference voltage is a data voltage corresponding to a specific gray level among a plurality of gray levels belonging to each group when the gray level of the image signal is divided into a plurality of groups based on at least one most significant bit. delete delete The method of claim 1, The specific gray level is a gray level corresponding to a boundary of each group. The method of claim 4, wherein The data driver, A first decoder configured to select two reference voltages from among the predetermined number of reference voltages, A plurality of resistors connected in series between the two selected reference voltages, And A second decoder for selecting a contact corresponding to the gray level of the video signal among a plurality of contacts formed by the series connected resistors from bits except the at least one most significant bit in the gray level of the video signal An organic light emitting display device comprising a. The method of claim 1, The buffer is A first transistor having a source connected to the first power voltage and having a gate and a drain connected to each other, A second transistor having a source connected to the first power voltage and a gate connected to the gate of the first transistor; A third transistor having a drain connected to the drain of the first transistor and a gate connected to an input terminal, and A fourth transistor having a drain connected to a drain and an output terminal of the second transistor and having a gate and a drain connected to each other; An organic light emitting display device comprising a. The method of claim 6, The buffer is And a fifth transistor having a source connected to the sources of the third and fourth transistors, a drain connected to a second power supply voltage, and a gate and a drain connected to each other. The method according to any one of claims 1, 4, 5, 6 or 7, The resistance ladder section and the predetermined number of voltage selection section, The organic light emitting diode display of each of the first to third colors of the image signal. The method of claim 8, The organic light emitting diode display of which the first to third highest reference voltages and the first to third lowest reference voltages respectively applied to the resistance ladder units of the first to third colors are set differently. A plurality of pixels formed on the substrate, each pixel including a plurality of subpixels having respective colors; A first resistor unit formed of a wiring having a resistance value on the substrate and having a first highest reference voltage and a first lowest reference voltage applied to both ends thereof; A second resistor unit formed of a wiring having a resistance value on the substrate and having a second highest reference voltage and a second lowest reference voltage applied to both ends thereof; A third resistor formed on the substrate and having a resistance value, and having a third highest reference voltage and a third lowest reference voltage applied to both ends thereof; A predetermined number of first voltage selectors formed on the substrate and connected to the first resistor through at least one first switch and selecting a first reference voltage through the first switch; A predetermined number of second voltage selectors formed on the substrate and connected to the second resistor through at least one second switch and selecting a second reference voltage through the second switch; A predetermined number of third voltage selectors formed on the substrate and connected to the third resistor through at least one third switch and selecting a third reference voltage through the third switch; A predetermined number of first buffer units formed on the substrate and connected to the predetermined number of first voltage selection units, respectively; A predetermined number of second buffer units formed on the substrate and connected to the predetermined number of second voltage selection units, respectively; A predetermined number of third buffer units formed on the substrate and connected to the predetermined number of third voltage selection units, respectively; An image signal formed on the substrate and corresponding to the sub-pixels of the first to third colors, respectively, to the data voltage based on the first to third reference voltages, and the data voltage to the first to third colors; It includes a data driver for transmitting each of the sub-pixels of color, The first to third reference voltages are organic light emitting diodes that are data voltages corresponding to a specific gray level among a plurality of gray levels belonging to each group when the gray level of the image signal is divided into a plurality of groups based on at least one most significant bit. Display device. The method of claim 10, The data driver, A first decoder configured to select two first to third reference voltages from each of the plurality of first to third reference voltages, A plurality of first resistors connected in series between the selected two first reference voltages, A plurality of second resistors connected in series between the selected two second reference voltages, A plurality of third resistors connected in series between the selected two first reference voltages, and A second decoder for selecting a contact corresponding to the gray level of the video signal among a plurality of contacts formed by the first to third resistors connected in series from bits except for the at least one most significant bit in the gray level of the video signal An organic light emitting display device comprising a. delete The method of claim 10, The buffer is A first transistor having a source connected to the first power voltage and having a gate and a drain connected to each other, A second transistor having a source connected to the first power voltage and a gate connected to the gate of the first transistor, A third transistor having a drain connected to the drain of the first transistor and a gate connected to an input terminal, and A fourth transistor having a drain connected to a drain and an output terminal of the second transistor and having a gate and a drain connected to each other; An organic light emitting display device comprising a. The method according to any one of claims 10, 11 or 13, The first to third highest reference voltages are set differently, and the first to third lowest reference voltages are set differently.

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