KR100695653B1 - Liquid crystal display panel and manufacturing method of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor liquid crystal panel and a method of manufacturing the same, and to a thin film transistor liquid crystal panel and a method of manufacturing the same, which provide a light blocking wall around an active channel to improve a flicker phenomenon according to the present invention. will be.

An object of the present invention is to block light incident on an active channel region by separately forming a barrier wall around the active region to block light incident on an active region where the data line and the gate line overlap each other.

Thin Film Transistors, Active Channels, Leakage Current, Flicker

Description

Liquid crystal display panel and its manufacturing method {LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURING METHOD OF THE SAME}

1 is a plan view of a lower substrate of a thin film transistor liquid crystal display panel according to the related art.

2 is a cross-sectional view of a lower substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of a lower substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a cross-sectional view of a lower substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

5 to 16 are process diagrams illustrating a manufacturing process of a lower substrate of the liquid crystal display according to the present invention shown in FIG.

FIG. 17 is a view for explaining a process of etching contact after filling a contact hole with metal to create a barrier wall according to the present invention.

18 is a cross-sectional view of a manufacturing process of a lower substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

19 is a cross-sectional view of a lower substrate of a liquid crystal display according to an embodiment of the present invention.

FIG. 20 is a partial cross-sectional view illustrating a portion of a cross-sectional view taken along line C-C 'of FIG. 9.

21 to 32 are process diagrams illustrating a manufacturing process of a lower substrate of the liquid crystal display according to the present invention shown in FIG.

FIG. 33 is a partial cross-sectional view illustrating a portion of a cross-sectional view taken along the line D-D 'of FIG. 25.

34 to 37 are views illustrating part of the manufacturing process of the lower substrate of the liquid crystal display according to the exemplary embodiment of the present invention.

***** Explanation of symbols on the main parts of the drawing *****

1: transparent substrate 10: storage capacitor lower electrode

14: dielectric layer 15: lower BM

16, 17: 1-1, 1-2 insulating layer 18: first insulating layer

20: silicon thin film 21: gate insulating film

30: lower horizontal barrier wall 94: upper horizontal barrier wall

36: upper contact electrode of the storage capacitor

37: contact electrode under the storage capacitor

40, 41, 102, 103: first, second, third and fourth barrier walls

35: gate electrode 46: source electrode

45: second connection electrode 47: drain electrode

48: first connecting electrode 66: third connecting electrode

70: upper BM 80: pixel electrode

The present invention relates to a light blocking wall of a liquid crystal display device of a thin film transistor. More specifically, the light blocking wall for blocking light incident around an active channel of a thin film transistor is provided around the active layer of the thin film transistor. A thin film transistor liquid crystal panel and a method of manufacturing the same.

Conventionally, when light enters an active channel located below the gate electrode of a liquid crystal panel including a thin film transistor, leakage current is generated, causing flicker due to leakage current, thereby degrading image quality.

1 is a plan view of a lower substrate of a thin film transistor liquid crystal display panel according to the related art. This will be described with reference to FIG. 1. The gate line 35 is formed in the horizontal direction, and the data line 54 is provided in the vertical direction. In the lower portion of the data line 54, the silicon thin film 20 is formed to have a substantially “b” shape. The data line 54 is connected to one end of the silicon thin film 20 through the source electrode 46, and the other end of the silicon thin film connects the drain electrode 47 and the third connection electrode 66 to the pixel electrode and the drain electrode. Electrode) is connected to the pixel electrode 80. An active channel 19 is formed in a region where the silicon thin film 20 and the gate line 35 meet each other.

When unwanted light enters the active channel 19 region of the liquid crystal display, leakage current is generated, which causes the screen to flicker. This mainly occurs because light incident from the light source is reflected to the metal film or the like constituting the liquid crystal display element and is incident on the active channel 19 region. In particular, in the case of a liquid crystal device used in a liquid crystal projector, a high brightness light source is used, which causes more serious problems. In order to prevent the reflected light from entering the active channel 19 region, a lower black matix (BM) and an upper black matrix (BM) are used. The lower BM serves to prevent the light reflected by the anti dust glass or the lens attached to the lower substrate of the liquid crystal panel from re-injecting and entering the active channel region, and the upper BM is incident from the light source. The main function is to prevent the light from entering the area except the pixel area.

However, even with the upper BM and the lower BM there is a problem that can not sufficiently prevent the incident light diffused into the active channel.

An object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the liquid crystal display panel to block the light incident to the active channel of the switching element constituting the switching element of the liquid crystal.

It is still another object of the present invention to provide a liquid crystal display panel and a method of manufacturing the same, wherein a barrier wall for blocking light incident to the active channel is formed around a switching element that does not transmit light, and thus does not adversely affect the aperture ratio.

An object of the present invention is to a lower BM, a thin film transistor used as a switching element, a gate line for applying a voltage to the thin film transistor gate, a data line for applying a data voltage to a drain of the thin film transistor, an upper BM and the thin film transistor. A liquid crystal display panel which transmits or blocks light by changing an arrangement of liquid crystal materials through a liquid crystal material between a lower substrate having a pixel electrode driven by the upper substrate and an upper substrate having an opposite electrode facing the pixel electrode. A lower substrate is formed on the transparent substrate in the order of the lower BM, the switching element, the data line, the upper BM and the pixel electrode, between the lower BM and the switching element, between the switching element and the data line. Between the data line and the upper BM and between the upper BM and the A first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer are respectively provided between the small electrodes, and the first insulating layer is spaced apart from the left and right of the channel along a channel length direction of the switching element. A hole having a predetermined size is formed in the upper portion of the layer toward the lower substrate, and the first barrier wall and the second barrier wall are filled with the impermeable material.

An object of the present invention is a lower BM, a thin film transistor used as a switching element, a gate line for applying a voltage to the gate of the thin film transistor, a data line for applying a data voltage of the thin film transistor drain, the upper BM and the thin film Manufacturing a liquid crystal display panel that transmits or blocks light by changing the arrangement of liquid crystal materials through a liquid crystal material between a lower substrate having a pixel electrode driven by a transistor and an upper substrate having an opposite electrode facing the pixel electrode. The method of manufacturing the lower substrate may include forming a lower BM by depositing and patterning an opaque layer on the transparent substrate and depositing a first insulating layer on the transparent substrate and the lower BM. And the active layer of the thin film transistor on the first insulating layer. A third step of forming and a fourth step of depositing a gate insulating film on the first insulating layer and the active layer of the thin film transistor and a predetermined distance from the active layer along the longitudinal direction of the active layer on the first insulating layer and the gate insulating film Steps 5-1 for forming the first and second vertical grooves formed at both sides in a distant position, and Step 5-2 for filling the first and second vertical grooves with an impermeable material and a gate on the gate insulating layer. A step 6-1 of depositing a material forming a line and a step 6-2 of forming a pattern of the deposited gate line using a mask; and a step of depositing a second insulating layer on the gate line and the gate insulating layer. An eighth step of forming a contact hole crossing the second insulating layer vertically and contacting the source and the drain of the thin film transistor; A ninth step of forming a source electrode and a drain electrode of the thin film transistor by filling a metal in the contact hole; and a tenth step of depositing a third insulating layer on the second insulating layer, the source electrode, and the drain electrode. An eleventh step and a third insulating layer crossing the third insulating layer vertically to form a contact hole connected to the drain electrode, and filling the contact hole with a metal to form a third connection electrode connected to the drain electrode; And a twelfth step of depositing a fourth insulating layer on the third connecting electrode, and forming a contact hole vertically crossing the fourth insulating layer and contacting the third connecting electrode, wherein the pixel is connected to the contact hole. A thirteenth step of forming an electrode can also be achieved by a method for manufacturing a liquid crystal display panel.

The features, advantages and preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 is a cross-sectional view of a lower substrate of a liquid crystal display according to an exemplary embodiment of the present invention. A storage capacitor lower electrode 10 formed of a conductive material is provided on the transparent substrate 1, and the dielectric layer 14 is stacked thereon, and the lower BM 15 is further stacked to form a storage capacitor. At this time, the lower BM 15 is also used as the upper electrode of the storage capacitor using a conductive impermeable material. After stacking the first insulating layer 18 thereon, the active layer 20 is provided with a pattern, and a gate insulating film 21 is deposited thereon. In order to prevent light incident from the upper substrate from being diffusely reflected to the active layer, the gate insulating layer 21 and the first insulating layer 18 are surrounded by the gate line 35 along the length direction of the active layer 20 to surround the active layer. The first blocking wall 41 and the second blocking wall 42 penetrating are formed of an opaque material. After the second insulating layer 49 is deposited and formed on the data line 53, the third insulating layer 54 is formed again. The upper BM 70 is patterned on the third insulating layer 54, the fourth insulating layer 71 is formed on the upper portion of the third insulating layer 54, and the alignment layer is formed after forming the pixel electrode 80 thereon. Has The first blocking wall 41 and the second blocking wall 42 are formed over the entirety or a part of the first insulating layer 18 along the longitudinal direction of the active layer 20, thereby forming the upper BM (in addition to the gate line 35). 70) and / or the lower BM 15 can now more reliably block the diffused light passing through.

3 is a cross-sectional view of the lower substrate of the liquid crystal display device shown in FIG. 3 in the structure of the lower substrate of the liquid crystal display device shown in FIG. 2. There is a difference in that it further includes (30). Due to such a difference, the lower horizontal blocking wall 30 is provided on the first insulating layer 16, and the second insulating layer is disposed on the first insulating layer 16 and the lower horizontal blocking wall 30. After the deposition of the layer 17 and before the active layer 20 is applied, the first and second insulating layers 17 may be planarized. The channel region of the active layer 20 is surrounded by the first barrier wall 41, the second barrier wall 42, the gate line 35, and the lower horizontal barrier wall 30 to further diffuse diffused light. You can block more reliably.

4 is a cross-sectional view of a lower substrate of a liquid crystal display according to an exemplary embodiment of the present invention. As a lower substrate of a liquid crystal display device in which a gate electrode or a gate line 35 is provided below the active layer 20, the gate line 35, the third blocking wall 92, the fourth blocking wall 93, and the upper substrate. A structure in which the channel region of the active layer is surrounded by the horizontal barrier wall 94 is proposed. A storage capacitor lower electrode 10 formed of a conductive material is provided on the transparent substrate 1, and the dielectric layer 14 is stacked thereon, and the lower BM 15 is further stacked to form a storage capacitor. At this time, the lower BM 15 is also used as the upper electrode of the storage capacitor using a conductive impermeable material. After laminating the first insulating layer 18 thereon, the gate line 35 is formed. After the gate insulating layer 91 is formed on the gate line 35, the active layer 20 is patterned on the gate insulating layer 91. A tenth insulating layer 89 is provided on the active layer 20, and an upper horizontal barrier wall 94 is provided on the active layer 20, and each of the active layers 20 is filled with an impermeable material with a channel region interposed therebetween. The third blocking wall 92 and the fourth blocking wall 93 are formed. The eleventh insulating layer 95 is provided on the upper portion thereof, and the data line 53 is provided on the pattern. After the third insulating layer 54 is formed on the eleventh insulating layer 95 and the data line 53, the upper BM is deposited, and then a fourth insulating layer 71 is formed on the upper BM. After the pixel electrode 80 is formed on the substrate, the alignment film is formed. In the embodiment shown in FIG. 4, diffuse reflection is caused by blocking around the channel region of the active layer 20 with the third blocking wall 92, the fourth blocking wall 93, the gate line 35, and the upper horizontal blocking wall 94. It is now possible to more reliably block the light.

5 to 15 are process diagrams illustrating a manufacturing process of a lower substrate of the liquid crystal display according to the present invention shown in FIG. 3. The lower substrate of the liquid crystal display according to the present invention shown in FIG. 2 has a difference in that the lower substrate shown in FIG. 3 and the lower horizontal blocking wall 30 are not provided. Slightly different from the embodiment shown in FIG. 3 except for some process differences, such as having a first insulating layer 16 and a first insulating layer 18 corresponding to the 1-2 insulating layer 17. The person skilled in the art through the modification can be easily invented, so the detailed description will be omitted. In FIGS. 5 to 15, two views, which consist of an upper view and a lower view, are shown at the same time. The upper view shows a layout plan view of the lower substrate, and the lower view shows a cross-sectional view of the lower substrate. As shown in FIG. 5, the cross-sectional view shown at the bottom is a cross-sectional view taken along the line segment direction in the "B" direction after unfolding a cross-sectional view cut in the line segment direction in the substantially "A" direction shown in the layout plan view shown at the top. It is shown continuously and must be understood with some imagination. In addition, although the incision was made along the "A" direction and the "B" direction, it is shown that it is shown in order to show the component implemented in the position separated from the "A" segment or the "B" segment if necessary. I hope.

A dopant is implanted on the transparent substrate 1 to deposit doped polysilicon having high electrical conductivity, and then patterned to form a storage capacitor lower electrode 10 (FIG. 5). The dielectric material 14 is deposited on the storage capacitor lower electrode 10 by thermal oxidation or low pressure chemical vapor deposition (LPCVD), and then doped polysilicon and tungsten silicide thereon. (WSix) is continuously deposited and patterned to pattern the lower BM 15 with a double film. At this time, the lower BM 15 is formed as an opaque thin film to be used as a capacitor upper electrode. The reason why the lower BM 15 is formed as a double layer is that the stress can be alleviated in order to suppress crack generation due to internal stress of the tungsten silicide thin film, and the interface characteristics of SiO ₂ and silicide (Six) This is because the breakdown voltage of the storage capacitor insulating film can be increased. The lower BM 15 may be formed by a single layer film such as titanium silicide (TiSix) or tungsten silicide (WSix). You may also In addition, the lower BM may be first patterned with an opaque conductive thin film on the transparent substrate, a dielectric layer such as a silicon oxide film is deposited on the upper layer, and then a conductive thin film is formed and patterned on the upper portion of the storage capacitor upper electrode. In this case, the lower BM simultaneously functions as the storage capacitor lower electrode. As shown in the layout diagram shown in the upper part of FIG. 6, the lower BM 15 is patterned while leaving a contact area for connecting to the lower electrode 10 of the storage capacitor. After forming the storage capacitor, the first-first insulating layer 16 is deposited (FIG. 6). The first insulating layer 16 is deposited to a thickness of approximately 3000 m 3 or more.

Next, after the lower horizontal blocking wall 30 is patterned using a material that blocks light, the first and second insulating layers 17 are deposited and planarized (FIG. 7). The material forming the lower horizontal blocking wall 30 may be any material that blocks light, and it is preferable to use the same material as the material forming the lower BM. The first and second insulating layers 17 are deposited to a thickness of approximately 3000 GPa or more.

Next, the semiconductor active layer 20 is patterned in a substantially "b" shape on the first and second insulating layers 17, and then the gate insulating film 21 is deposited (FIG. 8). Thereafter, a plurality of contact holes penetrating through the gate insulating film 21, the first-first insulating layer 16, and the first-second insulating layer 17 are formed, and the contact hole 25 for the storage upper electrode 25 and the storage are formed. The lower electrode contact hole 26 is formed. In this case, the first barrier wall contact hole 31 and the second barrier wall contact hole 32 for blocking the incident light incident to the semiconductor active layer 20 by using the same mask are disposed on the lower horizontal barrier wall 30. Each is formed to be in contact (Fig. 9). A first barrier wall contact hole 31 and a second barrier wall contact hole 32 may be formed by using a mask separate from a mask forming the contact hole 25 for the upper storage electrode and the contact hole 26 for the lower storage electrode. Of course it can form.

Particularly important is that the first and second barrier wall contact holes 31 and 32 are formed so that the opening ratio is not reduced when the first and second barrier wall contact holes 31 and 32 are filled with an impermeable metal in the next process formed. The upper BM 70 should not be left outside the area where it is formed. In FIG. 9, for convenience, the region of the upper BM 70 to be formed in the future is illustrated by a thick one-dot chain line. As shown in FIG. 9, it can be seen that the light blocking wall contact holes 31 and 32 are formed on the region where the upper BM 70 is formed, and preferably, on the region where the lower BM 15 is formed. It is good to be. The optimal position for forming the vertical barrier wall is the position that is closest to the active channel in the longitudinal direction of the active channel (the vertical direction of "L") among the regions that do not affect the opening ratio within the range to prevent the short between the upper and lower layers. It is preferable to form.

9 is shown as if the first and second barrier wall contact holes 31 and 32 penetrate through the semiconductor active layer 20 in contact with each other, but is shown in the top view shown in the upper part of FIG. As can be seen, the first and second barrier wall contact holes 31 and 32 are not in contact with the semiconductor active layer 20 at all. In order to illustrate this more clearly, a cross-sectional view of the C-C 'direction of FIG. 9 is illustrated in FIG. 20. As shown in the plan view of FIG. 9 and FIG. 20, the first and second barrier wall contact holes 31 and 32 are formed at adjacent positions along the longitudinal direction of the channel region 19 of the semiconductor active layer 20. have. In addition, it can be seen that the first and second barrier wall contact holes 31 and 32 are formed to surround the active layer on the upper region where the lower horizontal barrier wall 30 is formed to be in contact with the lower horizontal barrier wall 30.

Next, the gate electrode has a thickness of approximately 3000 Å while filling the contact hole 25 for the storage upper electrode, the contact hole 26 for the storage lower electrode, the first barrier wall contact hole 31, and the second barrier wall contact hole 32. After applying polysilicon, the gate electrode 35, the contact electrode 36 for the storage capacitor upper electrode, and the contact electrode 37 for the storage capacitor lower electrode are pattern-formed (FIG. 10). The gate electrode 35 should be conductive and have good interfacial properties with SiO ₂ , which is a lower gate insulating film, and should have low light transmittance in order to suppress leakage current caused by light. It must also be able to withstand about 800 degrees of post-process temperature for dopant activation. Because of these requirements, doped polysilicon is mainly used as the material for forming the gate electrode 35, and it is preferable to use a double layer of doped polysilicon and tungsten silicide (WSix) to increase electrical conductivity and lower light transmittance. When the gate electrode polysilicon is deposited by chemical vapor deposition (CVD), the first barrier wall contact hole 31 and the second barrier wall contact hole 32 are respectively filled with the same material as the gate electrode. The first blocking wall 41 and the second blocking wall 42 are formed.

An appropriate pattern is formed on a mask used to form the gate electrode 35 to etch the gate electrode forming material stacked on the first blocking wall 41 and the second blocking wall 42 to form a contact layer on the blocking layer. When forming a pattern to form a more perfect blocking wall or a mask used for etching the gate electrode without forming a pattern for the first blocking wall 41 and the second blocking wall 42, the gate electrode is used as it is. The first blocking wall 41 and the second blocking wall 42 may be formed by a stringer remaining during etching.

A process of filling the gate electrode polysilicon into the first barrier wall contact hole 31 and the second barrier wall contact hole 32 will be described in more detail with reference to FIG. 17. As shown in FIG. 17, when the contact hole has a width of 'a' and a depth of 'b', when the gate electrode polysilicon having a thickness of 't' is coated, as shown in FIG. Contact holes are filled together. In the present invention, 'a' and 'b' were 6000 mm 3, and the thickness 't' was 3000 mm 3. After etching the remaining portion using a mask that leaves the gate electrode, the gate electrode polysilicon filled in the contact hole after etching as shown in FIG. 17 (b) remains, which is called a stringer. do.

As described above, the gate electrode polysilicon deposited on the first barrier wall contact hole 31 and the second barrier wall contact hole 32 is removed using a separate mask in addition to the method of forming the stringer remaining when the gate electrode pattern is formed. Of course you can. In some cases, as shown in FIG. 18, the gate electrode polysilicon deposited on the first barrier wall contact hole 31 and the second barrier wall contact hole 32 may be left to have a pattern on the top thereof so as to overlap the vertical grooves. It may be. FIG. 19 is a cross-sectional view of a lower substrate of a liquid crystal display in which some of the gate electrode polysilicon deposited on the first barrier wall contact hole 31 and the second barrier wall contact hole 32 remains. Preferably, the gate electrode 35 pattern may overlap the first blocking wall contact hole 31 and the second blocking wall contact hole 32.

The second insulating layer may be formed on the gate insulating layer 21, the contact electrode 36 for the storage capacitor upper electrode, the contact electrode 37 for the storage capacitor lower electrode, the first blocking wall 41 and the second blocking wall 42. 49). A source electrode contact hole 46 ', a drain electrode contact hole 47', a storage capacitor lower electrode 37 and a first connection electrode contact hole 48 'connecting the drain electrode 47 and a storage capacitor Second contact electrodes 45 'for connecting the upper electrode 36 and the common electrode are respectively formed (FIG. 11).

Next, a metal film for forming the data line 53 is deposited using PVD (Physical Vapor Deposition) and then patterned. Since the data line 53 has a high electrical conductivity, metal is used, and aluminum (Al) is usually used. Titanium (Ti), titanium nitride (TiN), etc. are made of two layers (Al / TiN) or three or four layers (TiN / Al / TiN) to reduce reflectivity on the upper and lower parts of aluminum and reduce contact resistance with the lower semiconductor film. , Ti / TiN / Al / TiN). As a result, the first connection electrode 48 connecting the source electrode 46, the drain electrode 47, the storage capacitor lower electrode 37, and the drain electrode 47, and the storage capacitor upper electrode 36 and the common electrode are connected to each other. The second connection electrode 45 is completed.

Afterwards, a third insulating layer covering the second insulating layer 49, the source electrode 46, the drain electrode 47, the storage capacitor lower electrode 37, the first connection electrode 48, and the second connection electrode 45. Layer 54 is deposited (FIG. 12). As shown in the circle of FIG. 12, the first blocking wall 41 and the second blocking wall 42 are in contact with the lower horizontal blocking wall 30 along the length (“L”) direction of the channel of the active layer. It is preferably formed to be " L1 " longer than the length L of the channel in order to more reliably block light incident on the channel. As shown in the figure, when the channel is formed to have a length 'L' and a width 'W', the length and the width of the lower horizontal barrier wall 30 should be long and wide, respectively, L1 and W1.

After the third insulating layer 54 is planarized, a contact hole 66 'is formed for the third connection electrode for connecting the common electrode contact hole 65', the drain electrode 47 and the pixel electrode (Fig. 13). Next, a metal film for forming the upper BM is deposited and then patterned to form a common electrode 65 and a third connection electrode 66. The upper BM must be opaque and have a high electrical conductivity because a constant voltage is applied and it is also used as a secondary wiring. Since it is a post process, it does not need to withstand high temperatures, so aluminum (Al) is usually used, and titanium nitride (TiN) may be laminated on either top or bottom to reduce reflectivity. The fourth insulating layer 71 is deposited on the third insulating layer 54, the common electrode 65, and the third connection electrode 66 (FIG. 14). According to the layout of FIG. 14, it can be seen that the upper BM 70 is entirely deposited. However, only a part of the upper BM 70 is illustrated in the cross-sectional view for the sake of convenience of description. In the present invention, the thickness of the upper BM 70 is about 4000 kPa.

After the fourth insulating layer 71 is flattened, a contact hole 72 'for the pixel electrode is formed (FIG. 15). Next, the lower substrate process is completed by patterning the pixel electrode using a transparent electrode material, for example, indium tin oxide (ITO) (FIG. 16). When cut in the direction F-F 'of the layout diagram shown in the upper portion of Figure 16 is a cross-sectional view shown in FIGS.

21 to 32 are process diagrams illustrating a manufacturing process of a lower substrate of the liquid crystal display according to the present invention shown in FIG. In FIGS. 21 to 32, two views consisting of a top view and a bottom view are shown simultaneously, the top view showing a layout plan view of the bottom substrate, the bottom view showing a cross-sectional view of the bottom substrate, and the scheme described above. Same as bar.

A dopant is implanted on the transparent substrate 1 to deposit doped polysilicon having increased electrical conductivity, and then patterned to form a storage capacitor lower electrode 10 (FIG. 21). The dielectric material 14 is deposited on the storage capacitor lower electrode 10 by thermal oxidation or low pressure chemical vapor deposition (LPCVD), and then doped polysilicon and tungsten silicide thereon. (WSix) is continuously deposited and patterned to pattern the lower BM 15 with a double film. At this time, the lower BM 15 is formed as an opaque thin film to be used as a capacitor upper electrode. The reason why the lower BM 15 is formed as a double layer is that the stress can be alleviated in order to suppress crack generation due to internal stress of the tungsten silicide thin film, and the interface characteristics of SiO ₂ and silicide (Six) This is because the breakdown voltage of the storage capacitor insulating film can be increased. The lower BM 15 may be formed by a single layer film such as titanium silicide (TiSix) or tungsten silicide (WSix). You may also In addition, the lower BM may be first patterned with an opaque conductive thin film on the transparent substrate, a dielectric layer such as a silicon oxide film is deposited on the upper layer, and then a conductive thin film is formed and patterned on the upper portion of the storage capacitor upper electrode. In this case, the lower BM simultaneously functions as the storage capacitor lower electrode. As shown in the layout shown in the upper part of FIG. 22, the lower BM 15 is patterned while leaving a contact area for connecting to the lower electrode 10 of the storage capacitor. After forming the storage capacitor, the first insulating layer 18 is deposited (FIG. 22). The first insulating layer 18 is deposited to a thickness of approximately 3000 kPa or more.

Next, the gate line 35 is patterned, and the gate insulating film 91 is formed and planarized on the gate line 35 and the first insulating layer 18 (FIG. 23). The gate line 35 should be conductive and have good interfacial properties with SiO ₂ , which is an upper gate insulating film, and should have low light transmittance in order to suppress leakage current caused by light. As the gate line 35 forming material, doped polysilicon is mainly used, and a double layer of doped polysilicon and tungsten silicide (WSix) is preferably used to increase electrical conductivity and lower light transmittance.

A silicon thin film is coated and patterned on the upper region of the gate insulating film 91 to form the active layer 20 (FIG. 24). After the tenth insulating layer 89 is formed thereon, the upper storage contact hole 25 and the lower storage electrode penetrate the first insulating layer 18, the gate insulating layer 91, and the tenth insulating layer 89. The third blocking wall contact is formed in each of the electrode contact holes 26 and penetrates the gate insulating layer 91 and the tenth insulating layer 89 to contact the gate electrode 35 using the same mask or a separate mask. A hole 92 'and a fourth blocking wall contact hole 93' are respectively formed (FIG. 25). In the cross-sectional view shown in the lower part of FIG. 25, the third barrier wall contact hole 92 ′ and the fourth barrier wall contact hole 93 ′ are formed as though penetrating the active layer 20. Please think of it as a problem caused by the representation using the drawings. Referring to the plan view of the upper portion of FIG. 25, the third barrier wall contact hole 92 ′ and the fourth barrier wall contact hole 93 ′ are disposed along the gate line 35 in the longitudinal direction of the active layer, with the active layer interposed therebetween. It can be seen that is formed in the longitudinal direction ("L" direction). In order to illustrate this more precisely, a part of the cutaway view taken along the line D-D 'of the plan view of FIG. 25 is illustrated in FIG. 33.

Filling and patterning the upper storage contact hole 25, the lower storage contact hole 26, the third blocking wall contact hole 92 ′ and the fourth blocking wall contact hole 93 ′ with an impermeable metal. (Figure 26). In this case, the upper electrode contact hole 25 and the storage lower electrode contact hole 26 are filled with a conductive metal, and the third blocking wall contact hole 92 ′ and the fourth blocking wall contact hole 93 ′ are formed of light ( It is desirable to form a non-conductive or conductive material that blocks light. An impermeable metal filled in the contact hole 25 for the storage upper electrode, the contact hole 26 for the storage lower electrode, the third barrier wall contact hole 92 'and the fourth barrier wall contact hole 93' It is preferable to use the same material as the material forming the BM. In this case, as shown in the plan view of FIG. 26, the upper horizontal blocking wall 94 connecting the third blocking wall contact hole 92 ′ and the fourth blocking wall contact hole 93 ′ is formed with an impermeable material to form an upper portion. It is possible to reduce light incident from the substrate into the channel region. By filling the impermeable metal described above, the storage capacitor upper contact electrode 36, the storage capacitor lower contact electrode 37, the third blocking wall 92, the fourth blocking wall 93, and the upper horizontal blocking wall 94. Are formed respectively.

Next, after the eleventh insulating layer 95 is deposited on the upper portion, the second connection electrode contact hole 45 'for connecting the storage capacitor upper contact electrode 36 through a predetermined region of the eleventh insulating layer 95 is formed. ), The first connection electrode contact hole 48 'for connecting to the storage capacitor lower contact electrode 37 and the source electrode contact hole 46' and the drain connected to the source and drain regions of the active layer 20, respectively. Electrode contact holes 47 'are formed respectively (FIG. 27).

Next, a metal film for forming the data line 53 is deposited using PVD (Physical Vapor Deposition) and then patterned. Since the data line 53 needs to have high electrical conductivity, metal is used, and aluminum (Al) is usually used. Titanium (Ti), titanium nitride (TiN), etc. are made of two layers (Al / TiN) or three or four layers (TiN / Al / TiN) to reduce reflectivity on the upper and lower parts of aluminum and reduce contact resistance with the lower semiconductor film. , Ti / TiN / Al / TiN). As a result, the first connection electrode 48 connecting the source electrode 46, the drain electrode 47, the storage capacitor lower electrode 37, and the drain electrode 47, and the storage capacitor upper electrode 36 and the common electrode are connected to each other. The second connection electrode 45 is completed. Thereafter, a third insulating layer covering the eleventh insulating layer 95, the source electrode 46, the drain electrode 47, the storage capacitor lower electrode 37, the first connection electrode 48, and the second connection electrode 45. Layer 54 is deposited (FIG. 28).

After the third insulating layer 54 is planarized, a contact hole 66 'is formed for the third connection electrode for connecting the common electrode contact hole 65', the drain electrode 47 and the pixel electrode (Fig. 29).

Next, a metal film for forming the upper BM is deposited and then patterned to form a common electrode 65 and a third connection electrode 66. The upper BM must be opaque and have high electrical conductivity because a constant voltage is applied and it is also used as a secondary wiring. Since it does not need to withstand high temperatures because it belongs to a later process, aluminum (Al) is usually used, and titanium nitride (TiN) may be laminated on either top or bottom to reduce reflectivity. The fourth insulating layer 71 is deposited on the third insulating layer 54, the common electrode 65, and the third connection electrode 66 (FIG. 30). According to the layout diagram of FIG. 30, it can be seen that the upper BM 70 is entirely deposited. However, only a part of the upper BM 70 is illustrated in the cross-sectional view for the sake of convenience of description. In the present invention, the thickness of the upper BM 70 is about 4000 kPa.

After the fourth insulating layer 71 is planarized, a contact hole for the pixel electrode 72 is formed (FIG. 31). Next, the lower substrate process is completed by patterning the pixel electrode using a transparent electrode material, for example, indium tin oxide (ITO) (FIG. 32). When cut in the direction F-F 'of the layout diagram shown in the upper portion of Figure 32 is a cutaway view shown in FIG.

34 to 37 are part of a process diagram of an embodiment according to the present invention in the case where the contact hole for the storage upper electrode and the contact hole for the storage lower electrode are formed on the first insulating layer and before the gate line is applied. .

FIG. 34 is a process of the next step of FIG. 22, wherein the upper and lower contact holes for the storage upper electrode 15 and the lower storage electrode 10 which are connected to the capacitor upper electrode 15 and the capacitor lower electrode 10, respectively, are formed in the first insulating layer 18. An electrode contact hole is formed, and polysilicon is filled, coated, and patterned to form a gate line 35, a storage capacitor upper contact electrode 36, and a storage capacitor lower contact electrode 37 (FIG. 34). As the material for forming the gate electrode 35, doped polysilicon is mainly used, and a double layer of doped polysilicon and tungsten silicide (WSix) is preferably used to increase electrical conductivity and lower light transmittance. In this case, the material filled in the contact hole for the storage upper electrode and the contact hole for the storage lower electrode is made of the same material as the gate line 35 to form the storage capacitor upper contact electrode 36 and the storage capacitor lower contact electrode 37. And patterning using the same mask as that used for forming the gate line 35.

Next, after applying the gate insulating film 91, the active layer 20 is formed on the upper part (FIG. 35). After depositing the tenth insulating layer 89 again on the gate insulating layer 91 and the active layer 20, the third connection electrode contact hole 110 ′ and the storage capacitor for connecting to the storage capacitor upper contact electrode 36 are formed. A fourth connection electrode contact hole 111 ′, a first blocking wall contact hole 92 ′, and a second blocking wall contact hole 93 ′ are formed to connect the lower contact electrode 37 (FIG. 36).

After filling and patterning the third connecting electrode contact hole, the fourth connecting electrode contact hole, the third blocking wall contact hole, and the fourth blocking wall contact hole with an impermeable metal, the eleventh insulating layer 95 is deposited thereon. To form (FIG. 37). As the impermeable metal filled in the third connection electrode contact hole, the fourth connection electrode contact hole, the third blocking wall contact hole, and the fourth blocking wall contact hole, it is preferable to use the same material as the material forming the lower BM. . In this case, as shown in the plan view of FIG. 37, light incident on the channel region from the upper substrate is formed by patterning the upper horizontal blocking wall 94 connecting the third blocking wall contact hole and the fourth blocking wall contact hole with an impermeable material. Makes it possible to reduce light. The third connection electrode 110, the fourth connection electrode 111, the third blocking wall 92, the fourth blocking wall 93, and the upper horizontal blocking wall 94 are respectively filled with the impermeable metal. Is formed. Thereafter, the process may proceed similarly to those shown in FIGS. 27 to 32 to complete the manufacture of the lower substrate.

The third connection electrode contact hole for connecting the storage capacitor upper contact electrode 36 and the storage capacitor lower contact electrode 37 to the storage capacitor upper contact electrode 36 in FIG. 36 after forming the process shown in FIG. Instead of forming the fourth connection electrode contact hole 111 'for connecting to the 110' and the lower capacitor electrode contact electrode 37, the source electrode 46 'is deposited after the eleventh insulating layer 95 is deposited. In the forming of the contact hole and the contact hole for the drain electrode 47, a contact hole connecting the upper storage capacitor upper contact electrode 36 and the lower storage capacitor contact electrode 37 may be formed. In addition to the above method, the formation of the storage capacitor upper contact electrode 36 and the storage capacitor lower contact electrode 37 and the connection electrode connected thereto may be performed in various processes.

The lower substrate according to the present invention presented above is combined with the upper substrate generated through a separate process and can be used as a liquid crystal panel by injecting liquid crystal between the upper substrate and the lower substrate. The upper substrate may include an opposite electrode facing the pixel electrode of the lower substrate, and may include a separate focusing lens for improving luminance.

In addition, the completed liquid crystal panel is used as a liquid crystal projector by forming an image by combining at least one illumination, condenser lens, and dichroic lens, and projecting the formed image using a projection lens.

As described above, the present invention relates to a thin film transistor liquid crystal panel and a method of manufacturing the same. In the related art, when light enters an active channel of a thin film transistor, a leakage current is generated in the active channel, thereby maintaining the transfer to the pixel electrode. The voltage became unstable and there was a flicker of pixels. The present invention can effectively reduce the flicker of pixels by providing a barrier wall around the active channel that blocks light incident to the periphery of the active channel. In addition, by forming the barrier wall below the region where the upper BM is formed, or preferably above the region where the lower BM is formed, it was possible to eliminate the side effect that the aperture ratio is reduced despite the addition of the barrier wall.

While preferred embodiments of the present invention have been described using specific terms, such descriptions are for illustrative purposes only and it is understood that various changes and modifications may be made therein without departing from the spirit and scope of the following claims. You must lose.

Claims (14)

delete A lower BM, a thin film transistor used as a switching element, a gate line applying a voltage to the thin film transistor gate, a data line applying a data voltage to a drain of the thin film transistor, an upper BM and a pixel electrode driven by the thin film transistor. A liquid crystal display panel which transmits or blocks light by changing an arrangement of liquid crystal materials through a liquid crystal material between a lower substrate provided and an upper substrate having an opposite electrode facing the pixel electrode. The lower BM, the switching element, the data line, the upper BM, and the pixel electrode are stacked on the transparent substrate in order, between the lower BM and the switching element, between the switching element and the data line, and the data line. And a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, respectively, between the upper BM and the upper BM and the pixel electrode, and along the channel length direction of the switching element. A hole having a predetermined size formed from the upper side of the first insulating layer toward the lower substrate while being spaced a predetermined distance from the left and right sides, and having a first blocking wall and a second blocking wall filled with an impermeable material in the hole, A potential is applied to the lower BM, The first insulating layer may include a first insulating layer deposited on the lower BM and a first insulating layer deposited between the first insulating layer and the switching element. 1. The liquid crystal display panel of claim 1, further comprising a lower horizontal blocking wall formed over the insulating layer and formed of an impermeable material wider than the width of the channel along the length direction of the channel. The method of claim 2, The first blocking wall and the second blocking wall are formed of the same material as the material forming the gate line. The method of claim 2, And the first blocking wall and the second blocking wall are in contact with the lower horizontal blocking wall. The method of claim 2, And the first blocking wall and the second blocking wall are electrically connected to the gate line. delete delete delete delete delete Driven by a lower BM to which a potential is applied, a thin film transistor used as a switching element, a gate line applying a voltage to a gate of the thin film transistor, a data line applying a data voltage of the drain of the thin film transistor, an upper BM and the thin film transistor A method of manufacturing a liquid crystal display panel which transmits or blocks light by changing an arrangement of liquid crystal materials through a liquid crystal material between a lower substrate having a pixel electrode and an upper substrate having a counter electrode facing the pixel electrode. The manufacturing of the lower substrate may include Forming a lower BM by depositing and patterning an opaque film on the transparent substrate; Depositing a first insulating layer on the transparent substrate and the lower BM; A third step of forming a lower horizontal blocking wall by patterning an impermeable material on a predetermined region of the first-first insulating layer; Depositing a 1-2 insulating layer on the 1-1 insulating layer and the lower horizontal blocking wall; A fifth step of patterning an active layer of the thin film transistor on the second insulating layer; A sixth step of depositing a gate insulating film on the first and second insulating layers and the active layer of the thin film transistor; Forming first and second vertical grooves on both sides of the first and second insulating layers and the gate insulating layer at positions spaced apart from the active layer along a length direction of the active layer and contacting the lower horizontal blocking wall; Step 7-1 and step 7-2 of filling the first and second vertical grooves with an impermeable material; An eighth step of depositing a material forming a gate line on the gate insulating layer, and an eighth step of pattern forming the deposited gate line using a mask; A ninth step of depositing a second insulating layer on the gate line and the gate insulating film; Forming a contact hole crossing the second insulating layer vertically and contacting the source and the drain of the thin film transistor, respectively; An eleventh step of filling the contact hole with a metal to form a source electrode and a drain electrode of the thin film transistor; A twelfth step of depositing a third insulating layer on the second insulating layer, the source electrode and the drain electrode; Forming a contact hole connected to the drain electrode vertically across the third insulating layer and filling a metal into the contact hole to form a third connection electrode connected to the drain electrode; A fourteenth step of depositing a fourth insulating layer on the third insulating layer and the third connection electrode; And And forming a contact hole contacting the third connection electrode vertically across the fourth insulating layer, and forming a pixel electrode connected to the contact hole. . The method of claim 11, The method of manufacturing a liquid crystal display panel, wherein the steps 7-2 and 8-1 are performed in one process. Driven by a lower BM to which a potential is applied, a thin film transistor used as a switching element, a gate line applying a voltage to a gate of the thin film transistor, a data line applying a data voltage of the drain of the thin film transistor, an upper BM and the thin film transistor A method of manufacturing a liquid crystal display panel which transmits or blocks light by changing an arrangement of liquid crystal materials through a liquid crystal material between a lower substrate having a pixel electrode and an upper substrate having a counter electrode facing the pixel electrode. The manufacturing of the lower substrate may include Forming a lower BM by depositing and patterning an opaque film on the transparent substrate; Depositing a first insulating layer on the transparent substrate and the lower BM; A third step of forming a gate line on the first insulating layer; A fourth step of depositing a gate insulating film on the gate line; A fifth step of forming a silicon thin film on the gate insulating film; A sixth step of depositing a tenth insulating layer on the silicon thin film and the gate insulating film; Steps 7-1 and 3rd forming third and fourth vertical grooves formed on both sides of the tenth insulating layer and the gate insulating film at positions spaced apart from the silicon thin film by a predetermined distance along the longitudinal direction of the silicon thin film. And 7-2 filling the fourth vertical groove with the impermeable material. Step 8-1 of applying an impermeable material on the tenth insulating layer corresponding to an upper portion of the channel region which is a region where the silicon thin film crosses the gate line, and patterning the impermeable material to form an upper horizontal blocking wall. Step 8-2; A ninth step of depositing an eleventh insulating layer on the tenth insulating layer and the upper horizontal blocking wall; Forming a contact hole in the tenth insulating layer to contact the source and the drain of the thin film transistor, respectively; An eleventh step of filling the contact hole with a metal to form a source electrode and a drain electrode of the thin film transistor; A twelfth step of depositing a third insulating layer on the tenth insulating layer, the source electrode and the drain electrode; Forming a contact hole connected to the drain electrode vertically across the third insulating layer and filling a metal into the contact hole to form a third connection electrode connected to the drain electrode; A fourteenth step of depositing a fourth insulating layer on the third insulating layer and the third connection electrode; And And forming a contact hole contacting the third connection electrode vertically across the fourth insulating layer, and forming a pixel electrode connected to the contact hole. . The method of claim 13, 7. The method of claim 7, wherein the steps 7-2 and 8-1 are performed by one process.

Images