KR100694480B1 - Method for forming gate electrode in semiconductor device - Google Patents

Abstract

A method for forming a gate electrode in a semiconductor device is provided to avoid damage to a sidewall of a gate electrode and a substrate in an active region by previously removing a hard mask functioning as an ion implantation preventing layer in a deep N-ion implanting process for forming a photodiode before a gate electrode is formed in a pixel region and a logic region. A gate conductive layer is formed on a substrate(10) including a pixel region and a logic region. First and second hard masks are sequentially deposited on the gate conductive layer. The first and the second hard masks are etched to form first and second hard mask patterns(16,15) on the gate conductive layer in the pixel region and the logic region. An ARC(anti-reflective coating) is formed on the gate conductive layer in the pixel region and logic region. A photoresist layer pattern(18) having a structure of opening the logic region is formed on the gate conductive layer to cover the second hard mask pattern in the pixel region. The photoresist layer pattern and the ARC are used to etch the second hard mask pattern in the logic region. The photoresist layer pattern and the ARC are removed. The gate conductive layer is etched through the first hard mask pattern to form first and second gate electrodes in the pixel region and the logic region. The first hard mask is made of one of an oxide layer, a nitride layer or a composition thereof.

Description

METHODE FOR FORMING GATE ELECTRODE IN SEMICONDUCTOR DEVICE

1A to 1E are cross-sectional views illustrating a gate electrode forming method of a CMOS image sensor according to Embodiment 1 of the present invention;

2A to 2E are cross-sectional views illustrating a gate electrode forming method of a CMOS image sensor according to Embodiment 2 of the present invention;

<Description of the symbols for the main parts of the drawings>

10, 20: substrate

11, 21: gate insulating film

12, 22: polysilicon film

13: oxide film

14: nitride film

16, 23, 23a: first hard mask pattern

15, 24: second hard mask pattern

17 bottom antireflection film

18, 25: photosensitive film pattern

12a, 22a: first gate electrode

12b, 22b: second gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly to a method of forming a gate electrode constituting a transistor which is a component of a CMOS image sensor.

The image sensor is a semiconductor device that converts an optical image into an electrical signal, and the image sensor is mainly composed of a charge coupled device (hereinafter referred to as a CCD) and a CMOS (Complementary MOS) image sensor.

A CCD is a device in which charge carriers are stored and transported in a capacitor while individual metal-oxide-silicon (MOS) capacitors are in close proximity to each other.

On the other hand, the CMOS image sensor includes one photodiode and three or four transistors for driving a unit pixel in one unit pixel by applying a semiconductor CMOS process. Such a plurality of transistors constituting the CMOS image sensor are made up of a gate electrode and a source / drain like a transistor of a general memory device.

In general, the gate electrode forming method of such a CMOS image sensor is as follows.

First, a gate oxide film is formed on a substrate, and then a polysilicon film for a gate electrode is deposited on the gate oxide film. Then, a hard mask is deposited on the polysilicon film, and an anti reflective coating (ARC) is applied on the hard mask. In this case, the hard mask functions as an ion implantation prevention layer in a deep N ion implantation process for forming a photodiode forming a unit pixel.

Subsequently, a predetermined photoresist pattern is formed on the antireflection film through a photo process, and the antireflection film, the hard mask, and the polysilicon are sequentially etched using the photoresist pattern. As a result, a gate structure having a structure in which a gate oxide film, a polysilicon film, a hard mask, and an antireflection film is stacked is formed on the substrate.

Thereafter, the photoresist pattern and the anti-reflection film are removed through a strip process, and the hard mask is removed through a separate wet etching process. In this case, the hard mask may exist in the pixel region where the pixel of the image sensor is formed, but should not exist in the logic region where other logic elements are formed. This is because, in the case of a logic device, since the contact resistance of the gate electrode has a great influence on device characteristics, a silicide layer must be formed on the gate electrode in order to reduce the contact resistance of the gate electrode.

That is, in order to form the silicide layer on the gate electrode, the polysilicon film for the gate electrode containing silicon must be exposed. Therefore, the hard mask must be removed in the logic region.

Accordingly, when the hard mask is made of nitride-based material, the hard mask is removed using phosphoric acid (H ₃ PO ₄ ), and when the hard mask is made of oxide-based material, BOE (Buffered Oxide Etchant) is used. The hard mask was removed.

However, when the hard mask is removed using the phosphoric acid solution, sidewall damage of the polysilicon film and the substrate damage of the active area occur. When the hard mask is removed using the BOE solution, the process margin is insufficient. There is a problem that substrate damage occurs.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and can prevent sidewall damage of the gate electrode and damage to the active region of the substrate caused by removal of the hard mask when forming the gate electrode of the CMOS image sensor. It is an object of the present invention to provide a method for forming a gate electrode of a semiconductor device.

According to an aspect of the present invention, a gate conductive layer is formed on an entire surface of an upper surface of a substrate defined by a pixel region and a logic region, and functions as a hard mask when etching the gate conductive layer on the gate conductive layer. Sequentially depositing a first hard mask and a second hard mask functioning as an ion implantation prevention layer during an ion implantation process for forming a photodiode of the pixel region, etching the first and second hard masks to etch the pixel Forming first and second hard mask patterns on the gate conductive layer in the region and the logic region, respectively, and forming an anti-reflection film on the gate conductive layer in the pixel region and the logic region; Forming a photoresist pattern having a structure in which the logic region is opened on the gate conductive layer to cover the second hard mask pattern of the pixel region; Etching the second hard mask pattern of the logic region by using the photoresist pattern and the anti-reflection film; Removing the photoresist pattern and the anti-reflection film; And etching the gate conductive layer through the first hard mask pattern to form first and second gate electrodes in the pixel region and the logic region, respectively.

In the present invention, the first hard mask may be formed in any one of an oxide film, a nitride film, and a laminated film thereof, but the total thickness of the first hard mask is 600 kPa.

In the present invention, the second hard mask is formed of an oxide film, but preferably formed to a thickness of 1500 to 2500 kPa.

In the present invention, the first and second hard masks may be etched using a mixed gas of CF ₄ and CHF ₃ , and the second hard mask pattern may be removed using a BOE solution.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example 1

1A to 1E are cross-sectional views illustrating a method of forming a gate electrode of a CMOS image sensor according to example 1 of the present invention. Hereinafter, 'Pixel' is a pixel region where a pixel of an image sensor is to be formed, and 'Logic' is a logic region where other logic elements are to be formed.

First, as illustrated in FIG. 1A, an oxidation process is performed to form a gate insulating layer 11 on a substrate 10 defined as a pixel region and a logic region Logic. For example, the gate insulating film 11 is formed to a thickness of 10 ~ 30 kHz. Preferably, it is formed in the thickness of 22 microseconds.

Here, the oxidation process may be performed by a wet oxidation method in which the silicon substrate 10 is heated at a temperature of approximately 900 to 1000 ° C. in an oxidizing gas such as water vapor, or heated at a temperature of about 1200 ° C. using pure oxygen as an oxidizing gas. It is carried out by dry oxidation method.

Next, a polysilicon film 12 is deposited on the gate insulating film 11 as a gate conductive film. For example, the polysilicon film 12 is deposited to a thickness of 1500 to 2500 mW. Preferably, it is deposited to a thickness of 2000 kPa.

Here, the polysilicon film 12 is formed of a doped or undoped silicon film. For example, in the case of an undoped silicon film, it is deposited by a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ . On the other hand, in the case of the doped silicon film is deposited by LPCVD method using a gas mixed with PH ₃ , PCl ₅ , BCl ₃ or B ₂ H ₆ in SiH ₄ .

Subsequently, the oxide film 13 and the nitride film 14 are sequentially deposited on the polysilicon film 12 using a first hard mask functioning as a hard mask during the etching process of the polysilicon film 12. Here, the first hard mask is deposited so that the total thickness of the oxide film 13 and the nitride film 14 is 600 kPa. Preferably, the oxide film 13 is deposited to a thickness of 300 GPa and then the nitride film 14 is deposited to a thickness of 300 GPa.

Subsequently, a second hard mask (not shown) that functions as an ion implantation prevention layer is deposited during an ion implantation process for forming a photo diode in the pixel region Pixel. Here, the second hard mask is formed of an oxide film, which is deposited to a thickness of 1500 to 2500 mW. Preferably, it is deposited to a thickness of 2000 kPa.

In particular, the second hard mask is formed for use as an ion implantation prevention layer on the gate electrode of the transistor that is aligned on one side of the photodiode in the pixel region Pixel. This is because when the gate electrode and the photoresist pattern of the transistor that are aligned on one side of the photodiode are mis-aligned when forming the photoresist pattern for forming the photodiode, the photoresist pattern alone may completely block the implantation of ions. Because there is not.

Subsequently, a mask process and an etching process are performed to sequentially etch the first and second hard masks such as the oxide film (not shown), the nitride film 14, and the oxide film 13. As a result, the first hard mask pattern 16 and the second hard mask pattern 15 are formed on the gate conductive layer 22 of the pixel region Pixel and the logic region Logic, respectively.

In the etching process for etching the first and second hard masks, a mixed gas of CF ₄ and CHF ₃ is used in the oxide film etching chamber.

Subsequently, as shown in FIG. 1B, a bottom anti-reflective coating (BARC) 17 is coated on the gate conductive layer 12 of the pixel region and the logic region Logic. For example, the bottom anti-reflection film 17 may be formed higher than the first hard mask pattern 16 to protect the first hard mask pattern 16 during the subsequent etching process. Preferably, it is applied in a thickness of 1000 kPa.

Subsequently, the photoresist pattern 18 having the structure of opening the logic region Logic to cover the second hard mask pattern 15 of the pixel region on the bottom anti-reflection film 17 by performing a photo process is performed. To form. As a result, the second hard mask pattern 15 of the pixel area is protected during the subsequent etching process.

Subsequently, as illustrated in FIG. 1C, an etching process using the photoresist pattern 18 as an etching mask is performed to remove the second hard mask pattern 15 exposed in the logic region Logic. In this etching process, BOE solution is used. In this case, the second hard mask pattern 15 of the pixel region Pixel is not etched by the photoresist pattern 18, and the oxide layer 13 forming the first hard mask pattern 16 of the logic region Logic is bottomed. It is not etched by the antireflection film 17.

Subsequently, as shown in FIG. 1D, a strip process is performed to remove the photoresist pattern 18 (see FIG. 1C). As a result, both the first hard mask pattern 16 and the second hard mask pattern 15 serving as the ion implantation prevention layer exist in the pixel region Pixel, and the first hard mask pattern 16 in the logic region Logic. Only remains.

Subsequently, as illustrated in FIG. 1E, an etching process using the first hard mask pattern 16 as a mask is performed to etch the polysilicon film 12 (see FIG. 1D). As a result, the first gate electrode 12a serving as the pixel gate electrode and the second gate electrode 12b serving as the logic gate electrode are formed on the gate insulating layer 11 of the pixel region Pixel and the logic region Logic, respectively.

When etching the polysilicon layer 12, the second hard mask pattern 15 of the pixel region Pixel and the first hard mask pattern 16 of the logic region Logic are etched to a predetermined thickness. Accordingly, only the oxide layer 13 remains on the second gate electrode 12b in the logic region Logic. At this time, the oxide layer 13 remaining in the logic region Logic is removed by a subsequent wet etching process.

Subsequently, a deep N ion implantation process is performed to form a photodiode in the substrate 10 of the pixel region by using the second hard mask pattern 15 as an ion implantation prevention film according to a known technique. A silicide layer is formed on the second gate electrode 12b of the logic.

In the deep N ion implantation process, a photoresist pattern having a structure of opening only a region in which a photodiode is to be formed through a separate photo process as well as the second hard mask pattern 15 is used as an ion implantation prevention layer.

As described above, in order to form a gate electrode and a hard mask in the pixel region and the logic region, a deep N ion implantation process is performed to form a photodiode, and a gate is formed to form a silicide layer on the gate electrode of the logic region. Removal of the hard mask on top of the electrode caused problems of sidewall damage of the gate electrode and / or substrate damage of the active region.

Accordingly, in the exemplary embodiment of the present invention, before forming the gate electrodes in the pixel region and the logic region, the sidewalls of the gate electrode are damaged by removing the hard mask which functions as an ion implantation prevention layer in the deep N ion implantation process for forming the photodiode. And occurrence of damage to the substrate in the active region can be suppressed.

Example 2

2A to 2E are cross-sectional views illustrating a method of forming a gate electrode of a CMOS image sensor according to a second exemplary embodiment of the present invention. Hereinafter, 'Pixel' is a pixel region where a pixel of an image sensor is to be formed, and 'Logic' is a logic region where other logic elements are to be formed.

First, as shown in FIG. 2A, an oxidation process is performed to form a gate insulating layer 21 on a substrate 20 defined as a pixel region and a logic region Logic. For example, the gate insulating film 21 is formed to a thickness of 10 ~ 30 kHz. Preferably, it is formed in the thickness of 22 microseconds. Here, the oxidation process uses the same method as in Example 1 of the present invention.

Subsequently, a polysilicon film 22 is deposited on the gate insulating film 21 as a gate conductive film. For example, the polysilicon film 22 is deposited to a thickness of 1500 to 2500 mW. Preferably, it is deposited to a thickness of 2000 kPa.

Here, the polysilicon film 22 is formed of a doped or undoped silicon film.

Subsequently, a nitride film (not shown) is deposited on the polysilicon film 22 using a first hard mask that functions as a hard mask during the etching process of the polysilicon film 22. Preferably, the nitride film is deposited to a thickness of 600 kPa.

Subsequently, an oxide film (not shown) is deposited using a second hard mask that functions as an ion implantation prevention film in an ion implantation process for forming a photodiode in the pixel region Pixel. For example, an oxide film is deposited to a thickness of 1500 to 2500 kPa. Preferably, it is deposited to a thickness of 2000 kPa.

In particular, the second hard mask is formed for use as an ion implantation prevention layer on the gate electrode of the transistor that is aligned on one side of the photodiode in the pixel region Pixel. This is because when the gate electrode and the photoresist pattern of the transistor that are aligned on one side of the photodiode are mis-aligned when forming the photoresist pattern for forming the photodiode, the photoresist pattern alone may completely block the implantation of ions. Because there is not.

Subsequently, a mask process and an etching process are performed to sequentially etch the first and second hard masks such as the nitride film and the oxide film. As a result, the first hard mask pattern 23 and the second hard mask pattern 24 are formed on the gate conductive layer 22 of the pixel region Pixel and the logic region Logic, respectively.

In the etching process for etching the first and second hard masks, a mixed gas of CF ₄ and CHF ₃ is used in the oxide film etching chamber.

Subsequently, as illustrated in FIG. 2B, a photo process is performed to open the logic region Logic on the gate conductive layer 22 to cover the second hard mask pattern 24 of the pixel region Pixel. The photosensitive film pattern 25 is formed. As a result, the second hard mask pattern 24 of the pixel area is protected during the subsequent etching process.

Subsequently, as illustrated in FIG. 2C, an etching process using the photoresist pattern 25 as an etching mask is performed to remove the second hard mask pattern 24 exposed in the logic region Logic. In this etching process, BOE solution is used. In this case, the second hard mask pattern 24 of the pixel region Pixel is not etched by the photoresist pattern 25, and the first hard mask pattern 23 of the logic region Logic is formed of a nitride film by a BOE solution. It is not etched.

Subsequently, as illustrated in FIG. 2D, a strip process is performed to remove the photoresist pattern 25 (see FIG. 2C). As a result, both the first hard mask pattern 23 and the second hard mask pattern 24 serving as the ion implantation prevention layer exist in the pixel region Pixel, and the first hard mask pattern 23 in the logic region Logic. Only remains.

Subsequently, as illustrated in FIG. 2E, an etching process using the first hard mask pattern 23 as a mask is performed to etch the polysilicon film 22 (see FIG. 2D). As a result, the first gate electrode 22a serving as the pixel gate electrode and the second gate electrode 22b serving as the logic gate electrode are formed on the gate insulating layer 21 of the pixel region Pixel and the logic region Logic, respectively.

When the polysilicon layer 22 is etched, the second hard mask pattern 24 of the pixel region Pixel and the first hard mask pattern 23 of the logic region Logic are etched by a predetermined thickness. Accordingly, a first thickness of the first hard mask pattern 23a remains on the second gate electrode 22b of the logic region Logic. At this time, the first hard mask pattern 23a remaining in the logic region Logic is removed by a subsequent wet etching process.

Subsequently, a deep N ion implantation process is performed to form a photodiode in the substrate 20 of the pixel region by using the second hard mask pattern 24 as an ion implantation prevention film according to a known technique. A silicide layer is formed on the second gate electrode 22b of the logic.

In the deep N ion implantation process, a photoresist pattern having a structure of opening only a region in which a photodiode is to be opened through a separate photo process as well as the second hard mask pattern 24 is used as an ion implantation prevention layer.

Accordingly, in Embodiment 2 of the present invention, before the gate electrodes are formed in the pixel region and the logic region, the hard mask which functions as an ion implantation prevention film in the deep N ion implantation process for photodiode formation is removed in advance. It is possible to suppress occurrence of sidewall damage and substrate damage in the active region.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, before the gate electrode is formed in the pixel region and the logic region, the hard mask which functions as an ion implantation prevention film in the deep N ion implantation process for forming the photodiode is removed in advance to form the gate electrode. It is possible to suppress occurrence of sidewall damage and substrate damage in the active region.

Claims (13)

Forming a gate conductive layer on the entire upper surface of the substrate including the pixel region and the logic region; Sequentially depositing a first hard mask functioning as a hard mask during etching of the gate conductive film and a second hard mask functioning as an ion implantation prevention film in an ion implantation process for forming a photodiode in the pixel region on the gate conductive layer; step; Etching the first and second hard masks to form first and second hard mask patterns on the gate conductive layers of the pixel region and the logic region, respectively; Forming an anti-reflection film on the gate conductive layer in the pixel region and the logic region; Forming a photoresist pattern having a structure in which the logic region is opened on the gate conductive layer to cover the second hard mask pattern of the pixel region; Etching the second hard mask pattern of the logic region by using the photoresist pattern and the anti-reflection film; Removing the photoresist pattern and the anti-reflection film; And Etching the gate conductive layer through the first hard mask pattern to form first and second gate electrodes in the pixel region and the logic region, respectively Gate electrode forming method of a semiconductor device comprising a. The method of claim 1, The first hard mask is formed of any one of an oxide film, a nitride film and a stacked film thereof. The method of claim 2, And the first hard mask is formed to have a total thickness of 600 GPa. The method of claim 1, And the second hard mask is formed of an oxide film. The method of claim 4, wherein The oxide film is a gate electrode forming method of a semiconductor device to form a thickness of 1500 ~ 2500Å. The method according to any one of claims 1 to 5, The etching of the first and second hard masks may include forming a gate electrode of a semiconductor device using a mixed gas of CF ₄ and CHF ₃ . delete The method of claim 1, The etching of the second hard mask may include forming a gate electrode of a semiconductor device using a BOE solution. delete The method of claim 1, The method of forming a gate electrode of a semiconductor device, wherein the anti-reflection film is formed higher than the first hard mask. The method of claim 10, The anti-reflection film is removed after removing the photoresist pattern. The method according to any one of claims 1 to 5, And the gate conductive film is formed of a polysilicon film. The method of claim 12, The polysilicon film is a gate electrode forming method of a semiconductor device to form a thickness of 1500 ~ 2500Å.

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