KR100691129B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100691129B1 KR100691129B1 KR1020050070802A KR20050070802A KR100691129B1 KR 100691129 B1 KR100691129 B1 KR 100691129B1 KR 1020050070802 A KR1020050070802 A KR 1020050070802A KR 20050070802 A KR20050070802 A KR 20050070802A KR 100691129 B1 KR100691129 B1 KR 100691129B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 3
- 229910000070 arsenic hydride Inorganic materials 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 229910003822 SiHCl3 Inorganic materials 0.000 claims 1
- 239000002019 doping agent Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000137 annealing Methods 0.000 description 2
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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Abstract
반도체 기판 위에 게이트 배선, 게이트 전극 및 게이트 상부 산화막을 형성하는 단계, 게이트 전극 측벽에 실리콘 산화막을 형성하는 단계, 반도체 기판의 노출된 영역에 에피층을 형성하는 단계, 에피층이 포함하고 있는 불순물 이온을 확산시켜 소스 및 드레인 접합 영역을 형성하는 단계를 포함하는 반도체 소자의 제조 방법. Forming a gate wiring, a gate electrode and an upper oxide film on the semiconductor substrate, forming a silicon oxide film on the sidewall of the gate electrode, forming an epitaxial layer in an exposed region of the semiconductor substrate, and impurity ions included in the epitaxial layer Diffusing to form source and drain junction regions.
트랜지스터, 소스 및 드레인 접합 영역, EPI Transistor, Source and Drain Junction Region, EPI
Description
도 1 내지 도 2는 본 발명의 한 실시예에 따른 반도체 소자의 제조 공정을 단계별로 도시한 단면도이다.1 to 2 are cross-sectional views showing step-by-step manufacturing processes of a semiconductor device according to an embodiment of the present invention.
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 소스 및 드레인 접합 영역을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming source and drain junction regions of a semiconductor device.
일반적으로 반도체 소자는 LOCOS(local oxidation of silicon) 또는 STI(swallow trench isolation) 소자 분리 방법에 의해 소자 영역에 게이트, 소스 및 드레인을 구비하는 트랜지스터를 구비하고 구비하고 있다.In general, a semiconductor device includes and includes a transistor having a gate, a source, and a drain in an element region by a local oxidation of silicon (LOCOS) or shallow trench isolation (STI) device isolation method.
이와 같은 반도체 소자의 트랜지스터를 제조하는 방법에 관해 설명한다.A method of manufacturing a transistor of such a semiconductor element will be described.
우선, STI(shallow trench isolation)가 형성되어 있는 반도체 기판 위에 게이트 절연막을 형성하고, 그 위에 폴리(poly) 실리콘 층을 증착한다. 여기서, STI는 반도체 기판에 형성된 소자를 전기적으로 격리 시킴으로써 소자간의 오동작을 방지한다.First, a gate insulating film is formed on a semiconductor substrate on which shallow trench isolation (STI) is formed, and a polysilicon layer is deposited thereon. Here, the STI prevents malfunction between the devices by electrically isolating the devices formed on the semiconductor substrate.
이어, 게이트 절연막 및 폴리 실리콘층은 사진 식각하여, 게이트 전극을 형 성한다. 이때, 게이트 전극은 STI가 형성되어 있지 않은 반도체 기판 위에 형성된다.The gate insulating film and the polysilicon layer are then etched to form a gate electrode. At this time, the gate electrode is formed on the semiconductor substrate on which the STI is not formed.
그 다음, 게이트 전극을 마스크로 삼아 반도체 기판 위에 이온 주입 장치를사용하여 불순물 이온을 고농도로 주입하고, 어닐링(annealing) 공정을 하여 게이트 전극의 양측으로 노출되는 반도체 기판의 활성 영역에 소스 및 드레인 접합영역을 형성한다.Then, using the ion implantation device on the semiconductor substrate using the gate electrode as a mask, a high concentration of impurity ions are implanted, and annealing is performed to source and drain junctions to active regions of the semiconductor substrate exposed to both sides of the gate electrode. Form an area.
이와 같이, 종래의 소스 및 드레인 접합 영역은 이온 주입 장치와 별도의 어닐링 공정을 통해 형성된다.As such, the conventional source and drain junction regions are formed through an annealing process separate from the ion implantation apparatus.
따라서, 본 발명의 기술적 과제는 반도체 소자의 공정을 단순화하는 것이다. Therefore, the technical problem of this invention is to simplify the process of a semiconductor element.
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 상기 반도체 기판 위에 게이트 배선, 게이트 전극 및 게이트 상부 산화막을 형성하는 단계, 상기 게이트 전극 측벽에 실리콘 산화막을 형성하는 단계, 상기 반도체 기판의 노출된 영역에 에피층을 형성하는 단계, 상기 에피층이 포함하고 있는 불순물 이온을 확산시켜 소스 및 드레인 접합 영역을 형성하는 단계를 포함한다.The present invention relates to a method of manufacturing a semiconductor device, comprising: forming a gate wiring, a gate electrode, and an upper oxide film on the semiconductor substrate; forming a silicon oxide film on the sidewall of the gate electrode; Forming an epitaxial layer, and diffusing impurity ions included in the epitaxial layer to form source and drain junction regions.
상기 에피층은 TCS(SiHCl3), DCS(SiH2Cl2) 및 SiH 가스를 사용하여 반도체 기판의 결정축을 따라 성장하는 것이 바람직하다.The epi layer is preferably grown along the crystal axis of the semiconductor substrate using TCS (SiHCl 3), DCS (
상기 에피층의 두께는 1000~3000Å로 형성하는 것이 바람직하다.It is preferable that the thickness of the said epi layer is 1000-3000 micrometers.
상기 에피층은 상기 게이트 전극의 50~90%정도의 두께로 형성하는 것이 바람 직하다.Preferably, the epi layer is formed to a thickness of about 50 to 90% of the gate electrode.
상기 에피층이 포함하고 있는 불순물 이온을 확산시켜 소스 및 드레인 접합 영역을 형성하는 단계에서 상기 불순물 이온의 확산은 700~1200℃의 온도에서 이루어지는 것이 바람직하다.In the forming of the source and drain junction regions by diffusing the impurity ions contained in the epitaxial layer, the diffusion of the impurity ions is preferably performed at a temperature of 700 to 1200 ° C.
상기 에피층은 PH3, AsH3 또는 B2H6 불순물을 첨가하는 것이 바람직하다.The epi layer is preferably added to the PH3, AsH3 or B2H6 impurities.
반도체 기판, 상기 반도체 기판 위에 형성되어 있는 게이트 절연막, 상기 게이트 절연막 위에 형성되어 있는 게이트 전극, 상기 게이트 전극 상부에 형성되어 있는 게이트 상부 산화막, 상기 게이트 전극 측면에 형성되어 있는 실리콘 산화막, 상기 실리콘 산화막 측면에 형성되어 있는 에피층, 그리고 상기 에피층 아래 영역에 형성되어 있는 소스 및 드레인 영역을 포함한다.A semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed over the gate insulating film, a gate upper oxide film formed over the gate electrode, a silicon oxide film formed over the gate electrode side, and the silicon oxide film side surface And an epitaxial layer formed on the substrate, and a source and drain region formed on the region below the epitaxial layer.
상기 게이트 상부 산화막 및 상기 실리콘 산화막은 상기 에피층이 상기 게이트 전극 위에 형성되는 것을 방지하는 것이 바람직하다.이하 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 상세하게 설명하면 다음과 같다. Preferably, the gate upper oxide layer and the silicon oxide layer prevent the epi layer from being formed on the gate electrode. Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 2는 본 발명의 한 실시예에 따른 반도체 소자의 제조 공정을 단계별로 도시한 단면도이다.1 to 2 are cross-sectional views showing step-by-step manufacturing processes of a semiconductor device according to an embodiment of the present invention.
도 1에 도시한 바와 같이, STI(shallow trench isolation)(2)가 형성되어 있는 반도체 기판(1) 위에 하부 산화막을 형성하고, 그 위에 폴리(poly) 실리콘 층과 상부 산화막을 형성한다. 여기서, STI(2)는 반도체 기판(1)에 형성된 소자를 전기적으로 격리 시킴으로써 오동작을 방지한다.As shown in Fig. 1, a lower oxide film is formed on a
이어, 하부 산화막, 폴리 실리콘층 및 상부 산화막층을 사진 식각하여 게이 트 절연막(3), 게이트 전극(4)과 게이트 상부 산화막(5)을 형성한다. 이때, 게이트 전극(4)은 STI(2)가 없는 반도체 기판(1) 위에 형성하고, 게이트 전극(4) 측면에 실리콘 산화막(6a, 6b)을 형성한다.Subsequently, the lower oxide film, the polysilicon layer, and the upper oxide film layer are photo-etched to form a
그런 다음, 도 2에 도시한 바와 같이, 노출된 반도체 기판(1) 위에 에피층(7)을 형성한다.Then, as shown in FIG. 2, the
에피층(7)은 가스 상태의 반도체 결정을 석출하여 반도체 기판의 결정축을 따라 결정을 성장함으로써 형성되는데, 이때, 가스는 TCS(SiHCl3), DCS(SiH2Cl2) 및 SiH를 사용한다. 여기서, 에피층(7)의 두께는 게이트 전극(4)의 50~90%정도의 두께로 형성한다. 이때, 에피층(7)은 1000~3000Å정도의 두께로 형성하는 것이 바람직하다.The
이러한 에피층(7)이 성장할 때, 트랜지스터가 갖는 채널의 특성에 따른 도펀트 물질을 주입한다. When the
NMOS(n-channel metal oxide semiconductor)인 경우, 도펀트는 PH3 또는 AsH3를 사용하며, PMOS(p-channel metal oxide semiconductor)인 경우, 도펀트는 B2H6를 사용한다. In the case of an n-channel metal oxide semiconductor (NMOS), the dopant uses PH3 or AsH3, and in the case of a p-channel metal oxide semiconductor (PMOS), the dopant uses B2H6.
그런 다음, 10초 내지 60분 동안 에피층(7)에 700~1200℃의 열을 가한다. 이에 따라, 에피층(7)이 포함하고 있는 도펀트는 반도체 기판(1) 위에 확산되어 소스 및 드레인 접합 영역(8a, 8b)을 형성한다. 이때, 압력은 대기압에서 760torr 또는 저기압에서 20torr 이상의 압력이 바람직하다.Then, the heat of 700-1200 ° C. is applied to the
본 발명은 첨부된 도면에 도시된 일 실시예를 참고로 설명되었으나 이는 예 시적인 것에 불과하며, 당해 기술분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 수 있을 것이다. 따라서, 본 발명의 진정한 보호범위는 첨부된 청구범위에 의해서만 정해져야 할 것이다.Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.
본 발명에 따르면 실리콘 산화막 측면에 도펀트를 함유한 에피층을 형성하고 열을 가함으로써 소스 및 드레인 접합 영역을 형성함으로써 반도체 소자의 제조 공정을 단순화 할 수 있다.According to the present invention, a process for manufacturing a semiconductor device can be simplified by forming an epitaxial layer containing a dopant on the side of the silicon oxide film and applying heat to form source and drain junction regions.
Claims (8)
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| KR1020050070802A KR100691129B1 (en) | 2005-08-02 | 2005-08-02 | Manufacturing method of semiconductor device |
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| KR1020050070802A KR100691129B1 (en) | 2005-08-02 | 2005-08-02 | Manufacturing method of semiconductor device |
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| KR20070016042A KR20070016042A (en) | 2007-02-07 |
| KR100691129B1 true KR100691129B1 (en) | 2007-03-09 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980081779A (en) * | 1997-04-29 | 1998-11-25 | 빌헬름에핑 | MOOS transistor and its manufacturing method |
| KR20000043199A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Fabrication method of transistor of semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980081779A (en) * | 1997-04-29 | 1998-11-25 | 빌헬름에핑 | MOOS transistor and its manufacturing method |
| KR20000043199A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Fabrication method of transistor of semiconductor device |
Non-Patent Citations (2)
| Title |
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| 1019980081779 * |
| 1020000043199 * |
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| KR20070016042A (en) | 2007-02-07 |
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