KR100689819B1 - Semiconductor memory device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The apparatus includes a memory cell array including at least one cell capacitor, and on-chip bypass capacitors each including at least two series connected capacitor arrays, each capacitor array including a plurality of parallel connected capacitors, and a plurality of parallel connected capacitors. Capacitors connected in parallel have the same structure as cell capacitors, and the voltage difference between the voltages applied across the on-chip bypass capacitors is a voltage equal to or less than a product of the breakdown voltage of each of the capacitors multiplied by the number of capacitor arrays. do. Therefore, it is possible to reduce the voltage difference applied to both ends of the capacitor to prevent deterioration of the oxide film formed between both electrodes of the on-chip bypass capacitor array. In addition, the number of on-chip bypass capacitor arrays connected in series can be minimized, so that the layout area is not increased and the capacitance is not reduced.

Description

Semiconductor memory device

1 shows an embodiment of an on-chip bypass capacitor of a semiconductor memory device of the present invention.

FIG. 2 shows a configuration of an embodiment of the capacitor array shown in FIG.

Figure 3 shows a semiconductor memory device of an embodiment with an on-chip bypass capacitor of the present invention.

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an on-chip bypass capacitor having the same structure as the memory cell capacitor.

The on-chip bypass capacitor of the semiconductor memory device is a basic component used to filter out a large amount of noise present between operating power supplies such as a power supply voltage and a ground voltage.

In general, the on-chip bypass capacitor of the conventional semiconductor memory device is filled in the empty space of the peripheral circuit region, not the memory cell array region. Therefore, the area where the on-chip bypass capacitor is filled is limited, and the filtering effect is increased only when the on-chip bypass capacitor having a large capacitance is formed in the limited area.

The on-chip bypass capacitor of the conventional semiconductor memory device is constructed by connecting a plurality of MOS capacitors in parallel between a power supply voltage generation line and a ground voltage line. However, when the MOS capacitor is used as an on-chip bypass capacitor, it is impossible to have a large capacitance. Therefore, a method of using a memory cell capacitor as an on-chip bypass capacitor that can form a large capacitance in a small area compared to the MOS capacitor has emerged. This information is introduced in Korean Patent Application No. 2004-6875.

The on-chip bypass capacitors introduced here can be formed using the same fabrication process as the on-chip bypass capacitors as the memory cell capacitors, and the voltages at both ends of the on-chip bypass capacitors are the supply voltage (VDD) and the ground voltage (VSS), respectively. It is disclosed that it may be. In order to reduce the voltage difference between the two ends of the on-chip bypass capacitor, at least two series connected capacitor arrays are employed.

In addition, in the conventional on-chip bypass capacitor, when the voltage at both ends becomes the power supply voltage VDD and the ground voltage VSS, the voltage difference between both ends becomes small, thereby preventing the problem of deterioration of the oxide film formed between the two electrodes. Can be.

However, various internal voltages exist in the semiconductor memory device, and some of these voltages have higher levels than the internal power supply voltages. Therefore, when a conventional on-chip bypass capacitor is constructed between these voltages and the external ground voltage, the voltage difference across the capacitor becomes larger than the breakdown voltage of the capacitor, causing deterioration in the oxide film between the capacitor's both electrodes. There is.

Of course, in order to solve this problem, connecting a large number of capacitor arrays in series between these voltages and the external ground voltage can reduce the voltage difference between the two electrodes of the capacitor array, but the capacitance becomes smaller. There is a problem that the layout area is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of preventing the deterioration of an oxide film formed between both electrodes by reducing the voltage difference between both electrodes of the on-chip bypass capacitor array while minimizing an increase in layout area.

A semiconductor memory device of the present invention for achieving the above objects comprises a memory cell array including at least one cell capacitor, and on-chip bypass capacitors each including at least two series connected capacitor arrays, each capacitor array having a plurality of And a plurality of parallel connected capacitors, wherein the plurality of parallel connected capacitors have the same structure as the cell capacitor, and a voltage difference between voltages applied across the on-chip bypass capacitors is equal to the breakdown voltage of each of the plurality of capacitors. The voltage is less than or equal to a value multiplied by the number of arrays.

The cell capacitor may be a capacitor having a metal-insulator-semiconductor (MIS) structure, or a capacitor having a metal-insulator-metal (MIM) structure.

An external power supply voltage applied from the outside of each of the on-chip bypass capacitors, an external ground voltage applied from the outside, a first internal power supply voltage lower than the external power supply voltage and higher than the external ground voltage, and higher than the external power supply voltage A second internal power supply voltage, a third internal power supply voltage lower than the external ground voltage, and two different voltages among the fourth internal power supply voltages lower than the first internal power supply voltage and higher than the external ground voltage are applied. It is done.

Hereinafter, a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

1 illustrates an embodiment of an on-chip bypass capacitor of a semiconductor memory device of the present invention, in which an internal circuit (or memory cell array capacitor) connected between internal voltages V1 and V2 and an on-chip bypass in parallel with the internal circuit are shown. And a pass capacitor, wherein the on-chip bypass capacitor includes at least two capacitor arrays C1 and C2 connected in series. The total capacitance of the on-chip bypass capacitor illustrated in Figure 1 is

Ctotal = (C1 × C2) / (C1 + C2)

And the voltage across the capacitor arrays C1 and C2 is

ΔV = 1/2 × (V1-V2)

to be.

In FIG. 1, at least two capacitor arrays connected in series are shown, but may include three or more capacitor arrays. However, in the case of three or more capacitor arrays, the layout area takes up more than the two capacitor arrays, and the capacitance becomes small. Therefore, it is desirable to include two capacitor arrays connected in series.

If the breakdown voltage of the capacitor of the capacitor array is VCBV when the on-chip bypass capacitor is composed of two capacitor arrays, the voltage difference between the voltages V1 and V2 applied to both ends of the on-chip bypass capacitor is 2VCBV. It is desirable to set the voltage to be less than or equal to

FIG. 2 shows the configuration of the embodiment of the capacitor array shown in FIG. 1, wherein the capacitor array C1 is composed of four parallel-connected capacitors C1-1 to C1-4. Although not shown, the capacitor array C2 may also be configured to include four parallel connected capacitors.

In addition, although FIG. 2 illustrates that the capacitor array is composed of four parallel connected capacitors, four or more capacitors may be connected in parallel.

The capacitors constituting the on-chip bypass capacitors of FIGS. 1 and 2 may be formed using the same process steps as those used for the memory cell capacitor, and due to the parallel connection of the capacitors of the on-chip bypass capacitor arrays. Capacitance can be large and deterioration of the oxide layer can be prevented by decreasing the voltage difference between both electrodes of the capacitor due to the series connection of the on-chip bypass capacitor arrays.

In general, an internal power supply voltage VEXT applied from the outside, an external ground voltage VSS applied from the outside, and high voltages used to enable other internal voltages, for example, word lines, are provided in the semiconductor memory device. (VPP), internal power supply voltage (VINTA) for memory cell arrays for memory cell arrays, internal power supply voltage (VINTP) for peripheral circuits for peripheral circuits, bit line precharge voltage (VBL) for precharging bit lines, There is a voltage VP applied to the cell capacitor of the memory cell, and a substrate voltage VBB applied to the substrate. As a result, the voltages V1 and V2 across the on-chip bypass capacitor of the semiconductor memory device of the present invention may be these voltages, and the voltage difference between these voltages is less than or equal to the breakdown voltage VCBV of the capacitor. By setting the same value, it is possible to prevent deterioration of the oxide film formed between the both electrodes of the capacitor.

Figure 3 shows a semiconductor memory device of an embodiment with an on-chip bypass capacitor of the present invention, wherein the internal voltages VPP, VEXT, VINTP / VINTA, VP / VB, VSS, VBB, and on-chip bypass capacitors ( 30, 32, 34, 36, 38, 40, 42). In addition, each of the on-chip bypass capacitors 30, 32, 34, 36, 38, 40, and 42 is composed of on-chip bypass capacitor arrays C1 and C2.

The breakdown voltage (VCBV) of the cell capacitor is approximately VINTA / 2, which is set almost equal to the precharge voltage VBL, and the level of these voltages is VPP> VEXT> VINTP (VINTA)> VP (VBL)> VSS. > VBB is set to be. In Fig. 3, the voltage difference (V1-V2) between these adjacent voltages is less than or equal to 2VCBV, and between the high voltage (VPP) and the internal power supply voltage (VINTP / VINTA) for the memory cell array and the peripheral circuit. It is shown assuming that the voltage difference and the voltage difference between the cell capacitor and the bit line voltage VP / VBL and the substrate voltage VBB are less than or equal to 2VCBV.

In FIG. 3, the on-chip bypass capacitor 30 is between the voltage VPP and the external power supply voltage VEXT, and the on-chip bypass capacitor 32 is between the voltage VEXT and the voltage VINTP / VINTA, and the on-chip bypass capacitor 34 is between voltage VINTP / VINTA and voltage VP / VBL, on-chip bypass capacitor 36 is between voltage VP / VBL and voltage VSS, and on-chip bypass capacitor 38 is voltage ( Between VSS) and voltage VBB, on-chip bypass capacitor 40 between voltage VPP and voltage VINTP / VINTA, and on-chip bypass capacitor 42 between voltage VP / VBL and voltage VBB. Is connected to.

The capacitor arrays C1 and C2 of FIG. 3 may be formed using the same process steps as those used for the memory cell capacitors. That is, the capacitor arrays C1 and C2 may be capacitors of a metal-insulator-semiconductor (MIS) structure or a metal-insulator-metal (MIM) structure. In addition, the capacitors C1 and C2 of some of the on-chip bypass capacitors of the on-chip bypass capacitors 30, 32, 34, 36, 38, 40, and 42 are the same as the process steps used for the memory cell capacitor. Formed using a step, the remainder may be formed using the same process step as the process step used for the MOS capacitors. That is, capacitors constituting the capacitor arrays C1 and C2 of all on-chip bypass capacitors may be configured as memory cell capacitors, and capacitor arrays C1 of on-chip bypass capacitors of some of all on-chip bypass capacitors. The capacitors constituting C2) may be configured as MOS capacitors rather than memory cell capacitors. In this case, the on-chip bypass capacitor composed of MOS capacitors does not need to be connected in series like the capacitor arrays C1 and C2.

In the on-chip bypass capacitor of the semiconductor memory device of the present invention, when the voltage difference applied to both ends of the capacitor is small enough to be less than or equal to the breakdown voltage of one capacitor array, only one capacitor array is connected to the on-chip bypass capacitor. It can also be configured.

While embodiments of the invention have been described with respect to two on-chip bypass capacitor arrays, it will be appreciated by those skilled in the art that any number of more than three on-chip bypass capacitor arrays may be used. Although embodiments of the present invention have been described as each on-chip bypass capacitor array comprising four capacitors, one of ordinary skill in the art will appreciate that one or more of any number of capacitors may be used. In addition, the skilled person will appreciate that the number of capacitors in each on-chip bypass capacitor array may vary.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

 The semiconductor memory device of the present invention can prevent the deterioration of the oxide film formed between both electrodes of the on-chip bypass capacitor array by reducing the voltage difference applied to both ends of the capacitor.

Thus, the number of on-chip bypass capacitor arrays connected in series can be minimized, thereby not increasing the layout area and reducing the capacitance.

Claims (4)

A memory cell array comprising at least one cell capacitor; And Have on-chip bypass capacitors each including at least two series-connected capacitor arrays, Each capacitor array includes a plurality of parallel connected capacitors, The plurality of parallel connected capacitors have the same structure as the cell capacitor, And a voltage difference between voltages applied across the on-chip bypass capacitors is a voltage less than or equal to a value of a breakdown voltage of each of the plurality of capacitors multiplied by the number of the capacitor arrays. The method of claim 1, wherein the cell capacitor A semiconductor memory device comprising a capacitor having a metal-insulator-semiconductor (MIS) structure. The method of claim 1, wherein the cell capacitor A semiconductor memory device comprising a capacitor having a metal-insulator-metal (MIM) structure. The capacitor of claim 1, wherein both ends of each of the on-chip bypass capacitors are disposed. An external power supply voltage applied from the outside, an external ground voltage applied from the outside, a first internal power supply voltage lower than the external power supply voltage and higher than the external ground voltage, a second internal power supply voltage higher than the external power supply voltage, and the external ground voltage And a third lower internal power supply voltage and two different voltages from among the fourth internal power supply voltages lower than the first internal power supply voltage and higher than the external ground voltage.

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