KR100689383B1 - Apparatus and method for compensate of timing margin loss as capacitance load between microprocessor and input/output unit - Google Patents

Abstract

The present invention relates to an apparatus and a method for improving timing margin reduction due to overlap of capacitance load when fan out is increased. The present invention relates to a microprocessor and a plurality of input / output chips. A system for performing parallel communication between I / O chips, the system comprising: at least one timing delay unit connected in series between the microprocessor and the plurality of input / output chips connected in parallel with the microprocessor; The delay unit is configured to delay the time of each of the output signals of the microprocessor in response to a time delay caused by the capacitance load inherent to the plurality of input / output chips, thereby preventing a malfunction of the microprocessor parallel bus.

Microprocessor, Parallel Bus, Fan Out, Timing Margin, Capacitance Load

Description

Apparatus and method for improving timing margin reduction due to overlapping capacitance load between microprocessor and input / output devices             

1 is a view schematically illustrating a structure in which other input / output chips are connected to a parallel bus of a processor according to the prior art;

2 is a diagram illustrating an embodiment of a structure in which other input / output chips are connected to a parallel bus of a processor according to the present invention;

3 illustrates another embodiment of a structure in which other input / output chips are connected to a parallel bus of a processor according to the present invention.

The present invention relates to a parallel communication device and a method thereof between a processor and an input / output device, and in particular, it is possible to improve a timing margin deterioration due to overlapping capacitance loads when fan out is increased for parallel communication between a microprocessor and an input / output device. It relates to an apparatus and a method.

In general, parallel communication is performed between a microprocessor and a memory or other I / O chip. The connection between the microprocessor and the memory and the other input / output chips is connected through a parallel bus or a local bus, and at this time, an address, a data signal line and other control signals are controlled. The signal lines are shared with each other, and a chip select signal line for selecting each chip is individually connected to a plurality of input / output chips connected in parallel to the microprocessor.

Hereinafter, a parallel signal connection structure between a microprocessor and other input / output devices according to the related art will be described with reference to FIG. 1.

1 is a diagram schematically illustrating a structure in which other input / output chips are connected to a parallel bus of a processor according to the prior art.

Referring to FIG. 1, a microprocessor 101 and a plurality of input / output chips (I / O chips) 111 to 119 are formed, wherein the input / output chip is a memory, for example. A device for inputting a predetermined signal and outputting a signal corresponding to the input signal as shown in FIG.

As shown in FIG. 1, the microprocessor 101 is connected to the plurality of input / output chips 111 to 119 through a parallel bus or a local bus. In this case, an address / data (ADDR / DATA) signal and a control signal line are shared by the plurality of input / output chips 111 to 119. That is, as shown in FIG. 1, the address / data signal and the control signal line are connected to any one input / output chip, for example, the input / output chip 111 located at the top, and the plurality of parallel connection with the input / output chip 111. The input / output chips 113 to 119 share with each other. In addition, a chip select signal line (CS) for selecting each of the plurality of input / output chips 111 to 119 is individually connected to each of the plurality of input / output chips 111 to 119. That is, the chip select signal CS0 is connected to the input / output chip CHIP0 111 located at the top, the chip select signal CS1 is connected to the input / output chip CHIP1 113, CS2 is connected to the input / output chip CHIP2 115, and CS3 is the input / output chip. The chip CHIP3 117 is connected, and the CS4 is individually connected to the input / output chip CHIP4 119, respectively.

However, in the case of using the connection method according to the conventional method as described above, the number of input / output chips that can be connected to the parallel bus is limited due to the limitation of the driving current in the microprocessor 101. In addition, since the input / output chips respectively connected to the microprocessor 101 have unique capacitance load values of the input / output chips, the capacitance load value is increased whenever the parallel bus sequentially passes through the input / output chips connected to the microprocessor 101. It will continue to overlap. In addition, the signal delay is also weighted according to the overlap of the capacitance load value. For example, assuming a delay of Nns due to a unique capacitance load of the plurality of input / output chips 111 to 119, the delay of about 5Nns is finally added to the CHIP4 119 connected to the lowest end. .

For example, when the capacitance load value of the input / output chips as described above is 10 pF, there is a delay of 1 ns. In the case of a flash memory that is generally used, the capacitance load of about 30 pF is passed through the input / output chips. The signal on the parallel bus will have a delay of about 3 ns and the value of the continuation signal will have a delay each time the chips are connected to the parallel bus.

Therefore, as shown in FIG. 1, when a plurality of input / output chips are connected to the microprocessor 101, an address / data signal and a control signal overlap the delays of the continuous signal while passing through the connected input / output chips. On the other hand, chip select pins for selecting respective input / output chips are connected to each input / output chip without delay, and an error occurs as data is transmitted or received. As a result, the number of fan outs due to the driving current limitation of the microprocessor parallel bus is limited, but there is a problem in that the input and output chips have more restrictions. In addition, even if only the case in which the microprocessor receives the signals from the input and output chips, there is a problem in that the number of the input and output chips to increase the number of limitations. In this case, the fan out refers to the number of output lines connected by distributing the output of one gate to another in an electronic circuit, which is related to the output power that the gate can afford. It also refers to the number of submodules that a module calls directly in a structural system design, which requires that this not exceed seven.

In other words, when the fan out increases as the parallel connection between the microprocessor and the input / output chips using the parallel bus or the local bus different from the prior art increases, the capacitance load of each interface chip has The values overlap and increase. As a result, the delay of the signal is gradually increased in each of the input / output chips, which causes a problem in that a system error occurs in transmitting and receiving a signal.

Accordingly, the present invention was devised to solve the above-described problems of the prior art, and an object of the present invention is to provide a delay in time caused by capacitance load inherent in I / O chips when connecting memory and other I / O chips to a parallel bus of a microprocessor. The present invention provides an apparatus and method for improving timing margin reduction due to overlapping capacitance loads.

Another object of the present invention is to provide an apparatus and method for improving timing margin reduction caused by overlapping capacitance loads by preventing time delay due to overlapping capacitance loads between a microprocessor and an input / output device. Is in.

An apparatus according to an embodiment of the present invention for achieving the above objects; A system for performing parallel communication between a microprocessor and a plurality of I / O chips, the system being connected in series between the microprocessor and the plurality of input / output chips connected in parallel with the microprocessor. At least one timing delay device, wherein the timing delay device delays the time of each of the output signals of the microprocessor in response to a time delay caused by a capacitance load inherent to the plurality of input and output chips. Features of the jacket.

Method according to an embodiment of the present invention for achieving the above objects; In a system for performing communication using a parallel bus between a microprocessor and a plurality of I / O chips, a method for preventing a malfunction of the parallel bus, the microprocessor and the micro At least one timing delay unit connected in series between the plurality of input / output chips connected in parallel with a processor, wherein a time delay caused by a capacitance load inherent to the plurality of input / output chips for each of the output signals of the microprocessor is included; In response to the control, the delay time is transmitted.

In addition, the timing delay unit adds a time delay to the chip select signal of the microprocessor which is individually connected to the input / output chips, so that the address / data and the control signal of the microprocessor occur in the parallel input / output chips. It is characterized by synchronizing delay and timing margin.

In addition, when the parallel bus of the microprocessor has a timing margin, the timing delay unit does not delay a chip select signal input to the input / output chips belonging to a range allowed by the timing margin when connecting the input / output chips. And a time delay corresponding to the timing margin from the input / output chip deviating from the timing margin.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

According to the present invention, when a memory and other I / O chips are connected to a parallel bus or a local bus of a processor, a capacitance load inherent in the I / O chips is provided. By reducing the time delay caused by the, it is possible to prevent the malfunction of the parallel bus or local bus.

In general, when a fan out is increased by sequentially connecting memory or other input / output chips using a parallel bus of a microprocessor, capacitance load values of an interface chip overlap each other. Will increase. This causes a delay in the signal, which increases the possibility of generating an error in sending and receiving a signal. Accordingly, the present invention proposes an apparatus and method for improving the occurrence of a system error by preventing the signal delay caused by the capacitance load overlap as described above.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings of FIGS. 2 and 3 to improve timing margins according to an exemplary embodiment of the present invention.

2 is a diagram illustrating another embodiment of a structure in which other input / output chips are connected to a parallel bus of a processor according to the present invention. In particular, FIG. 2 is a diagram illustrating an embodiment in which a timing delay is applied to each chip selection to prevent a malfunction of a parallel bus of a processor.

Referring to FIG. 2, a microprocessor 201, a plurality of input / output chips 211 to 219, and a plurality of timing delayers 231 to 237 are included. The fields 231 to 237 are connected to the chip select signals CS1 to CS4 respectively output from the microprocessor 201, and the microprocessor 201 may be used to prevent malfunction of parallel buses of the microprocessor 201. Delays the time of each of the chip select signals, e.g., CS1 to CS4.

As shown in FIG. 2, when the memory or input / output chips 211 to 219 are connected through the microprocessor 201 parallel bus, capacitance loads of the input / output chips 211 to 219 overlap each other. A method for improving a malfunction of a parallel bus according to a time delay of a generated signal, except for an input / output chip 211 connected to the first chip selection signal CS0 of the microprocessor 201, that is, located at the top thereof. A delay chip, that is, a timing delay unit, is connected to a chip select signal individually connected to each of the input / output chips 213 to 219.

Hereinafter, an operation configuration between a microprocessor and an input / output chip having the above configuration will be described.

In the operating method of FIG. 2, when the other input / output chips 211 to 219 are connected through a parallel bus of the microprocessor 201, the address / data (ADDR / DATA) and control (CONTROL) of the microprocessor 201 are controlled. ) Signals are daisy-chained.

Here, the daisy chain method is a process in which the request processing circuits are arranged in series and preferentially processed from the closest to a central processing unit (CPU) such as the microprocessor when there are many devices generating an interrupt request. Say the way. Meanwhile, whenever the address / data and control signals pass through the input / output chips 211 to 219 connected in the daisy chain manner, the signals are controlled by their capacitance loads of the input / output chips 211 to 219. The timing delay occurs in these fields.

On the other hand, the chip select signals CS0 to CS4 of the microprocessor 201 are individually connected to each of the input / output chips 211 to 219 without undergoing a timing delay unlike the address / data and control signals. Therefore, as the number of the input / output chips 211 to 219 connected to the microprocessor 201 and the parallel bus increases, the time interval between the chip select signals CS0 to CS4 and the address / data and control signals becomes longer. do. This causes a malfunction of the parallel bus.

Accordingly, the present invention includes timing delayers 231 to 237 for providing a time delay to the chip select signals CS1 to CS4 that are individually connected to the respective input / output chips 211 to 219. To configure. Accordingly, in the present invention proposed by the above-described daisy chain method, a timing delay is applied to each of the chip select signals by a timing delay that increases whenever the input / output chips increase, thereby preventing malfunction of the parallel bus. Can be.

That is, using the time delay chip, for example, the timing delayers 231 to 237, to the chip select signal that is individually connected to the input / output chips 211 to 219 on the parallel bus of the microprocessor 201, the address / data and In response to the time delay caused by the continuous connection of the control signals, the time for reaching the respective input / output chips is delayed to prevent malfunction of the parallel bus.

For example, the control signal of the microprocessor 201 is input to CHIP0 211 and sequentially passes from CHIP1 213 to CHIP4 219. At this time, when it is assumed that each of the CHIP0 211 to CHIP4 219 has a delay of Nns, the control signal passing through the CHIP0 211 is the CHIP0 211 and the CHIP1 213 at the CHIP1 213. ) Is added to have a delay of 2Nns.

On the other hand, as the chip select signals CS0 and CS1 are directly input to the CHIP0 211 and the CHIP1 213, respectively, the time delay of the control signal does not occur. Accordingly, a difference occurs in the timing margin between the control signal input to the CHIP1 213 and the chip selection signal CS1, thereby causing a malfunction of the parallel bus.

Therefore, a timing delay unit 231 is provided on the parallel bus between the chip select signal CS1 and the CHIP1 213 to remove the chip select signal CS1 from the timing margin to which the control signal is applied, thereby preventing malfunction of the parallel bus. do.

In addition, when the capacitance load value of the input / output chips as described above is 10pF, there is a delay of 1 ns. In the case of a flash memory that is generally used, it has a capacitance load of about 30 pF. Signal is weighted by passing through the input / output chips to have a delay of about 3ns. This delay weighting also results in a delay in the value of the continuous signal each time the chips are continuously connected to the parallel bus.

Accordingly, by controlling the delay of the chip select signal in response to 3 ns as described above or the delay weighted by the input / output chips through the timing delay unit, the timing margin of the address / data and control signals and the chip select signals are synchronized. By doing so, it is connected to the parallel bus through which the malfunction of the parallel bus can be prevented.

3 is a diagram illustrating another embodiment of a structure in which other input / output chips are connected to a parallel bus of a processor according to the present invention. In particular, FIG. 3 illustrates an embodiment in which a time delay is applied to chip selection in consideration of a timing margin of a parallel bus of a processor.

Referring to FIG. 3, as shown in FIG. 2, a microprocessor 301, a plurality of input / output chips 311 to 319, and a plurality of timing delayers 331 to 333 are included. The timing delayers 331 to 333 delay the time of each of the chip select signals of the microprocessor 301, for example CS3 to CS4, in consideration of the timing margin of the parallel bus of the microprocessor 301. It performs the function.

As shown in FIG. 3, when the memory or input / output chips 311 to 319 are connected through the microprocessor 301 parallel bus, capacitance loads of the input / output chips 311 to 319 overlap each other. The timing margin of the parallel bus according to the time delay of the generated signal is considered. Such a configuration is such that when the parallel bus has a timing margin that operates correctly even if a certain time delay occurs, for example, when the parallel bus has a time delay exceeding the timing margin from the fourth connected input / output chip 317, the fourth input / output From the chip select signal CS3 connected to the chip 317, a time delay chip, i.e., a timing delay device, is connected so that the parallel bus can operate inside the timing margin.

In other words, when the parallel bus of the microprocessor 301 has a timing margin, FIG. 3 shows input / output chips to a range allowed by the timing margin when connecting a memory and other input / output signals. In the case of the connection, a timing delay unit is not used for each chip select signal, whereas an input / output chip burner which is connected to the input / output chip and the input / output chips are continuously connected to leave the timing margin has a timing delay corresponding to the timing margin. By applying a chip to the chip select signal, it is possible to prevent the malfunction of the parallel signal.

The present invention proposed as described above relates to an apparatus and method for improving problems in the prior art, that is, in the prior art, as the memory and other input / output chips connected to the parallel bus of the microprocessor increase, Since the capacitance load inherent in the chip I / O pin is continuously overlapped, the delay of the signal increases, thereby causing the parallel bus to malfunction. In addition, when a signal delay occurs due to the overlap of the capacitance loads, a limited number of input / output chips have to be used rather than the fan-out number due to driving current limitation.

However, in the present invention, by passing the chip select signals through a timing delay unit, the timing margin between the address / data and control signals and the chip select signals can be improved, thereby preventing malfunction of the parallel bus.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

As described above, according to the apparatus and method for improving timing margin reduction according to capacitance load overlap between the microprocessor and the input / output device of the present invention, by providing a time delay suitable for the chip select signals, The timing margin between the chip select signals can be improved, thereby preventing the malfunction of the parallel bus.

In addition, when connecting memory and other I / O chips to the parallel bus or local bus of the microprocessor, it is possible to prevent the time delay caused by the capacitance load inherent in the I / O chips, and to delay the time due to the overlap of the capacitance load between the microprocessor and the I / O device. By preventing the above, the malfunction of the parallel bus can be prevented in advance.

Claims (6)

In a system for performing parallel communication between a microprocessor and a plurality of I / O chips, At least one timing delay unit connected in series between the microprocessor and the plurality of input / output chips connected in parallel with the microprocessor, The timing delay unit delays each of the output signals of the microprocessor in response to a time delay caused by a capacitance load inherent to the plurality of input / output chips, When the parallel bus of the microprocessor has a timing margin, the timing delay unit does not give a time delay to a chip select signal input to the input / output chips belonging to a range allowed by the timing margin when connecting the input / output chips. And a time delay corresponding to the timing margin from the input / output chip deviating from the timing margin. The method of claim 1, The timing delay unit adds a time delay to a chip select signal of the microprocessor which is individually connected to the input / output chips, so that a time delay occurs when the address / data and the control signal of the microprocessor occur on the parallel input / output chips. And parallel timing synchronization. delete In a system for performing communication using a parallel bus between a microprocessor and a plurality of I / O chips, a method for preventing a malfunction of the parallel bus, At least one timing delay unit connected in series between the microprocessor and the plurality of input / output chips connected in parallel with the microprocessor, For each of the output signals of the microprocessor to control and transmit the delay time corresponding to the time delay caused by the capacitance load inherent to the plurality of input and output chips, The time delay control may be performed without delaying a chip select signal input to the input / output chips belonging to a range allowed by the timing margin when connecting the input / output chips when the parallel bus of the microprocessor has a timing margin. And providing a time delay corresponding to the timing margin from an input / output chip that deviates from the timing margin. The method of claim 4, wherein The time delay control gives a time delay to a chip select signal of the microprocessor which is individually connected to the input / output chips, so that the address / data and the control signal of the microprocessor occur in the parallel input / output chips. A method for preventing a malfunction of a parallel bus, characterized by synchronizing delay and timing margin. delete

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