KR100684890B1 - Serdes system - Google Patents

Abstract

A SerDes(Serializing/Deserializing) system is provided not to be overhead to the size of the semiconductor IC by including a pipeline and a serial-parallel signal converter for transceiving a signal even if a command packet is received without gap. A controller(100) manages signal transceiving with a memory device(200). A pipeline(320) transfers the signal transceived by the controller in a serial type. A serializer of a serial-parallel signal converter(340) converts a parallel signal transferred through the pipeline into a serial signal by responding to a control signal, and transfers the serial signal to the memory device. A deserializer of the serial-parallel converter converts a serial signal received from the memory device into the parallel signal by responding to the control signal, and transfers the parallel signal to the pipeline. A control signal generation circuit(360) generates the control signal. The semiconductor IC device is a DRAM and the controller is an FPGA(Field Programmable Gate Array).

Description

Suddes System

1 is a block diagram of a suddes system according to the present invention.

2 is an embodiment of a sudes system according to the present invention.

3 is a timing diagram when a command is issued at no intervals in the Sustain system according to the present invention.

* Explanation of symbols for main parts of drawings *

320: pipeline

322: command pipeline

324: data pipeline

340: serial-to-parallel signal converter

342: mux, 344: mux and demux

321: CRQ pin, 343: XRQ pin

323: CDQ pin, 345: XDQ pin

TECHNICAL FIELD The present invention relates to semiconductor integrated circuits, and more particularly, to a suddes system for use in semiconductor integrated circuits.

Semiconductor integrated circuits are interconnected on a substrate and integrated on a higher order. Small integrated circuits (SSI) of less than 100 integrated semiconductors, medium scale integrated circuits (MSI) of about 100 to 1000, and large scale integrated circuits (LSI) of more than 10,000 are called. It is called VLSI (Very LSI). In monolithic semiconductor integrated circuits, the degree of integration refers to the number of individual electrical circuit elements, such as transistors, diodes, resistors, and capacitors, interconnected on small chips of one- to-a-millimeter square silicon sheets.

The LSI increases the economic efficiency of the semiconductor device, such as lowering the price per function and lowering the price of the entire assembled electronic system. Further, high performance, high reliability, miniaturization, and low power consumption of the electronic device and system are achieved.

The SERDES system is a system related to the transmission and reception of signals transmitted between devices in a semiconductor integrated circuit. The SERDES system converts a parallel signal into a serial signal or converts a serial signal into a parallel signal. In general, Sustain systems include serializers and deserializers. Here, a serializer is a device for converting parallel signals into a serial signal, and a deserializer is a device for converting serial signals into a parallel signal. Suddes systems are now widely employed to perform higher bandwidth data communications in semiconductor integrated circuits.

Conventional Sudes systems use registers such as First In First Out (FIFO). The FIFO is the operation performed on the input value first entered into the register. If you need to keep sending command packets gapless, you should use a FIFO. However, registers must increase in proportion to the number of command packets output at a gapless rate. This is an overhead in the size of the semiconductor integrated circuit.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a sustain system in which the size of a semiconductor integrated circuit does not become an overhead even when an instruction packet is transmitted at an interval.

Sude system according to the present invention; A controller that controls transmission and reception of signals with the semiconductor memory device; A pipeline for transmitting signals transmitted and received by the controller in parallel; The parallel signal transmitted from the pipeline is converted into a serial signal in response to a control signal and transmitted to the semiconductor memory device, or the serial signal transmitted from the semiconductor memory device is converted into a parallel signal in response to a control signal to the pipeline. A serial-to-parallel signal converter for transmitting; And a control signal generation circuit for generating the control signal.

In this embodiment, the semiconductor memory device is a DRAM.

In this embodiment, the semiconductor memory device is characterized in that it operates at a higher frequency than the controller.

In this embodiment, the controller is characterized in that the field programmable gate array (FPGA).

In this embodiment, the signal to be transmitted and received is characterized in that the data signal and the command signal.

In this embodiment, the pipeline is characterized in that each pipeline is provided for processing the data signal and the command signal.

In this embodiment, the serial-to-parallel signal converter is characterized in that the mux and demux.

In this embodiment, the control signal generation circuit is characterized in that the synchronization circuit.

In this embodiment, the synchronous circuit is a phase locked loop (PLL).

In this embodiment, the synchronization circuit is a DLL (Delay Locked Loop).

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 is a block diagram of a suddes system according to the present invention. The sused system includes a controller 100, a memory device 200, and a sused device 300. The suddes apparatus 300 includes a pipeline 320, a series-parallel signal converter 340, and a control signal generation circuit 360.

The controller 100 exchanges signals with the memory device 200. The controller 100 operates at a lower frequency than the memory device 200. The controller 100 may use a field programmable gate array (FPGA). FPGAs are a form of programmable logic chip. FPGAs are similar to programmable logic devices (PLDs), but FPGAs typically support thousands of gates, while PLDs are typically limited to hundreds of gates. Both are popular for prototyping integrated circuit designs. Once the design is confirmed, FPGAs are produced with chips with permanent electronics to further improve performance.

The memory device 200 operates at a higher frequency than the controller 100. The memory device 200 may use various semiconductor memory devices such as DRAM, SRAM, and PRAM.

Pipeline 320 is located between controller 100 and serial-to-parallel signal converter 320. The pipeline 320 transmits the parallel signal generated by the controller 100 to the serial / parallel signal converter 340 or the parallel signal converted by the serial / parallel signal converter 340 to the controller 100.

The serial to parallel signal converter 340 is located between the memory device 200 and the pipeline 320. The serial-to-parallel signal converter 340 includes a serializer for converting a parallel signal into a serial signal and a deserializer for converting a serial signal into a parallel signal. The serializer converts the parallel signal passing through the pipeline 320 into a serial signal and delivers the serial signal to the memory device. The deserializer converts the serial signal generated by the memory device 200 into a parallel signal and transmits the serial signal to the pipeline 320. At this time, the serial-to-parallel signal converter 340 converts the parallel signal into a serial signal or converts the serial signal into a parallel signal in response to the control signal generated by the control signal generation circuit 360.

The control signal generation circuit 360 generates a control signal and transmits the control signal to the serial / parallel signal converter 340. The control signal generation circuit 360 may be a synchronization circuit. The synchronization circuit may use a phase locked loop (PLL) or a delay locked loop (DLL).

2 is an embodiment of a sudes system according to the present invention. The sused system includes the FPGA 100, the DRAM 200, and the sused device 300.

For convenience of description, it is assumed that the FPGA 100 operates at 200 MHz and the DRAM 200 operates at 800 MHz. Relatively, the FPGA 100 is a low frequency controller, and the DRAM 200 is a high frequency memory device. The sustain device 300 includes a command signal line for managing the command signal CMD and a data signal line for managing the data signal DATA.

The command signal line includes a CRQ pin 321, a command pipeline 322, a mux 342, and an XRQ pin 343. The CRQ pin 321 is a low frequency command pin, and the XRQ pin 343 is a high frequency command pin. The CRQ pin 321 receives a command signal generated by the FPGA 100. The command signal input through the CRQ pin 321 is output through the XRQ pin 343 through the sustain device and transferred to the DRAM 200. Here, the number of CRQ pins 321 and XRQ pins 343 is adjusted so that input / output signals through the sustain device have the same bandwidth.

The command pipeline 322 is a path for transmitting command signals input through the CRQ pin 321 to the mux 342. The command signals passed are signals in parallel form.

The mux 342 converts the parallel command signal received from the command pipeline 322 into a serial command signal in synchronization with the PLL 360. The serial command signal is transmitted to the DRAM 200 through the XRQ pin 343. The DRAM 200 is activated according to the command signal transmitted from the XRQ pin 343 pin.

The data signal line includes a CDQ pin 323, a data pipeline 324, a mux and demux 344, and an XDQ pin 345.

The data signal line is used to read or write the data signal DQ generated in the FPGA 100 to the DRAM 200. The CDQ pin 323 is a low frequency input / output data pin. The XDQ pin 345 is an input / output data pin for high frequency.

The data pipeline 324 includes a write pipeline and a read pipeline. The light pipeline is a passage of data used when the FPGA 100 wants to store data in the DRAM 200. The lead pipeline is a data path that the FPGA 100 uses when reading data from the DRAM 200.

The sustain system according to the present invention operates as follows.

First, assume that the FPAG 100 intends to perform a write operation on the DRAM 200. The FPGA 100 generates a command signal for activating a write operation to the DRAM 200. The command signal generated from the FPGA 100 is transmitted to the DRAM 200 through the sustain device. The DRAM 200 is activated to enable a write operation by the transferred command signal. The FPGA 100 generates a data signal for storing in the DRAM 200. The CDQ pin 323 receives the data signal generated by the FPGA 100. The data signal received from the CDQ pin 323 is transmitted to the mux and demux 344 through the light pipeline of the data pipeline 324. In this case, the data to be transmitted is in parallel because the data signals are received through the plurality of CDQ pins 323. The mux and demux 344 converts the parallel data received from the data pipeline 324 into serial data in synchronization with the PLL 360. The data signal converted into serial data by the mux and demux 344 is transferred to the DRAM 200 through the XDQ pin 343. The DRAM 200 stores data in accordance with the transmitted serial data signal. This completes the write operation.

On the contrary, suppose the FPGA 100 wants to read a DRAM 200. The FPGA 100 generates a command signal for activating a read operation to the DRAM 200. The command signal generated from the FPGA 100 is transmitted to the DRAM 200 through the sustain device. The DRAM 200 is activated to enable a read operation by the transferred command signal. The DRAM 200 reads data, generates a data signal, and delivers the data signal to the XDQ pin 345. The data signal transmitted to the XDQ pin 345 is a high frequency serial signal. The mux and demux 344 convert the serial data signal received from the XDQ pin 345 into a parallel signal. Parallel data converted by the mux and demux 344 passes through the Read pipeline of the data pipeline 324. The data signal passing through the lead pipeline of the data pipeline 324 is transmitted to the FPGA 100 through the CDQ pin 323. This completes the reading process.

The data lines shown in FIG. 2 can be expanded to one or more.

3 is a timing diagram when a command is issued at no intervals in the Sustain system according to the present invention. Referring to Figures 2 and 3, the SUDES system receives a 200 Mbps command packet from the FPGA 100 to the CRQ pin 321, and then sends an 800 Mbps command to the DRAM 200 through the XRQ pin 343. Convert the packet and deliver it.

The worst timing condition for the instruction packet is when each instruction is attached gapless. Referring to FIG. 3, the operation will be described below. The write command packet W1 is simultaneously received from the CRQ pin 323 together with the activation command packet A of the DRAM 200. The Serdes system receives the received command packets A, W1, W2 and converts them into serial command packets ACT, WR1, WR2. The command packets ACT, WR1 and WR2 in serial form are delivered to the DRAM 200. The DRAM 200 is activated by the command packets ACT, WR1, and WR2. The CDQ pin 323 receives data packets D1 and D2 to be stored. The input data packet is a parallel data packet. The sudes system converts the received parallel data packet into a serial data packet in synchronization with the PLL 360. The converted serial data packets DA1 and DA2 are transferred to the DRAM 200. The DRAM 200 stores data according to serial data packets received. Referring to FIG. 3, the sustain system according to the present invention obtains an output without restriction even if the instruction packet is delivered at no interval.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, the Sustain system according to the present invention includes a pipeline for transmitting and receiving a signal and a serial / parallel signal converter, so that even if a plurality of command packets are transmitted at no interval, the size of the semiconductor integrated circuit is not overhead.

Claims (10)

Semiconductor memory devices; A controller that controls transmission and reception of signals with the semiconductor memory device; A pipeline for transmitting signals transmitted and received by the controller in parallel; The parallel signal transmitted from the pipeline is converted into a serial signal in response to a control signal and transmitted to the semiconductor memory device, or the serial signal transmitted from the semiconductor memory device is converted into a parallel signal in response to a control signal to the pipeline. A serial-to-parallel signal converter for transmitting; And A sused system including a control signal generation circuit for generating the control signal. The method of claim 1, The suede system, characterized in that the semiconductor memory device is DRAM The method of claim 1, And the semiconductor memory device operates at a higher frequency than the controller. The method of claim 1, The controller is a sustained system, characterized in that the field programmable gate array (FPGA). The method of claim 1, And a signal for transmitting and receiving is a data signal and a command signal. The method of claim 5, The pipeline is configured to process the data signal and each pipeline to process the command signal. The method of claim 1, The serial-to-parallel signal converter is a mux and a demux. The method of claim 1, And the control signal generation circuit is a synchronization circuit. The method of claim 8, The synchronization circuit is a PLL (Phase Locked Loop). The method of claim 8, The synchronization circuit is a DLL (Delay Locked Loop).

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