KR100680501B1 - Radio frequency identification system of dual phase locked loop type - Google Patents

Abstract

A dual PLL(Phase Locked Loop) type RFID(Radio Frequency IDentification) system is provided to minimize interference among RFID readers by using a channel after checking whether the other RFID reader occupies the channel by using a line discriminated into each PLL when the entire frequency band is unfit for an FHSS(Frequency Hopping Spread Spectrum) mode. The first and second PLLs(192,194) respectively generate the first and second reference frequency signal. An RF receiver(120) processes an RFID reception signal with the first reference frequency signal. An RF transmitter(140) processes an RFID transmission signal with the first reference frequency signal. A signal coupler(170) couples the reception signals of a specific band by connecting to an input terminal of the RF receiver. A signal level detector(180) converts the coupled signal by using the second reference frequency signal and checks a power level of the converted signal. A controller(160) moves the band of the reference frequency signal by applying control voltage to the first and second PLLs if the power level received from the signal level detector is over a predetermined value.

Description

Radio Frequency IDentification system of dual Phase Locked Loop type

1 is a block diagram schematically showing the overall components of a dual phase synchronous RFID system according to an embodiment of the present invention;

FIG. 2 is a block diagram schematically illustrating a form in which components of a first phase synchronizer circuit and a second phase synchronizer circuit are connected in a dual phase synchronization circuit RFID system according to an exemplary embodiment of the present invention; FIG.

3A and 3B are diagrams illustrating two forms of implementing a signal coupling unit included in a dual phase synchronous RFID system according to an embodiment of the present invention.

Figure 4 is a block diagram schematically showing the components of the signal level detection unit of the dual phase synchronization circuit RFID system according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

100: dual phase synchronous RFID system

105, 110: antenna 120: RF receiver

130: baseband receiver 140: RF transmitter

150: baseband transmitter 160: controller

170: signal coupling unit 180: signal level detection unit

190: phase synchronization circuit unit 192: first phase synchronization circuit

194: second phase synchronizing circuit 192a, 194a, 192f, 194f: divider

192b, 194b: frequency detector 192c, 194c: charge pump

192d, 194d: loop filter 192e, 194e: VCO

196: TCXO

The present invention relates to an RFID system.

Currently, ubiquitous network technology has attracted the attention of many people, ubiquitous network technology means a technology that allows to naturally connect to various networks regardless of time and place.

As the next generation technology of the ubiquitous network technology, RFID technology may be cited. Among them, RFID technology introduced in commerce is representative.

In general, a commercial RFID system consists of an RFID tag attached to a product and embedded with details, an RFID reader that reads information of the RFID tag using RF communication, and the RFID tag attached to the product is located at which the RFID reader is located. Since information is transmitted through RF communication through the region, it provides a foundation for efficiently managing logistics / distribution such as distribution, assembly, price change, and sales of goods.

On the other hand, the conventional RFID reader is generally implemented by envelope detection using an Amplitude Shift Keying (ASK) modulation scheme. According to the conventional design scheme, the data recognition rate is lowered due to a lower bit error rate.

Since RFID readers target tags moving at high speeds, the radio wave environment is severely changed, and the reception signal changes greatly according to the external environment changes. In particular, the frequency interference between RFID readers greatly affects the recognition rate of RFID tags. Gives.

In order to minimize the influence of the frequency interference phenomenon, a frequency hopping method is used, and a representative hopping method may be FHSS (Frequency-Hopping Spread Spectrum).

Unlike the Direct Sequence Spread Spectrum (DSSS) method, which operates at 12dB SNR using phase shift keying (PSK) phase modulation technology and uses 15 overlapping channels, the FHSS method uses 23 independent channels and spans all channels. It randomly leaps channels by "Random Hopping Sequence" and transmits and receives data.

However, in the FHSS scheme, if the hopped channel is used by another RFID reader, it is difficult to completely exclude the inter-reader interference because a frequency collision occurs.

RFID frequencies range from low frequency (LF) such as 125 KHz and 135 KHz, high frequency (HF) such as 13.56 MHz, ultra high frequency (UHF) in the 433 MHz and 900 MHz bands, and microwave in the 2.45 GHz band. The frequency of the 900 MHz band is expected to be widely used due to the advantages of being able to make it small, small, long recognition distance, and distinguishing multiple tags.

In particular, since the frequency of the 900 MHz band has a narrow overall frequency bandwidth and a small number of carriers, even if the FHSS scheme is employed, the effect may be further reduced.

According to the present invention, when the entire frequency required band is not suitable for the FHSS method in using the frequency hopping method, the present invention provides a plurality of phase synchronization circuits and uses different lines for each phase synchronization circuit to determine whether another RFID reader occupies a predetermined channel. After examining whether the channel is used, an RFID system that minimizes interference between RFID readers is provided.

A dual phase synchronous circuit RFID system according to the present invention comprises: a first phase synchronous circuit unit for generating a first reference frequency signal; A second phase synchronization circuit unit for generating a second reference frequency signal; A reception processing unit processing an RFID reception signal using the first reference frequency signal; A transmission processor which processes the RFID transmission signal by using the first reference frequency signal; A signal combiner coupled to an input of the receive processor to couple a received signal of a predetermined band; And a signal level detecting unit converting the coupled signal by using the second reference frequency signal and determining a power level of the converted signal.

In addition, the dual phase synchronization circuit RFID system according to the present invention receives the power level from the signal level detection unit, and if the power level is a predetermined value or more, the first phase synchronization circuit unit and the second phase synchronization circuit unit is controlled. A control unit for shifting the band of the reference frequency signal by applying a voltage is included.

In addition, the signal level detection unit of the dual phase synchronization circuit RFID system according to the present invention is further provided with an attenuator on the input end side, and includes a filter on the output end side.

In addition, the first phase synchronization circuit unit and the second phase synchronization circuit unit of the dual phase synchronization circuit RFID system according to the present invention includes a divider for shifting a band of a reference frequency signal according to the control voltage.

Hereinafter, a dual phase synchronization circuit type RFID system according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. An RFID system according to an embodiment of the present invention is an RFID reader.

1 is a block diagram schematically showing the overall components of a dual phase synchronous RFID system 100 according to an embodiment of the present invention.

Referring to FIG. 1, a dual phase synchronization circuit type RFID system 100 according to an exemplary embodiment of the present invention has a large first antenna 105, an RF receiver 120, a baseband receiver 130, and a second antenna 110. The RF transmitter 140 includes a baseband transmitter 150, a controller 160, a signal combiner 170, a signal level detector 180, and a phase synchronization circuit 190.

First, referring to the components for processing the transmission signal, the controller 160 is provided with a communication protocol to control wireless communication with the RFID tag, and periodically sends an information request signal to determine the location of the RFID tag. .

In addition, the controller 160 analyzes the code of the tag identification information received from the RFID tag. At this time, the data format is converted and filtering is performed to extract necessary information.

The control unit 160 may be a field programmable gate array (FPGA) circuit or a digital signal processing (DSP) circuit, and the FPGA circuit may be programmed as needed to implement a function of an RFID reader receiver out of a chip production process. It means a gate array circuit (logical integrated circuit) which can be added.

In addition, a DSP (Digital Signal Processing) circuit is a circuit that performs algebraic processing on digital data obtained by A / D conversion of an analog signal and filters or performs signal processing such as spectrum analysis.

When the controller 160 processes a digital signal such as an information request signal, an I-phase (Q) signal and a quadrature-phase (Q) signal, which are digital signal states, may be connected to a first digital to analog converter (1DA) 155a and a first signal. It is converted into an analog signal through 2DA 155b, and amplified into an intermediate frequency signal of a predetermined size through a third band amplifier 154a and a fourth BA 154b.

The first IF filter 153a and the second IF filter 153b respectively filter the I signal and the Q signal, and at this time, the signal of the noise component introduced during the analog signal conversion and amplification process is filtered.

The third mixer 152a and the fourth mixer 152b receive a reference frequency signal from a second local generator (LO) 156 connected to the first phase synchronization circuit 192, and the filtered I The signal and the Q signal are mixed with the reference frequency signal and converted into an RF signal.

The signal synthesizing unit 151 combines the I signal and the Q signal converted into the RF signal to generate a single RF signal, and the RF transmission signal is a second band pass filter (which may be provided as a saw filter) ( 144 and a power transmitter (PA) 142, and the second antenna 110 and the transmission through the 110.

On the other hand, with respect to the components for processing the received signal, the signal is received from the RFID tag through the first antenna 105, RF consisting of a low noise amplifier (LNA) 122 and the first band pass filter 124 The receiver 120 filters the unwanted component signals after low noise amplifying the signal received through the first antenna 105.

Here, the signal combiner 170 is connected between the LNA 122 and the first band pass filter 124, and the signal combiner 170 sequentially rotates the signal level detector 180 and the phase synchronization circuit 190. ), Which will be described later.

The balun circuit 131 separates the RF received signal transmitted from the RF receiver 120 into an I signal and a Q signal. Here, the term "balun" refers to a circuit for converting a balanced signal into an unbalanced signal (or vice versa) as "Balance-Unbalance".

The balun circuit 131 has an output terminal connected to the first mixer 132a and the second mixer 132b, respectively, when there is an I signal and a Q signal using the same transmission band. Driving (a kind of signal conversion) to separate the I or Q signal.

The balun circuit 131 may be implemented through a line combination, a lumped element, a resonant waveguide method, or the like.

The first mixer 132a and the second mixer 132b receive a reference frequency signal from the first local generator 136 connected to the first phase synchronization circuit 192, and synthesize the separated I and Q signals. To generate an intermediate frequency signal.

The I and Q signals generated as the intermediate frequency signal are removed through the first low pass filter (LPF) 133a and the second LPF 133b, respectively, to remove the noise components mixed in the mixing process, and the first BA 134a and the second BA. Intermediate frequency amplification is performed via 134b.

The intermediate frequency amplified I and Q signals are converted into digital signals at the first AD (Analog to Digital converter) 135a and the second AD 135b, respectively, and the controller 160 receives the signals and interprets the signals. Process on

At this time, the phase synchronizing circuit 190 is a dual type, and includes a first phase synchronizing circuit 192 and a second phase synchronizing circuit 194. The first local generator 136 and the base of the base band receiving unit 130 are provided. The second local generators 156 of the band transmitter 150 all receive a reference frequency signal from the first phase synchronizer circuit 192.

The signal combiner 170 couples a frequency signal of an adjacent band that may cause interference to an RF received signal, and transmits the signal to the signal level detector 180. The signal level detector 180 converts the signal into an intermediate frequency signal. Convert to measure power value.

The second phase synchronizer circuit 194 provides a reference frequency signal for use by the signal level detecting unit 180 to convert the coupled signal into an intermediate frequency signal, wherein the reference frequency in the range of about 900 MHz to 930 MHz is provided. Supply the signal.

The signal level detecting unit 180 transmits the measured power value to the control unit 160, and when the control unit 160 determines that the power value is higher than the reference value set in the memory, Judging from the frequency and interference.

As it is determined that an interference phenomenon has occurred, the controller 160 transmits a control signal to the phase synchronization circuit unit 190, and the phase synchronization circuit unit 190 changes the transmission / reception band by shifting the band of the reference frequency signal. do.

Accordingly, RFID readers can increase frequency utilization efficiency by checking for mutual interference and using or avoiding corresponding channels to use other channels.

2 schematically illustrates a form in which the components of the first phase synchronizer circuit 192 and the second phase synchronizer circuit 194 are connected to each other in the dual phase synchronous RFID system 100 according to the embodiment of the present invention. It is a block diagram.

Referring to FIG. 2, the components of the first phase synchronizer circuit 192 and the second phase synchronizer circuit 194 are shown, and the first phase synchronizer circuit 192 and the second phase synchronizer circuit 194 are basically shown. Since the configuration and operation are the same, a description will be made using the first phase synchronization circuit 192 as an example.

The first phase synchronization circuit 192 may include a first divider 192a, a first frequency detector 192b, a first charge pump 192c, a first loop filter 192d, and a first voltage controlled oscillator (VCO) ( 192e) and a second divider 192f.

TCXO (Temperature Compensated X-tal Oscillator) 196 is a circuit having a crystal oscillator and controlling the frequency disturbance according to the temperature change. The TCXO (Temperature Compensated X-tal Oscillator) 196 is a first frequency divider 192a. To provide.

The first divider 192a reduces the oscillation frequency signal by a predetermined ratio according to the control signal of the controller 160 to shift the band of the final reference frequency signal output from the first phase synchronizer circuit 192. .

The first frequency detector 192b detects a reference frequency signal output from the first VCO 192e and compares it with an oscillation frequency signal transmitted from the TCXO 196.

In general, the reference frequency signal is a high frequency (eg, frequency signal in "㎓") signal, and the oscillation frequency signal is a relatively low frequency signal (eg, frequency signal in "MHz" unit) compared to the reference frequency signal.

Accordingly, the second divider 192f converts the reference frequency signal to a relatively low frequency in order to convert the reference frequency signal output from the first VCO 192e into a size comparable with the oscillation frequency signal.

For example, if the TCXO 196 provides an oscillation frequency signal of 100 MHz and the first VCO 192e provides a reference frequency signal of 1.1 GHz, the second divider 192f receives 1/10 of the reference frequency signal. Switch to the size of.

The first frequency detector 192b compares the frequency of the oscillation frequency signal and the converted reference frequency signal, and transfers a control signal corresponding to the frequency difference to the first charge pump 192c and controls the first charge pump 192c. Adjust the current value according to the signal.

The charge pump is an electronic circuit that supplies or absorbs a specific amount of charge according to a control signal. When the voltage of the reference frequency signal is larger than the oscillation frequency signal, the charge pump transfers the specific amount of charge to the first loop filter 192d. If the voltage of the reference frequency signal is smaller than that of the oscillation frequency signal, the branch circuit draws a certain amount of charge from the first loop filter 192d.

In addition, the first loop filter 192d may filter a signal of a noise component flowing on the first charge pump 192c. For example, a second filter including a plurality of capacitors and resistors may be used.

In the capacitor connected in parallel with the resistor, the amount of charge and push of the charge pump is adjusted to adjust the voltage of the first VCO 192e and to reduce the spurious characteristics generated on the phase synchronization circuit.

The first VCO 192e includes a resonator, a power supply (not shown), and the like, and resonates a reference frequency signal without shaking in accordance with a control signal passed through the first loop filter 192d.

Thus, for example, the reference frequency signal is minutely flowed due to external environmental change factors such as temperature to become unstable, and distortion of the intermediate frequency signal can be prevented.

As described above, the third divider 194a, the second frequency detector 194b, the second charge pump 194c, the second loop filter 194d, and the second VCO 194e of the second phase synchronizer circuit 194. The fourth divider 194f operates in the same manner, and the first phase synchronizer circuit 192 and the second phase synchronizer circuit 194 receive an oscillation frequency signal from one TCXO 196.

3A and 3B illustrate two forms of the signal coupling unit 170 implemented in the dual phase synchronous RFID system 100 according to an embodiment of the present invention.

Referring to FIG. 3A, the signal combiner 170 is implemented with one inductor 172 and two capacitors 174 and 176, which are filter type structures, and are predetermined according to the values of the respective lumped elements. The frequency signal of the band may be resonated and coupled to the signal level detector 180.

Referring to FIG. 3B, the signal combiner 170 includes two transmission lines located in close proximity, and the upper transmission line (hereinafter, referred to as a “first transmission line”) is an LNA 122. ) And a first band pass filter 124, both ends function as input ports (a) and pass (b), respectively.

That is, the signal output from the LNA 122 flows through the first transmission line through the input port (a) and is then input to the first band pass filter 124 as it is through the through port (b).

At this time, a part of the power of the signal flowing through the first transmission line is coupled to the lower transmission line (hereinafter referred to as "second transmission line") due to the interference effect of the electromagnetic field, and the coupled signal is output port (c). It is transmitted to the signal level detecting unit 180 through.

The signal combiner 170 implemented in the form of a transmission line is used for signal detection / extraction, not for power distribution, and the remaining ports of the second transmission line, that is, the isolation port d, are connected to the ground terminal through the resistor 178. Connected.

This is connected to the ground terminal through a resistance of about 50 Ω in accordance with the impedance value of the second transmission line, and although it is not used as an actual input / output port, it is assumed that leakage power is reflected and returned. It is to be consumed as heat through (178). This isolation port allows for power stabilization on the combiner.

4 is a block diagram schematically illustrating the components of the signal level detecting unit 180 of the dual phase synchronous RFID system 100 according to the embodiment of the present invention.

Referring to FIG. 4, the signal level detector 180 includes a low pass filter 184, a log amplifier 183, a mixer 182, an attenuator 181, and the attenuator 181. The output terminal of the unit 170 and the low pass filter 184 are connected to the controller 160.

The attenuator 181 attenuates when the signal coupled through the signal coupling unit 170 has a larger power value than necessary, and the mixer 182 a reference frequency provided from the second phase synchronizer circuit 194. The signal and the coupled signal are mixed and converted into an intermediate frequency signal.

The log amplifier 183 converts the intermediate frequency signal into a DC signal, and the low pass filter 184 removes a signal of an RF component mixed with the DC signal.

Accordingly, the controller 160 receives the DC signal and determines the power level of the signal (causing the interference effect) adjacent to the currently received signal to determine whether the interference phenomenon or the degree of the interference phenomenon.

As described above, the controller 160, which grasps the degree of the interference phenomenon, applies a control signal to the phase synchronization circuit unit 190, and the first divider 192a and the third divider 194a of the phase synchronization circuit unit 190. Divides the oscillation frequency signal and shifts the band of the finally output reference frequency signal.

Although the present invention has been described above with reference to the embodiments, these are merely examples and are not intended to limit the present invention. It will be appreciated that various modifications and applications are not illustrated. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

According to the dual phase synchronous RFID system according to the present invention, before performing a leap on a shared frequency, the dual phase synchronous circuit determines whether or not the corresponding frequency band is used, and the frequency band is not occupied. In this case, it is possible to stably maintain communication without interfering between readers by setting a communication channel.

In addition, according to the present invention, by using the dual phase synchronization circuit can implement the "frequency check / hop" function in the most simplified circuit form, and can maximize the frequency hopping effect even in the RFID band with a narrow frequency bandwidth and a small number of carriers It works.

Claims (10)

A first phase synchronization circuit unit generating a first reference frequency signal; A second phase synchronization circuit unit for generating a second reference frequency signal; A reception processing unit processing an RFID reception signal using the first reference frequency signal; A transmission processor which processes the RFID transmission signal by using the first reference frequency signal; A signal combiner coupled to an input of the receive processor to couple a received signal of a predetermined band; And And a signal level sensing unit for converting the coupled signal using the second reference frequency signal and determining a power level of the converted signal. The method of claim 1, When the power level is received from the signal level detection unit and the power level is equal to or greater than a predetermined value, a controller for applying a control voltage to the first phase synchronization circuit unit and the second phase synchronization circuit unit to move a band of a reference frequency signal. Dual phase synchronization circuit type RFID system, characterized in that it is included. The method of claim 1, wherein the second phase synchronization circuit portion Dual phase synchronization circuit type RFID system, characterized in that for generating a second reference frequency signal in the 900 MHz to 930 MHz band. The method of claim 1, wherein the signal coupling unit Dual phase synchronization circuit type RFID system, characterized in that provided as a line coupler or coupler element of the transmission line type. The method of claim 1, wherein the signal level detecting unit Dual phase synchronization circuit type RFID system comprising an attenuator on the input side. The method of claim 1, wherein the signal level detecting unit Dual phase synchronization circuit type RFID system, characterized in that the filter is included on the output side. 3. The circuit of claim 2, wherein the first phase synchronizing circuit part and the second phase synchronizing circuit part And a divider for shifting a band of a reference frequency signal according to the control voltage. The method of claim 1, wherein the phase synchronization circuit unit A first divider for changing a frequency band of the oscillation frequency signal transmitted from the TCXO; A frequency detector for generating a control signal by comparing a finally output reference frequency signal with the band-changed oscillation frequency signal; A charge pump supplying a specific amount of charge in accordance with the control signal; A loop filter for filtering the signal supplied from the charge pump; A VCO resonating the reference frequency signal according to the filtered signal; And And a second divider for dividing the reference frequency signal at a predetermined ratio and transferring the reference frequency signal to the frequency detector. The method of claim 1, wherein the signal coupling unit Dual phase synchronization circuit type RFID system, characterized in that the combination of the passive elements of the inductor and capacitor. The method of claim 1, wherein the signal level detecting unit An attenuator for adjusting the power level of the coupling signal transmitted from the signal coupling unit; A mixer for mixing the reference frequency signal and the scaled cuffing signal; A log amplifier converting the mixed signal into a DC signal; And And a filter for removing a signal of a noise component mixed in the DC signal.

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