KR100676342B1 - Utilizing atomic layer deposition for programmable device - Google Patents

Abstract

In one aspect, an apparatus is provided for setting and reprogramming a state of programmable devices. In one aspect, an opening 220 is formed through the dielectric to expose the contact, which contact 170 is formed on the substrate 100. Electrode 230 is conformally deposited on the walls of dielectric 210 using atomic layer deposition (ALD). Programmable material 404 is formed on the electrode, and conductor 410 is formed for the programmable material. In one aspect, the barrier utilizes ALD to conformally deposit between electrode 230 and programmable material 404.

Phase Change Memory, Conformal Deposit, ALD, Programmable Materials

Description

UTILIZING ATOMIC LAYER DEPOSITION FOR PROGRAMMABLE DEVICE}

The present invention relates to a programmable device comprising phase change memory devices that can be programmed by changing the state of a phase change material.

Typical computers, or computer related devices, include physical memory, commonly referred to as main memory or random access memory (RAM). In general, RAM is memory used for computer programs, and read-only memory (ROM) is, for example, memory used to store programs that boot a computer and perform diagnostics. Typical memory applications include dynamic random access memory (DRAM), static random access memory (SRAM), erase and programmable read only memory (EPROM), electrical erase and programmable read only memory (EEPROM).

Solid state memory devices typically employ microelectronic circuit elements (eg, 1 to 4 transistors per bit) for each memory bit in memory applications. Since one or more electronic circuit elements are required for each memory bit, these devices can consume a substantial amount of chip real estate to store one bit of information, which limits the density of the memory chip. . The primary nonvolatile memory elements of such devices, such as EEPROMs, typically limit reprogrammability and float gate field effect transistors that hold charge at the gate of the field effect transistor to store each memory bit. Adopt. Memory devices of this type are also relatively slow to program.

Phase change memory devices use phase change materials in electronic memory applications, ie materials that can be electrically switched between alternate amorphous and alternate crystalline states. One type of memory device originally developed by Energy Conversion Devices, Inc. of Troy, Mich., Is in a single application, between an alternate amorphous structural state and an alternate crystalline local order, or across an entire range between fully amorphous and fully crystalline states. A local order uses a phase change material that can be electrically switched between different detectable states. Typical materials suitable for this application include those utilizing a variety of chalcogenide devices. Such electrical memory devices typically do not use a field effect transistor device as a memory memory element, but in an electrical context include an integral body of thin film chalcogenide material. As a result, only a very small chip area is required to store one bit of information, resulting in a uniquely high density memory chip. A phase change material, when set to any one of a crystalline, semi-crystalline, amorphous, or semi-crystalline state exhibiting a resistance value, the resistance value determines the physical state of the material (e.g., crystalline or amorphous). It also has true non-volatility in that it remains until it is reprogrammed. Thus, phase change memory materials lead to significant improvements in nonvolatile memory.

One feature common to solid state and phase change memory devices is that they consume significant amounts of power, especially when setting up or reprogramming memory elements. Power consumption issues are particularly important in portable devices that rely on power cells (eg batteries). It is desirable to reduce the power consumption of the memory device.

Another feature common to solid state and phase change memory devices is that the reprogrammable cycle life to / from amorphous and crystalline states is limited. Furthermore, over time, phase change materials may fail to reliably reprogram to / from amorphous and crystalline states. It is desirable to increase the programmable cycle life of phase change memory materials.

[Brief Description of Drawings]

Advantages of the present invention will become apparent upon reading the following detailed description and referring to the drawings.

1 is a schematic diagram illustrating an embodiment of a memory element array.

FIG. 2 schematically illustrates a cross-sectional planar side view of a portion of a semiconductor substrate having dielectric trenches formed therein and defining the z-direction thickness of the memory cell in accordance with one embodiment of forming a memory element on a substrate. FIG.

FIG. 3 shows the structure after introduction of the dopant for forming the isolation device of the memory element for the same cross section as in FIG. 2 in the structure of FIG.

4 illustrates a structure in which trenches are formed in the structure of FIG. 3.

5 is a schematic plan view of the structure of FIG.

FIG. 6 is a cross-sectional view of the structure of FIG. 4 after contact formation. FIG.

FIG. 7 shows the structure after forming the masking material and the dielectric material for the same cross section as in FIG. 6 in the structure of FIG.

FIG. 8 is a view showing a structure after exposing a contact by forming an opening through a dielectric in the same cross section as in FIG. 7 in the structure of FIG.

FIG. 9 illustrates a structure in which electrode monolayers are generated on a dielectric layer and a contact using ALD for the same cross-section as in FIG. 8 in the structure of FIG. 8; FIG.

FIG. 10 shows the structure after forming an electrode on the dielectric and the contact with respect to the same cross section as in FIG. 9 in the structure of FIG. 9; FIG.

FIG. 11 shows the structure after forming a dielectric in the opening and removing the horizontal portion of the electrode for the same cross section as in FIG. 10 in the structure of FIG. 10; FIG.

FIG. 12 illustrates a structure after conformally forming a barrier on an electrode using ALD for the same cross-section as in FIG. 11 in the structure of FIG.

FIG. 13 illustrates the structure after forming and patterning a programmable material, barrier, and conductor for the same cross section as in FIG. 12 in the structure of FIG.

FIG. 14 shows the structure after forming a dielectric body on a conductor, forming a via, and forming a signal line on the dielectric for the same cross section as in FIG. 13 in the structure of FIG. 13; FIG.

FIG. 15 illustrates a method of forming a memory device having a structure similar to that described by FIG.

FIG. 16 illustrates one system embodiment including a memory having a structure similar to that described by FIG. 14.

Example embodiments are described with reference to specific configurations. Those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the appended claims. Furthermore, well-known elements, devices, components, circuits, processing steps and the like will not be described in detail in order not to obscure the gist of the present invention.

A memory device is described that utilizes programmable materials to determine the state of its memory elements and reprograms to amorphous and crystalline states. The described memory device and method provide improved device reliability, improved programmable cycle life, and reduced power consumption compared to conventional devices. In addition, in one embodiment, the apparatus is manufacturable utilizing conventional process tools and facilities.

In one embodiment, atomic layer deposition (ALD) provides an advantage in electrode device configuration, including a reduction in programming current required for reset, set, and read operations in the memory device. Advantages of electrode device construction are obtained by utilizing ALD or atomic layer chemical vapor deposition (ALCVD) instead of chemical vapor deposition (CVD), including the ability to deposit very thin and conformal films. The film thickness is controlled by the number of deposition steps applied with a resolution defined by the thickness of one single layer. In addition, ALD deposition provides a wide range of film uniformity and accuracy.

1 is a schematic diagram of an embodiment of a memory array comprised of multiple memory elements presented and formed in accordance with the context of the description provided herein. In this example, the memory array 5 circuit includes an xy grating in which the memory elements 30 are electrically connected in series with the isolation devices 25 on a portion of the chip. In one embodiment, address lines 10 (e.g., columns) and 20 (e.g., rows) are connected to the external addressing circuit in a conventional manner. One purpose of an xy grid array in which memory elements are combined with isolation devices is to achieve that each discrete memory element is read and written without interfering with information stored in adjacent or distant memory elements in the array.

Memory arrays, such as the memory device 5 of FIG. 1, may be formed in portions of the substrate, including the entire portion of the substrate. Typical substrates include semiconductor substrates such as silicon substrates. As part of the infrastructure, other substrates are also suitable, including, but not limited to, substrates having ceramic, organic, or glass materials. In the case of a silicon semiconductor substrate, the memory array 5 may be fabricated at the wafer level on the substrate area, after which the wafer is divided into discrete dies or chips via singulation, some or all of the dies or chips. Has a memory array formed thereon. Additional addressing circuits (eg, decoders, etc.) may be formed as known to those skilled in the art.

2-14 illustrate a fabrication embodiment of the memory device 15 of the representative FIG. 2 illustrates a portion of substrate 100, for example a semiconductor (eg silicon) substrate. In this example, a P-type dopant, such as boron, is introduced to portion 110. In one example, a suitable concentration of P-type dopant has a size on the order of about 5 × 10 ¹⁹ to 1 × 10 ²⁰ atoms per cubic centimeter (atoms / cm 3) such that portion 110 of substrate 100 is converted to P ⁺⁺ . To be displayed. Overlaid on portion 110 of substrate 100 is portion 120 of P-type epitaxial silicon. In one example, the dopant concentration is about 10 ¹⁶ to 10 ¹⁷ atoms / cm 3.

2 illustrates a hollow trench isolation (STI) structure 130 formed in the epitaxial portion 120 of the substrate 100. As will be apparent from the discussion below, the STI structure 130 is a feature and is used at this point to define the z-direction thickness of the memory cell in such a way that only the z-direction thickness of the memory cell is defined. In one embodiment, the z direction regions 135A and 135B of the memory cell are patterned as strips whose x direction dimension is greater than the z direction dimension. As another feature, the STI structures 130 are used to separate individual memory elements from each other as well as from associated circuit elements (eg, transistor devices) formed in and on the substrate. State-of-the-art photolithography techniques used to pattern STI structures that define the z-direction thickness of the memory cell regions 135A and 135B can yield feature sizes (z-direction thickness) as small as 0.18 microns (μm). .

3 shows the structure of FIG. 2 after a further fabrication process in memory cell regions 135A and 135B. Within each memory cell region (strip), a signal line material 140 is laid over the epitaxial portion 120 of the substrate 100. In one example, signal line material 140 is N-type doped polysilicon (eg, N ⁺ silicon) formed by introducing phosphorous or arsenic at a concentration of about 10 ¹⁸ to 10 ¹⁹ atoms / cm 3, for example. In this example, signal line material 140 functions as an address line, a row line (eg, row line 20 of FIG. 1). A separating device (eg, separating device 25 of FIG. 1) is laid over the signal line material. In one example, the isolation device comprises an N-type silicon portion 150 (eg, having a dopant concentration of about 10 ¹⁴ to 10 ¹⁸ atoms / cm 3) and a P-type silicon portion 160 (eg, about 10 ¹⁹ to 10 ²⁰ PN diode having a dopant concentration of about atoms / cm 3). Although a PN diode is shown, it should be appreciated that other isolation structures may similarly be suitable. Such devices include, but are not limited to, metal oxide semiconductor (MOS) devices.

FIG. 4 is the structure of FIG. 3 viewed from the xy plane after forming the trenches 190 in the epitaxial portion 120 of the substrate 100. Trenchs 190 are, in this example, formed perpendicular to STI structures 130. Trenchs 190 define the x direction thickness of the memory cell. According to current photolithography techniques, the suitable feature size for the x direction thickness is as small as 0.25 μm. FIG. 4 also has a z-direction thickness defined by STI structures 130 and an x-direction thickness defined by trenches 190, and memory cells 145A and 145B separated by trenches 190. ) Is shown. Defining the x direction thickness relates, in one embodiment, to etching the conductor or signal line 140 of the memory line stack to define memory cells 145A and 145B of the memory cell region 135A. . When etching, the etching proceeds through the memory line stack to a portion of the conductor or signal line 140 in this example. At this point a timed etch can be utilized to stop the etch. After patterning, the N-type dopant is introduced into the base of each trench 190 to have a pocket 200 (N ⁺ ) having a dopant concentration of about 10 ¹⁸ to 10 ²⁰ atoms / cm 3 between the memory cells 145A and 145B. Regions).

Following introduction of the pockets 200, a dielectric material, such as silicon dioxide, is introduced into the trenches 190 to form the STI structures 132. The upper surface (as shown) can then be planarized, for example by CMP. FIG. 5 shows an xz perspective view of the structure of FIG. 4 in which memory cells (eg, memory cells 145A and 145B) are separated by STI structures 130 and 132.

FIG. 6 illustrates the structure of FIG. 4 in which a refractory metal silicide material, such as cobalt silicide (CoSi ₂ ), is formed in the p-type silicon portion 160 to define the contact 170 in this example. The contact 170, in one aspect, functions as a low resistance material when manufacturing peripheral circuits (eg, addressing circuits) in a circuit structure on a chip.

7 shows the structure of FIG. 6 after masking material 180 is introduced. As will become more apparent later, the masking material 180 functions in some sense as an etch stop layer for the subsequent etching process. In one embodiment, a suitable material for masking material 180 is a dielectric material, such as silicon nitride (Si ₃ N ₄ ).

FIG. 7 illustrates a dielectric material 210 introduced to have a thickness on the order of 100 angstroms to 50,000 angstroms sufficient to blanket the memory cells 145A and 145B over this structure. In one embodiment, the dielectric material 210 is SiO ₂ . In another embodiment, dielectric material 210 has its reduced thermal conductivity κ such that it preferably has a thermal conductivity less than κ _{SiO 2} , more preferably 1/3 to 1/10 smaller than κ _{SiO 2.} Selected material. As a general practice, SiO ₂ and Si ₃ N ₄ Is assumed to have a κ value of 1.0. Thus, SiO ₂ In addition, suitable materials for dielectric material 210 include materials having a κ value of less than 1.0. Certain high temperature polymers with κ values less than 1.0 include carbide materials, aerogels, Xerogels (having a κ value of about 0.1), and derivatives thereof.

FIG. 8 illustrates the structure of FIG. 7 after forming the openings 220 through dielectric 210 and masking material 180 to expose contact 170, for the same cross-section as FIG. 7. The formation of the openings 220 selectively etchant that etches the dielectric material 210 and the masking material 180 but does not etch the contact 170 (eg, contact 170 functions as an etch stop layer). It can be accomplished by etching patterning with (s).

FIG. 9 illustrates a conformal formation of electrode material 230 utilizing ALD for the same cross section as in FIG. 8. The use of ALD introduces one reactant gas at a time. The first gas is chemisorbed onto the surface of dielectric 210, masking material 180, and contact 170 to form chemisorbed layer 230A. Excess gas is then removed and a second gas is introduced. This gas reacts with the chemical adsorption layer 230A to produce a single layer of deposited film 230B. Individual precursors are pulsed onto surfaces in a sequential manner without mixing precursors in the gaseous state. Each individual precursor reacts with the surface to form an atomic layer in such a way that one layer is formed at a time. ALD processes have their own limitations. That is, regardless of the number of molecules applied to the surface in the overdosing mode, the surface reaction occurs and ends in such a way that one or more layers are not deposited at a time. The thin films are dried by causing a gas to erupt in a short instant in the cycles. Conventional CVD processes typically operate above 500 ° C. and ALD is possible below 400 ° C., in keeping with the industry's tendency to lower temperatures.

  Thin films on the sidewalls define the x-axis dimension of the electrode (as will become more apparent in FIG. 11), which is an important dimension in terms of device performance. The x-axis dimension determines the programming current required for reset, set, and read operations. The smaller the x-axis dimension that can be repeatedly reproduced, the smaller the required value for the programming currents required to operate the device. This is due to the smaller volume of programmable material whose phase is changing and reduced heat loss.

In one embodiment, electrode material 230 (collectively 230A, 230B,..., 230N atomic layers) has a uniform film thickness and very thin thickness (relative to the x-axis dimension shown in FIG. 11), It becomes a conformal film. In one embodiment, electrode material 230 has an x-axis dimension on the order of 10 angstroms to 1000 angstroms. In one embodiment, the electrode material 230 is at least one of tungsten (W), tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TiSiN), and tantalum nitride (TaN). In one embodiment, electrode material 230 has a resistivity on the order of 0.001 to 0.05 micrometers centimeters.

10 illustrates the structure of FIG. 9 after conformal formation of electrode material 230 is complete. This introduction is in that the electrode material 230 is formed along the sidewalls and the base of the openings 220 in such a way that the electrode material 230 is in contact with the contact 170 (electrode material portions 230A, 230B, 230C). Shown). Separation of a single conductive path (such as electrode material 230A) may be obtained through the inclined introduction of the dopant (eg, angularly deviating from the electrode material 230B).

11 illustrates the structure after dielectric material 250 is introduced into openings 220. In one embodiment, dielectric material 250 is silicon dioxide (SiO ₂ ). In another embodiment, dielectric material 250 is the material having a smaller thermal conductivity than the thermal conductivity κ κ _SiO2 of SiO _2, preferably less than about one-third to one-tenth κ _SiO2. After introduction, the structure undergoes planarization to remove the horizontal component of the electrode material 230. Suitable planarization techniques include those known to those skilled in the art, such as chemical or chemical mechanical polishing (CMP).

FIG. 12 shows the structure after selective conformal formation of barrier 275 utilizing ALD, for the same cross section as in FIG. In one embodiment, electrode 230 is selectively etched, the ALD for barrier 275 is utilized to fill the etched area, and barrier 275 is then planarized.

FIG. 13 illustrates the structure after forming and patterning conductor 410, barrier 408, and programmable material 404, for the same cross-section as FIG. 12. This patterning can be obtained using conventional photolithography and etching techniques. In this example, this etching proceeds through portions of the programmable material 404, barrier 408, and conductor 410 to the removal of barrier 275, dielectric 210, and dielectric 250. . In one embodiment, programmable material 404 is a phase change material having a property whose physical state (eg, crystalline and amorphous states) can be changed by applying an amount of energy (eg, electrical energy, thermal energy). Chalcogenide materials having the general formula are known to be suitable for this purpose. In one embodiment, chalcogenide alloys suitable as programmable material 404 include at least one element from Group VI of the Periodic Table of Elements. In one embodiment, Ge ₂ Sb ₂ Te ₅ is utilized as the programmable material 404. Other chalcogenide alloys that can be used as the programmable material 404 include GaSb, InSb, InSe, Sb ₂ Te ₃ , GeTe, InSbTe, GaSeTe, SnSb ₂ Te ₄ , InSbGe, AgInSbTe, (GeSn) SbTe, GeSb (SeTe), and Te ₈₁ Ge ₁₅ Sb ₂ S ₂ .

Barrier 408 includes one of titanium (Ti) and titanium nitride (TiN), for example. The barrier 408, in one feature, functions to inhibit diffusion between the volume of the programmable material 404 and the second signal line material (eg, the second electrode 10) overlying the volume of the programmable material 404. Signal line material 410 is laid over barrier 408. In this example, signal line material 410 functions as an address line, a column line (eg, column line 10 of FIG. 1). The signal line material 410 is patterned to be generally orthogonal to the signal line material 140 in one embodiment (column lines are orthogonal to the row lines). Signal line material 410 is, for example, an aluminum material, such as an aluminum alloy. Methods for introduction and patterning of barrier 408 and signal line material 410 include techniques known to those skilled in the art.

FIG. 14 illustrates the structure of FIG. 13 after forming dielectric material 412 on conductor 410. Dielectric material 412 is, for example, SiO ₂ , or other suitable material formed on conductor 410 to electrically separate conductor 410. Following this formation, dielectric material 412 is planarized, and vias are formed in the portion of the structure through dielectric material 412, dielectric material 210, and dielectric material 180 to contact 170. The via is filled with a conductive material 340, such as tungsten (W), and a barrier material 350, such as a combination of titanium (Ti) and titanium nitride (TiN). Techniques for introducing the dielectric material 412, forming, filling, and planarizing conductive vias are known to those skilled in the art. The structure shown in FIG. 14 also shows an additional signal line material 414 formed and patterned to mirror that of the signal line material 140 (eg, low line) formed on the substrate 100. Mirror conductor line material 414 mirrors signal line material 140 and is coupled to signal line material 140 through conductive vias. By mirroring a doped semiconductor, such as N-type silicon, the mirror conductor line material 414, in one feature, reduces the resistance of the signal line material 140 in the memory array, such as the memory array 5 illustrated in FIG. Function to reduce. Suitable materials for the mirror conductor wire material 414 include aluminum materials, such as aluminum alloys.

FIG. 15 has described a method of forming a programmable memory device having a structure similar to that shown in FIG. 14 according to one embodiment.

Furthermore, as shown in FIG. 16, memory arrays such as memory device 5 (FIG. 1) having a structure similar to that described with reference to FIG. 14 and accompanying devices may be incorporated into a suitable system. Can be. In one embodiment, system 700 includes a microprocessor 704, an input / output (I / O) port 706, and a memory 702. Microprocessor 704, input / output (I / O) port 706, and memory 702 are connected by data bus 712, address bus 716, and control bus 714. Microprocessor 704 fetches instructions and read data from memory 702 by sending an address on address bus 716 and sending a memory read signal on control bus 714. The memory 702 outputs addressed instructions or data words on the data bus 712 to the microprocessor 704. The microprocessor 704 sends the address on the address bus 716, sends the data word on the data bus 712, and sends the memory write signal to the memory 702 on the control bus 714 to the memory 702. Fill in 702. I / O port 706 is utilized to couple to at least one of input device 708 and output device 710.

Having disclosed exemplary embodiments, changes and modifications may be made to the disclosed embodiments without departing from the spirit and scope of the invention as defined by the claims.

Claims (15)

Forming a dielectric on the contact, wherein the contact is formed on the substrate; Forming an opening through the dielectric to expose the contact; Conformally depositing an electrode on the wall of the dielectric using atomic layer deposition (ALD), Forming a programmable material on the electrode; Forming a conductor for the programmable material How to include. The method of claim 1, Depositing a barrier between the electrode and the programmable material using ALD, the barrier comprising at least one of titanium silicide and titanium nitride How to include more. The method of claim 1, wherein conformally depositing the electrode comprises conformally depositing such that the electrode film thickness is between 10 angstroms and 1000 angstroms thick. The method of claim 1, wherein conformally depositing the electrode comprises tungsten (W), tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TN) having a resistivity of 0.001 0.05cm to 0.05 Ωcm. TiSiN), and at least one of tantalum nitride (TaN) conformally depositing. 2. The method of claim 1, wherein forming a programmable material comprises forming a chalcogenide memory device. Contacts on the substrate, A dielectric on the contact, the dielectric having an opening that exposes the contact; and Electrodes conformally deposited on the walls of the dielectric by atomic layer deposition (ALD), A programmable material on the electrode, Conductor formed for the programmable material Device comprising a. 7. The apparatus of claim 6, further comprising a barrier deposited by ALD between the electrode and the programmable material, the barrier comprising at least one of titanium silicide and titanium nitride. 7. The apparatus of claim 6, wherein the electrode has a film thickness of 10 angstroms to 1000 angstroms. The method of claim 6, wherein the electrode has a resistivity of 0.001 Ωcm to 0.05 Ωcm, the electrode is tungsten (W), tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TiSiN), and At least one of tantalum nitride (TaN). 7. The apparatus of claim 6, wherein the programmable material comprises a chalcogenide memory element. A microprocessor, Input / output (I / O) ports, A contact on a substrate, a dielectric on the contact, the dielectric having an opening exposing the contact, an electrode conformally deposited on a wall of the dielectric by atomic layer deposition (ALD), and a program on the electrode A memory comprising a programmable material and a conductor formed for the programmable material Including, The microprocessor, the I / O port, and the memory are connected by a data bus, an address bus, and a control bus.  12. The system of claim 11 further comprising a barrier deposited by ALD between the electrode and the programmable material, the barrier comprising at least one of titanium silicide and titanium nitride.  The system of claim 11, wherein the electrode has a film thickness from 10 angstroms to 1000 angstroms.  The method of claim 11, wherein the electrode has a resistivity of 0.001 Ωcm to 0.05 Ωcm, the electrode is tungsten (W), tungsten nitride (WN), titanium nitride (TiN), titanium silicon nitride (TiSiN), and A system comprising at least one of tantalum nitride (TaN).  12. The system of claim 11, wherein said programmable material comprises chalcogenide memory elements.

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