KR100670048B1 - A Liquid Crystal Display and A Driving Method Thereof - Google Patents

Abstract

The liquid crystal display of the present invention generates a correction data voltage in consideration of the data voltage of the current frame and the data voltage of the previous frame, and then applies the generated correction data voltage to the data line. By applying the above correction data voltage to the data line, the pixel voltage can reach the target level immediately.

Calibration data voltage, frame memory, data voltage compensation

Description

A liquid crystal display and a driving method thereof

1 is a diagram illustrating an equivalent circuit of each pixel in a liquid crystal display.

2 is a diagram illustrating a data voltage and a pixel voltage applied by a conventional driving method.

3 is a view showing transmittance of a liquid crystal display according to a conventional driving method.

4 is a model modeling a relationship between voltage and dielectric constant of a liquid crystal display.

5 is a view showing a data voltage application method according to a first embodiment of the present invention.

6 is a diagram illustrating transmittance of a liquid crystal display when a data voltage is applied according to the first embodiment of the present invention.

7 is a diagram illustrating transmittance of a liquid crystal display when a data voltage is applied according to the second embodiment of the present invention.

8 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

9 is a diagram illustrating a data voltage corrector according to an exemplary embodiment of the present invention.

10 is a diagram illustrating a conversion table according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a driving method thereof, and more particularly, to a liquid crystal display and a driving method thereof to which a compensated data voltage is applied so as to be suitable for realizing a moving image.

Recently, display devices are also required to be lighter and thinner in accordance with the light weight and thickness of personal computers and televisions, and according to such demands, flat displays such as liquid crystal displays (LCDs) instead of cathode ray tubes (CRTs) are required. Panel-type displays are being developed.

An LCD is a display device that obtains a desired image signal by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field. Such LCDs are typical among portable flat panel displays, and among them, TFT LCDs using thin film transistors (TFTs) as switching elements are mainly used.

Recently, as TFT LCDs are widely used as display devices of televisions as well as display devices of computers, there is an increasing need to implement moving images. However, the conventional TFT LCD has a disadvantage in that it is difficult to implement a moving picture because the response speed is slow. In order to improve the response speed problem, conventionally, an OCB (optically compensated band) mode or a TFT LCD using a ferro-electric liquid crystal (FLC) material is used.

However, in order to use such an OCB mode or FLC, a conventional TFT LCD panel has a problem of changing the structure.

The technical problem to be solved by the present invention is to solve the above problems and to improve the response speed of the liquid crystal by changing the driving method of the liquid crystal without changing the panel structure of the TFT LCD.

According to an aspect of the present invention for achieving the above object,

A plurality of gate lines transferring scan signals, a plurality of data lines transferring data voltages and insulated from and intersecting the gate lines, and formed in an area surrounded by the gate lines and the data lines, respectively, connected to the gate lines and the data lines, respectively. A liquid crystal display panel including a plurality of pixels arranged in a matrix form having a switching element; A gate driver for sequentially supplying scan signals to the gate lines; A data gradation signal correction unit which receives a gradation signal from a data gradation signal source and outputs a correction gradation signal in consideration of the gradation signal of the current frame and the gradation signal of the previous frame; And a data driver for converting the corrected gradation signal output from the data gradation signal correction unit into a corresponding data voltage and supplying the corrected gradation signal to the data line.

Here, the data gradation signal correction unit

A frame memory which receives a gray level signal from the data gray level signal source and stores and outputs the received gray level signal for one frame; A controller which controls the writing and reading of the gradation signal of the frame memory; And a data gradation signal converter configured to output the corrected gradation signal in consideration of the gradation signal of the current frame received from the data gradation signal source and the gradation signal of the previous frame received from the frame memory.

Meanwhile, the liquid crystal display according to another feature of the present invention is

A plurality of gate lines transferring scan signals, a plurality of data lines transferring data voltages and insulated from and intersecting the gate lines, and formed in an area surrounded by the gate lines and the data lines, respectively, connected to the gate lines and the data lines, respectively. A liquid crystal display panel including a plurality of pixels arranged in a matrix form having a switching element; A gate driver for sequentially supplying scan signals to the gate lines; A data voltage corrector which receives the data voltage from the data voltage source and outputs a correction data voltage in consideration of the data voltage of the current frame and the data voltage of the previous frame; And a data driver for supplying the corrected data voltage output from the data voltage corrector to the data line.

On the other hand, the driving method of the liquid crystal display device according to an aspect of the present invention

Arranged in a matrix form having a plurality of gate lines and a plurality of data lines insulated from and intersecting the gate lines, the switching elements connected to the gate lines and the data lines, respectively; A driving method of a liquid crystal display device including a plurality of pixels,

Sequentially supplying scan signals to the gate lines; Receiving an image signal from an image signal source and generating a corrected image signal in consideration of the image signal of the current frame and the image signal of the previous frame; And supplying a data voltage corresponding to the generated corrected image signal to the data line.

Hereinafter, embodiments of the present invention will be described in detail.

In general, LCDs include a plurality of gate lines that transmit scan signals and data lines that cross the gate lines and transmit data voltages. In addition, the LCD is formed in an area surrounded by these gate lines and data lines, and includes a plurality of pixels in matrix form connected through the gate lines and data lines and the switching elements, respectively.

In the LCD, each pixel may be modeled as a capacitor having a liquid crystal as a dielectric, that is, a liquid crystal capacitor. An equivalent circuit of each pixel in the LCD is shown in FIG.

As shown in FIG. 1, each pixel of the liquid crystal display includes a TFT 10 having a source electrode and a gate electrode connected to a data line Dm and a gate line Sn, and a drain electrode and a common voltage Vcom of the TFT, respectively. ) And a storage capacitor (Cst) connected to the liquid crystal capacitor (Cl) connected to the drain electrode of the TFT.

In FIG. 1, when the gate on signal is applied to the gate line Sn and the TFT 10 is turned on, the data voltage Vd supplied to the data line is applied to each pixel electrode (not shown) through the TFT. Then, an electric field corresponding to the difference between the pixel voltage Vp and the common voltage Vcom applied to the pixel electrode is applied to the liquid crystal (equivalently represented by the liquid crystal capacitor in FIG. 1), and thus transmittance corresponding to the intensity of the electric field. To allow light to pass through. In this case, the pixel voltage Vp should be maintained for one frame. In FIG. 1, the storage capacitor Cst is used to maintain the pixel voltage Vp applied to the pixel electrode.

On the other hand, since the liquid crystal has an anisotropic dielectric constant, there is a characteristic that the dielectric constant is different depending on the direction of the liquid crystal. That is, as the direction of the liquid crystal changes as the voltage is applied, the dielectric constant also changes accordingly, and thus the capacitance of the liquid crystal capacitor (hereinafter referred to as 'liquid crystal capacitance') also changes. Once electric charge is supplied to the liquid crystal capacitor during the period in which the TFT is turned on, the TFT is turned off. Since Q = CV, when the liquid crystal capacitance changes, the pixel voltage Vp applied to the liquid crystal also changes.

A/d이 된다. 여기서,

는 액정 분자가 기판에 평행한 방향으로 배열된 경우 즉, 액정 분자가 빛의 방향과 수직한 방향으로 배열된 경우의 유전율을 나타내며, A와 d는 각각 LCD 기판의 면적과 기판 사이의 거리를 나타낸다. 풀 블랙(full black)을 구현하기 위한 전압이 5V라 하면 액정에 5V가 인가되는 경우 액정 분자가 기판에 수직한 방향으로 배열되므로 액정 커패시턴스는 C(5V)=

A/d이 된다. TN 모드에 사용되는 액정의 경우에는

-

〉0 이므로 액정에 인가되는 화소 전압이 높아질수록 액정 커패시턴스가 더 커지 게 된다. Normally white mode TN (twisted Nematics) LCD, for example, when the pixel voltage supplied to the pixel is 0V, the liquid crystal capacitance is arranged in a direction parallel to the substrate, the liquid crystal capacitance is C (0V) =

A / d. here,

Denotes the permittivity when the liquid crystal molecules are arranged in a direction parallel to the substrate, that is, when the liquid crystal molecules are arranged in a direction perpendicular to the direction of the light, and A and d represent the area of the LCD substrate and the distance between the substrates, respectively. . If the voltage for realizing full black is 5V, when 5V is applied to the liquid crystal, the liquid crystal molecules are arranged in the direction perpendicular to the substrate, so that the liquid crystal capacitance is C (5V) =

A / d. In the case of liquid crystal used in TN mode

-

> 0, the higher the pixel voltage applied to the liquid crystal, the larger the liquid crystal capacitance becomes.

The amount of charge that the TFT must charge to make full black in the nth frame is C (5V) × 5V. However, assuming full white (V _n-1 = 0 V) in the n-1 th frame, which is the previous frame, the liquid crystal capacitance becomes C (0 V) since the liquid crystal does not respond during the turn-on time of the TFT. Therefore, even if a data voltage Vd of 5V is applied in the nth frame to make full black, the amount of charge charged in the actual pixel is C (0V) × 5V, and C (0V) <C (5V). The pixel voltage Vp supplied is applied with a pixel voltage less than 5V (for example, 3.5V), so that full black is not implemented. In addition, when the data voltage Vd is applied at 5V to implement full black in the next frame, the n + 1th frame, the amount of charge charged in the liquid crystal becomes C (3.5V) × 5V, which is eventually supplied to the liquid crystal. The voltage Vp is between 3.5V and 5V. If this process is repeated, the pixel voltage Vp reaches a desired voltage after several frames.

In other words, when the signal (pixel voltage) applied to an arbitrary pixel is changed from a low gray level to a high gray level (or from a high gray level to a low gray level), the gray level of the current frame is influenced by the gray level of the previous frame. Because it does not receive the desired gradation, it does not reach the desired gradation until a few frames have elapsed. Similarly, the transmittance of the pixel of the current frame is influenced by the transmittance of the pixel of the previous frame to obtain the desired transmittance after a few frames have elapsed.

On the other hand, if n-1 frame is full black, that is, the pixel voltage (Vp) is 5V, and a data voltage of 5V is applied to implement full black in n frame, the liquid crystal capacitance is C (5V), so C The amount of charges corresponding to (5V) x 5V is charged, so that the pixel voltage Vp of the liquid crystal is 5V.

As such, the pixel voltage Vp actually supplied to the liquid crystal is determined not only by the data voltage supplied to the current frame but also by the pixel voltage Vp of the previous frame.

2 is a diagram illustrating a data voltage and a pixel voltage when applied in the conventional driving method.

As shown in FIG. 2, the data voltage Vd corresponding to the target pixel voltage Vw is applied every frame without considering the pixel voltage Vp of the previous frame. Therefore, as described above, the pixel voltage Vp actually applied to the liquid crystal is lower or higher than the target pixel voltage by the liquid crystal capacitance corresponding to the pixel voltage of the previous frame. Therefore, the target pixel voltage is only reached after a few frames.

3 is a diagram showing the transmittance of the liquid crystal display according to the conventional driving method.

As shown in FIG. 3, in the related art, since the actual pixel voltage is lower than the target pixel voltage as described above, even when the response time of the liquid crystal is within 1 frame, the target transmittance is not reached until several frames have passed.

The embodiment of the present invention compares the image signal Sn of the current frame with the image signal Sn-1 of the previous frame to generate the following correction signal Sn 'and then corrects the image signal Sn'. Is applied to each pixel. Here, the image signal Sn refers to a data voltage in the analog driving method, but in the case of the digital driving method, since the binary gray level signal is used to control the data voltage, the correction of the voltage applied to the actual pixel is performed. Through the correction of

First, if the image signal (gradation signal or data voltage) of the current frame is the same as the image signal of the previous frame, correction is not performed.

Second, when the gray level signal or data voltage of the current frame is higher than the gray level signal (data voltage) of the previous frame, a corrected gray level signal (data voltage) is output than the current gray level signal (data voltage), and the current frame is output. When the gray level signal (data voltage) is lower than the gray level signal (data voltage) of the previous frame, the corrected gray level signal (data voltage) is lower than the current gray level signal (data voltage). At this time, the degree of correction is proportional to the difference between the current gray level signal (data voltage) and the gray level signal (data voltage) of the previous frame.

Hereinafter, a data voltage correction method according to an embodiment of the present invention will be described quantitatively.

4 is a model for simply modeling a relationship between a voltage and a dielectric constant of a liquid crystal display.

과 액정이 기판에 평행한 방향으로 배열된 경우 즉, 액정이 빛의 투과 방향 과 수직한 경우의 유전율(

)의 비를 나타낸다.In Fig. 4, the horizontal axis is the pixel voltage, and the vertical axis is the permittivity at a specific pixel voltage v.

And when the liquid crystals are arranged in a direction parallel to the substrate, that is, when the liquid crystals are perpendicular to the transmission direction of light (

) Ratio.

/

의 최대값 즉,

/

을 3이라 가정하였고, Vth와 Vmax를 각각 1V, 4V로 가정하였다. 여기서, Vth와 Vmax는 각각 풀 화이트 및 풀 블랙(또는 그 반대)에 해당하는 화소 전압을 나타낸다. In Figure 4,

Of

That is, the maximum of

Of

Is assumed to be 3, and Vth and Vmax are assumed to be 1V and 4V, respectively. Here, Vth and Vmax represent pixel voltages corresponding to full white and full black (or vice versa), respectively.

  If the capacitance of the storage capacitor (hereinafter referred to as 'storage capacitance') is equal to the average value of the liquid crystal capacitance <Cst>, and the width of the LCD substrate and the distance between the substrates are A and d, respectively, the storage capacitance Cst is It can be represented by Equation 1 below.

Cst = 〈Cl〉= 1/3 ( + 2) A/d = 5/3 A/d = 5/3 C0

Cst = 〈Cl〉 = 1/3 (+ 2) A / d = 5/3 A / d = 5/3 C0

A/d이다. Where C0 =

A / d.

/

는 다음의 수학식 2로 나타낼 수 있다. 4,

Of

May be represented by Equation 2 below.

/ = 1/3(2V + 1)

/ = 1/3 (2V + 1)

Since the total capacitance C (V) of the LCD is the sum of the liquid crystal capacitance and the storage capacitance, the capacitance of the LCD may be represented by the following equation (3) from equations (1) and (2).

C(V) = Cl + Cst = A/d + 5/3 C0 = 1/3(2V + 1)C0 + 5/3 C0

C (V) = Cl + Cst = A / d + 5/3 C0 = 1/3 (2V + 1) C0 + 5/3 C0

     = 2/3 (V + 3) C0

Since the charge amount Q applied to the pixel is preserved, the following equation (4) holds.

Q = C (Vn) Vn = C (Vf) Vf

Here, Vn represents a data voltage to be applied to the current frame (absolute value of the data voltage in the case of the inversion driving type), and C (Vn-1) represents a capacitance corresponding to the pixel voltage of the previous frame (n-1 frame). C (Vf) represents a capacitance corresponding to the actual pixel voltage Vf of the current frame (n frame).

The following equation (5) can be derived from equations (3) and (4).

C (Vn-1) Vn = C (Vf) Vf = 2/3 (Vn-1 + 3) Vn = 2/3 (Vf + 3) Vf

Therefore, the actual pixel voltage Vf can be represented by the following equation (6).

As can be clearly seen from Equation 6 above, the actual pixel voltage Vf is determined by the data voltage Vn applied to the current frame and the pixel voltage Vn-1 applied to the previous frame.

On the other hand, if the data voltage applied to make the pixel voltage reach the target voltage Vn in n frames is Vn ', Vn' may be represented by the following equation (7).

(Vn-1 + 3) Vn '= (Vn + 3) Vn

Therefore, Vn 'may be represented by the following equation (8).

As such, when the data voltage Vn 'obtained by Equation 8 is applied in consideration of the target pixel voltage Vn of the current frame and the pixel voltage Vn-1 of the previous frame, the target pixel voltage Vn is applied. You can reach it right away.

Equation 8 is derived from the diagram shown in FIG. 4 and some basic assumptions, and the data voltage Vn 'applied to a general LCD may be represented by Equation 9 below.

 Here, the function f is determined by the characteristics of the LCD. The function f basically has the following properties.

과

이 같은 경우에 f=0이 되며,

이

보다 큰 경우 f는 0 보다 크고,

이

보다 작은 경우 f는 0 보다 작다. In other words,

and

In this case, f = 0,

this

Is greater than 0 if greater than

this

If less than f is less than zero.

The following describes a data voltage application method according to an embodiment of the present invention.

5 is a view showing a data voltage application method according to the present invention.

As shown in Fig. 5, in the first embodiment of the present invention, the pixel voltage Vp is applied by applying the corrected data voltage Vn 'in consideration of the target pixel voltage of the current frame and the pixel voltage (data voltage) of the previous frame. This is to reach the target voltage. That is, in the first embodiment of the present invention, when the target voltage of the current frame and the pixel voltage of the previous frame are different, a first voltage (or lower voltage) higher than the target voltage of the current frame is applied as the corrected data voltage. After the target voltage level is reached directly in the frame, the target voltage is applied as the data voltage in subsequent frames. In this way, the response speed of the liquid crystal can be improved.

In this case, the corrected data voltage (charge amount) is determined in consideration of the liquid crystal capacitance determined by the pixel voltage of the previous frame. That is, according to the present invention, the charge amount Q is supplied in consideration of the pixel voltage level of the previous frame to reach the target voltage level immediately in the first frame.

6 is a diagram illustrating transmittance of a liquid crystal display when a data voltage is applied according to the first embodiment of the present invention. As shown in Fig. 6, since the corrected data voltage is applied according to the first embodiment of the present invention, the target transmittance is directly reached in the current frame.

 On the other hand, in the second embodiment of the present invention, the corrected voltage Vn 'slightly higher than the target voltage is applied as the pixel voltage. In this case, as shown in FIG. 7, the transmittance becomes smaller than the target value before about 1/2 of the response time of the liquid crystal, but after that, the transmittance is overcompensated and the average transmittance is equal to the target transmittance. Lose.

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described.

8 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention. The liquid crystal display according to the embodiment of the present invention shown in FIG. 8 uses a digital driving method.

As shown in FIG. 8, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel 100, a gate driver 200, a data driver 300, and a data gray level signal correction unit 400. .

In the liquid crystal display panel 100, a plurality of gate lines S1, S2, S3,..., Sn for transmitting a gate-on signal are formed, and data lines D1, for transmitting a corrected data voltage. D2, ..., Dm) are formed. The region surrounded by the gate line and the data line constitutes a pixel, and each pixel is connected to the thin film transistor 110 and the drain electrode of the thin film transistor 110 and the gate electrode and the source electrode connected to the gate line and the data line, respectively. (Cl) and the storage capacitor (Cst).

The gate driver 200 sequentially applies a gate-on voltage to the gate line, thereby turning on the TFT to which the gate electrode is connected to the gate line to which the gate-on voltage is applied.

The data gray level signal corrector 400 receives the data gray level signal Gn from a data gray level signal source (for example, a graphic controller) and then, as described above, the data gray level signal of the current frame and the data gray level signal of the previous frame. In consideration of this, the corrected data gradation signal Gn 'is output. In this case, the gradation signal correcting unit may exist as a stand-alone unit or may be integrated into a graphic card or an LCD module.

The data driver 300 converts the corrected gradation signal Gn 'received from the data gradation signal correction unit 400 into a corresponding gradation voltage (data voltage) and applies them to the data lines, respectively.

9 is a block diagram illustrating in detail a data gray signal correcting unit 400 according to an exemplary embodiment of the present invention.

As shown in FIG. 9, the data gray signal correcting unit 400 according to an exemplary embodiment of the present invention includes a synthesizer 410, a frame memory 420, a controller 430, a data gray signal converter 440, and a separator ( 450).

The synthesizer 410 receives the grayscale signal Gn transmitted from the data grayscale signal source and converts the frequency of the data stream at a rate that the data grayscale signal corrector 400 can process. For example, if 18 bits of data are received in synchronization with a 65 MHz frequency from a data gray signal source, and the processing speed of the components of the data gray signal correcting unit 400 is 50 Mhz, the synthesizer 410 may have 18 bits of gray. Two signals are bundled and synthesized into 36-bit gradation signals Gm and transmitted to the frame memory 420.

The synthesized gradation signal Gm outputs the previous gradation signal Gm-1 stored at a predetermined address to the data gradation signal converter 440 and is transmitted from the synthesizer 410 under the control of the controller 430. The gray level signal Gm to be stored is stored in the predetermined address. The data gradation signal converter 440 receives the gradation signal Gm of the current frame output from the synthesizer and the gradation signal Gm-1 of the previous frame output from the frame memory 420, and transfers the gradation signal of the current frame and the previous one. In consideration of the gray level signal of the frame, a corrected gray level signal Gm 'is generated.

The separator 450 separates the 36-bit corrected data gradation signal Gm 'output from the data gradation signal converter 440 and outputs the 18-bit corrected gradation signal Vn'.

In the embodiment of the present invention, since the clock frequency synchronized with the data gray level signal is different from the clock frequency for accessing the frame memory, a synthesizer 410 and a separator 450 for synthesizing and separating the data gray level signal are required. Such a synthesizer and a separator are unnecessary when the clock frequency synchronized with the signal and the clock frequency for accessing the frame memory 420 are the same.

As the data gradation signal converter 440 according to an embodiment of the present invention, a digital circuit that satisfies Equation 9 described above may be directly manufactured and used, and a look-up table may be prepared to read a read only memory (ROM). The gradation signal may be corrected by accessing the data after storing the data in the. In practice, the correction data voltage Vn 'is a complex function that is not only proportional to the difference between the data voltage (Vn-1) of the previous frame and the data voltage (Vn) of the current frame, but also depends on each absolute value. The advantage is that the circuit is much simpler than relying on processing.

On the other hand, to correct the data voltage according to an embodiment of the present invention should have a wider dynamic range than the actual gray scale range, which can be solved by using a high voltage integrated circuit (IC) in an analog circuit, but can be divided in a digital manner The number of gradations is limited. For example, in the case of 6-bit gradation, some of the 64 gradation levels must be allocated for the modulated voltage and not the actual gradation indication. In other words, some gradation levels should be allocated for voltage correction. Therefore, the number of gradations to be expressed is reduced.

Meanwhile, the following concept of truncation may be introduced to prevent a decrease in the number of gradations. For example, suppose that the liquid crystal drives between 1-4V and the voltage is required from 0-8V when considering the correction voltage. In this case, dividing up to 8V into 64 steps for faithful correction results in only about 30 gradations that can be actually expressed. Therefore, when the voltage width is lowered to 1-4V and the calculated voltage Vn 'exceeds 4V, truncating the correction voltage to 4V can reduce the number of gray levels.

10 is a configuration of a conversion table according to an embodiment of the present invention in which the concept of truncation is introduced.

As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, A various other change and a deformation | transformation are possible.

For example, in the exemplary embodiment of the present invention, the liquid crystal display device driven digitally is described in FIG. 8, but the present invention may also be applied to the liquid crystal display device driven in an analog manner.

In this case, a data voltage corrector that corresponds to the data gray scale signal corrector illustrated in FIG. 8 is required, and the data voltage corrector may be implemented through an analog circuit that satisfies Equation (9).

As described above, according to the present invention, the pixel voltage can reach the target voltage level by correcting the data voltage and applying the corrected data voltage to the pixel. Thus, the response speed of the liquid crystal can be improved without having to change the panel structure of the TFT LCD.

Claims (18)

A plurality of gate lines transferring scan signals, a plurality of data lines transferring data voltages and insulated from and intersecting the gate lines, and formed in an area surrounded by the gate lines and the data lines, respectively, connected to the gate lines and the data lines, respectively. A liquid crystal display panel comprising a plurality of pixels arranged in a matrix form having a switching element A gate driver for sequentially supplying scan signals to the gate lines; A data gradation signal correction unit which receives a gradation signal from a data gradation signal source and outputs a correction gradation signal in consideration of the gradation signal of the current frame and the gradation signal of the previous frame, and A data driver for converting the corrected gray level signal output from the data gray level signal corrector into a corresponding data voltage and supplying the corrected data voltage to the data line; Including, The data gray level signal correction unit A frame memory which receives a gray level signal from the data gray level signal source and stores and outputs the received gray level signal for one frame; A controller which controls the writing and reading of the gradation signal of the frame memory; A data gradation signal converter for outputting the corrected gradation signal in consideration of the gradation signal of the current frame received from the data gradation signal source and the gradation signal of the previous frame received from the frame memory; A synthesizer for receiving the gradation signal transmitted from the data gradation signal source, synthesizing the gradation signal to match the clock frequency to which the controller is synchronized, and outputting the synthesized gradation signal to the frame memory and the data gradation signal converter; A separator which separates the gray level signal output from the data gray level signal converter so that the gray level signal transmitted from the data gray level signal source matches the frequency to which the gray level signal is synchronized. Containing Liquid crystal display. delete delete The method of claim 1, And a clock frequency synchronized with the gray level signal supplied from the data gray level signal source and a clock frequency synchronized with the controller. delete The method of claim 4, wherein The data gradation signal converter assumes that the data voltage of the current frame is Vn and the data voltage of the previous frame is Vn-1.

And a gradation signal corrected to output a correction data voltage Vn 'that satisfies the above expression. The method of claim 6, And the data gradation signal converter outputs a corrected gradation signal satisfying the above equation using a digital circuit. The method of claim 4, wherein The data gradation signal converter is And a memory for storing a conversion table for recording the gradation signal corresponding to the gradation signal of the previous frame and the gradation signal of the current frame. The method of claim 8, The conversion table is The correction data voltage is the first voltage when the correction data voltage is larger than the first voltage, and the correction data voltage is the second voltage when the correction data voltage is smaller than the second voltage. Display device. A plurality of gate lines transferring scan signals, a plurality of data lines transferring data voltages and insulated from and intersecting the gate lines, and formed in an area surrounded by the gate lines and the data lines, respectively, connected to the gate lines and the data lines, respectively. A liquid crystal display panel including a plurality of pixels arranged in a matrix form having a switching element; A gate driver for sequentially supplying scan signals to the gate lines; A data voltage corrector which receives the data voltage from the data voltage source and outputs a correction data voltage in consideration of the data voltage of the current frame and the data voltage of the previous frame; And And a data driver for supplying the corrected data voltage output from the data voltage corrector to the data line. The method of claim 10, When the data voltage converter refers to the data voltage of the current frame as Vn and the data voltage of the previous frame as Vn-1,

And correcting the data voltage so as to output the correction data voltage Vn 'satisfying the above expression. delete delete delete delete delete delete delete

Images