KR100670041B1 - Fast Ethernet Receive Data Error Correction Circuit - Google Patents

Abstract

The present invention relates to a data receiving unit of a fast Ethernet 100Base-TX physical layer, and more particularly, to detect a data error occurring in a transmission line during data transmission / reception, and to notify the upper layer only by detecting a data error occurring in a transmission line. By adding error correction to the physical layer in addition to the simple Fast Ethernet physical layer, Fast Ethernet reception improves the accuracy of data transmission and reception in Fast Ethernet systems and eliminates the inefficiency of error data retransmissions, thereby improving the overall network efficiency of Fast Ethernet. Data error correction circuit.

To this end, the present invention includes a 5B / 4B decoder, a 5-bit symbol delay unit, a replacement, a 5B / 4B decoder, a 4B / 8B parallelizer, a cyclic redundancy checker, a multiplexer, and a reception-independent interface.

High Speed Ethernet, Independent Mediation Interface, 5B / 4B Decoder, Cyclic Redundancy Check, Link Layer, Physical Layer

Description

Fast Ethernet Receive Data Error Correction Circuit

1 is a schematic diagram of a Fast Ethernet network system.

2 is a block diagram of an error correction circuit of a data receiver of a Fast Ethernet physical layer proposed by the present invention.

The present invention relates to a data receiving unit of a fast Ethernet 100Base-TX physical layer. In particular, a fast Ethernet improves the accuracy of data transmission and reception in a fast Ethernet system by adding a function to correct a data error occurring in a transmission line during data transmission and reception to the physical layer. It relates to a received data error correction circuit.

The Institute of Electrical and Electronic Engineers (IEEE) 802.3 protocol in Ethernet communication is called carrier sense multiple access with collision detection (CSMA / CD).

A terminal operating in a CSMA / CD scheme checks a carrier in a transmission path before transmission and performs frame transmission when a channel is available. However, when there is a transmission from another terminal at the time of transmission, collision between frames inevitably occurs. If a collision is detected, it immediately stops transmitting the rest of the frame being transmitted and prepares for retransmission after a certain time.

Accordingly, in the CSMA / CD scheme, when a frame transmitted by terminals collides by sharing a transmission medium, a function of detecting a collision with a carrier and a function of retransmitting are implemented in a physical layer and a data link layer.

The link layer performs CSMA / CD operation according to carrier and collision information reported by the physical layer, and the physical layer transmits the transmitted and received bit strings in the form of non return to zero (NRZ) requested by the link layer to Manchester code. do. In addition, it extracts the transmission and reception clock from the received Manchester code, restores the NRZ bit string, detects carriers and collisions on the connected transmission medium, and reports them to the link layer.

Hereinafter, an Ethernet network system will be described with reference to the accompanying drawings.

1 is a schematic diagram of a Fast Ethernet network system.

In order for a plurality of PCs 30, 40, ..., N-1, N to operate independently and exchange information with each other, a management technology using a unified protocol is essential. In recent years, the biggest challenge is to deliver a large amount of information quickly, which is an increase in the amount of information per unit time.

Accordingly, it is necessary to connect a plurality of PCs (30, 40, .... N-1, N) to a single network and to smoothly exchange information between terminals falling within the network category. Therefore, it is necessary to distinguish whether terminals transmit and receive data in the same network category or transmit and receive data in different networks. Accordingly, it manages the data exchange between the network file server 10 and the plurality of PCs 30, 40, .... N-1, N with a repeater called a hub (hub) 20 or repeater. As the number of terminals connected to a network, that is, the number of channels, increases in these repeaters, the technology for managing them becomes more difficult. Therefore, as the repeater with better performance has to look at the contents of data transmitted and received by each terminal and control accordingly, the bottleneck does not occur in the network.

Conventional Fast Ethernet physical layer performs 5B / 4B decoding function of received frame data of 100Base-TX Ethernet in 4-bit unit during processing of received data. In this process, data error occurred in transmission line is transferred to 5B / 4B conversion table. By detection.

The detected error data is sent to the upper link layer as a reception error signal through a reception independent interface, and the link layer discards the entire reception frame including the reception error signal and causes the transmitter to retransmit the entire frame. Therefore, the conventional Fast Ethernet physical layer has a problem of reducing the transmission and reception efficiency of the network.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and improves the accuracy of data transmission and reception by detecting a data error occurring in a transmission line during transmission and reception of data and correcting the error.

In order to achieve this problem, the error correction circuit of the data receiver of the fast Ethernet physical layer proposed by the present invention includes a 5B / 4B decoder, a 5-bit symbol delay unit, a 5B / 4B decoder, a 4B / 8B parallelizer, a cyclic redundancy checker, Includes multiplexer and receive-independent interface.

The 5B / 4B decoder converts the parallel data grouped into 5 bits into 4 bits and outputs them to the medium access control of the link layer.

The 5-bit symbol delay adjusts the delay time to synchronize the received error signal through the 5B / 4B decoder with the received symbol signal from the transmission line.

The replacement and 5B / 4B decoding unit assumes that the received symbol data passing through the 5B / 4B decoder corresponds to High and that the received symbol data that has passed through the 5-bit symbol delayer is 1-bit error data. Generate bit data.

The 4B / 8B parallelizer parallelizes the 4-bit path data from the replacement and 5B / 4B decoders into 8-bit data to compute the 32-bit cyclic redundancy check check into 8 bits.

The cyclic redundancy check unit transmits 8-bit data from the 4B / 8B parallelizing unit with an extra code for each received frame, checks whether the transmission contents are correct accordingly, and outputs a cyclic redundancy check check completion signal.

When the received error signal is high, the multiplexer replaces the last four of the five modified four-bit data replaced by the 5B / 4B decoding unit and the error is recovered by the control of the cyclic redundancy check check completion signal of the cyclic redundancy check unit. Select bit data.

Receiving-independent interface is a connection that connects the media access control section of the link layer and the physical layer. It converts to a stream and delivers the received error signal to the link layer.

An embodiment of a data receiver error correction circuit of the fast Ethernet physical layer of the present invention configured as described above will be described with reference to FIG. 2.

2 is a block diagram of an error correction circuit of a data receiver of a Fast Ethernet physical layer proposed by the present invention.

As shown in FIG. 2, the data received from the transmission line is grouped into 5-bit parallel data in the physical layer and converted into 4 bits through the 5B / 4B decoder 100 to provide the reception media independent interface 700 with the reception error signal. It is output to the medium access control of the link layer.

The 5-bit symbol delay unit 200 receives the received error signal passing through the 5B / 4B decoder 100 and the received symbol signal from the transmission line, and adjusts and outputs a delay time for synchronization.

The replacement and 5B / 4B decoding unit 300 receives 1-bit error data from the received symbol data that has received a 5B / 4B decoder 100 through the 5-bit symbol delay unit 200 and corresponds to a high signal. In this example, five errors are generated to recover 4-bit data.

The 4B / 8B parallelizing unit 400 receives the 4-bit path data from the replacement and 5B / 4B decoding unit 300 and parallelizes the 8-bit data to calculate the 32-bit cyclic redundancy check check into 8 bits.

The cyclic redundancy check unit 500 receives 8-bit data from the 4B / 8B parallelizing unit 400 and transmits a redundant code for each received frame, checks whether the transmission contents are correct accordingly, and completes the cyclic redundancy check. Output the signal.

When the received error signal is high, the multiplexer 600 replaces the cyclic redundancy check check completion signal of the cyclic redundancy check unit 500 among the five modified four-bit data replaced by the 5B / 4B decoding unit 300 when the received error signal is high. The control selects the last 4 bits of data from which the error was recovered.

The reception medium independent interface 700 is a connection unit connecting the media access control unit of the link layer and the physical layer, and uses the 5B / 4B decoder 100 of the physical layer to rapidly transmit a bit string of a frame requested to be transmitted by the medium access control unit. It converts the 4-bit stream into the link layer with the received error signal.

Next, an operation of the data receiver error correction circuit of the fast Ethernet physical layer according to the present invention will be described in detail with reference to FIG. 2.

When a 1-bit error occurs in 5B / 4B decoding of received data performed every 5 clocks by the 5B / 4B decoder 100, the received error signal is high and the first to fifth bits of the 5th received data are high. If only one bit is inverted, the number of five cases is formed.

The 5B data are converted into 8 bits in the 4B / 8B parallelization unit 400 after the 5B / 4B decoding is performed by the 5B / 4B decoding unit 300 at the same time. When the 8-bit data passes through the cyclic redundancy check unit 500, the cyclic redundancy check check result is obtained only in any one path data having no remainder in the cyclic redundancy check check among the five path data.

On the other hand, the five cases of data inverted by one bit in the 5B / 4B decoding unit 300 is applied in parallel to the input of the multiplexer 600, and the modified 4-bit data is controlled according to the control of the cyclic redundancy check completion signal. Choose.

As a result, when the 1-bit error selected by the multiplexer 600 is notified to the upper link layer, the upper link layer passes the 5B / 4B decoder 100 and passes through the reception media independent interface 700 to the link layer. The received data is replaced with the corrected data at the time when the reception error signal becomes High to accurately perform error correction of the received data 1 bit.

As described above, the error correction circuit of the data receiver of the fast Ethernet physical layer according to the present invention improves the accuracy of data transmission and reception by reducing the existing bit error rate and reduces the actual transmission speed of the LAN system by reducing the retransmission due to the data error. It is to ensure high reliability in terms of product quality.

Claims (2)

A fast Ethernet network system including a fast access physical layer and a link layer medium access control unit, A first decoder for converting the parallel data obtained by grouping data from an external transmission line into M bits and converting the parallel data into N bits and outputting the received error signal; If the received error signal is high, M errors are recovered by assuming that the received symbol data whose delay time is adjusted to synchronize the received error signal with the received symbol signal from the transmission line is 1 bit error data. A replacement and second decoding section for generating generated N-bit data; Parallelize the N-bit path data from the substitute and second decoding units into L-bit data, and then transmit a margin code for each received frame, and examine whether the transmission contents are correct accordingly and output a cyclic redundancy check completion signal. A cyclic redundancy check unit; When the received error signal is high, the link selects the last N-bit data of which the error is repaired among the M modified N-bit data replaced by the replacement and second decoding units according to the cyclic redundancy check completion signal. A multiplexer outputting the layer; A connection unit for connecting the medium access control unit of the link layer and the physical layer, wherein the medium access control unit of the link layer is provided in units of N bits through the first decoder of the physical layer for high speed transmission of the bit string of a frame requested to be transmitted. A fast Ethernet received data error correcting circuit comprising a received intermediary independent interface for converting into a stream and passing the received error signal to the link layer. In claim 1, The first decoder, And converting the parallel data grouping the data from the external transmission line into M bits into (M-1) bits and outputting the received error signal together with the received error signal.

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