KR100669550B1 - Address coding device of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address coding apparatus for a semiconductor device, and discloses a technique for reducing wiring of an internal transmission signal by processing an address having a minimum number of bits necessary for an IO configuration of a semiconductor device. In the present invention, a number of IO configurations are possible in a single unit, and a DRAM product having a minimum difference in the number of address bits required for each configuration exists, wherein the number of address bits required when the IO configuration is maximum is minimal. In some cases, the number of decoded addresses is determined. When the IO configuration is the minimum, each address bit is decoded by one bit and used to select a minimum unit group of memory cells.

Description

Address coding device of semiconductor device

1A and 1B are address tables for explaining an address coding apparatus of a conventional semiconductor element.

2 is a block diagram of an address coding apparatus of a conventional semiconductor element.

3 is a block diagram of the control block of FIG.

4A and 4B are address tables for explaining the address coding apparatus of the semiconductor element of the present invention.

5 is a configuration diagram of an address coding apparatus of a semiconductor device according to the present invention.

6 is a block diagram of each control block of FIG. 5;

FIG. 7 is a detailed circuit diagram of the BX12 address decoder of FIG. 5; FIG.

FIG. 8 is a detailed circuit diagram of the block controller of FIG. 6. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for coding an address of a semiconductor device, and to reduce wiring of an internal transmission signal by processing a minimum bit number of addresses by using die bonding used in address processing when selecting an IO configuration of a semiconductor device. It's a technology that makes it possible.

1A and 1B are address tables for explaining an address coding apparatus of a conventional semiconductor element.

The conventional address coding apparatus for semiconductor elements uses addresses A12, A11, A10, and A9 in forming a minimum unit group of memory cells and giving a block address to each group.

FIG. 1A is an address table showing coding when there are 16 minimum unit groups selectable by addresses A12, A11, A10, and A9 when the DRAM unit has a small IO configuration. 1B is an address table showing coding when the number of minimum unit groups is cut in half when the IO configuration increases and the required address is reduced by one bit.

Here, the block selection signals MSB <0:15> indicate the number of each minimum unit group and the identification number of the group selected by the input address.

As shown in FIGS. 1A and 1B, when an arbitrary address is input, the number of groups to be selected is different. For example, when the addresses A <12: 9> are all "0", the block select signal MSB <0> is selected in FIG. 1A, and the block select signals MSB <0> and MSB <8> are selected in FIG. 1B. .

2 is a configuration diagram of an address coding apparatus of a conventional semiconductor element.

A conventional address coding apparatus of a semiconductor device includes an address decoder 1, a driver 2, a plurality of control blocks 10, a cell block, and a sense amplifier array 20.

Here, the address decoder 1 decodes the input addresses BX12TI, BX11TI, BX10TI, and BX9TI to output the decoded signals MMS <0:15>. The driver 2 drives the decoding signals MMS <0:15> to generate the block selection signals MSB <0:15>. Each control block 10 receives a block selection signal MSB <0:15> and outputs a control signal CON to the cell block and the sense amplifier array 20.

3 is a detailed block diagram illustrating each of the control blocks 10 of FIG. 2.

The control block 10 includes a block control unit 11 and a control signal generator 12.

Here, the block control unit 11 receives the active control signal ACS and the block selection signal MSB and outputs an operation signal when the corresponding block is selected. The control signal generator 12 outputs a control signal CON necessary for driving the cell block and the sense amplifier array 20 when the operation signal applied from the block controller 11 is activated.

A conventional address coding apparatus of a semiconductor device having such a configuration must decode an address and transmit a decoded signal according to the number of minimum unit groups of a memory cell. However, when the number of unit groups increases, the number of decoding circuits and the wiring increase together, thereby increasing the area of the chip.

On the other hand, in the single unit of DRAM, various IO configurations are possible through die bonding, and the minimum number of address bits required for each selected IO configuration at the same time the IO configuration is selected varies depending on the IO configuration. I will. That is, in the case of a wide range of products that can be selected through die bonding in the DRAM IO configuration, the number of bits of the required address varies according to the size difference of the IO configuration unit.

In this case, most products are based on handling the maximum number of bits corresponding to the IO configuration. However, when the IO configuration becomes large and the number of required address bits becomes small, there is a problem that internal circuits and signals that process the maximum number between the required number of address bits and the maximum set number of circuits may be wasted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to reduce wiring of an internal transmission signal by processing an address having a minimum number of bits necessary for an IO configuration of a semiconductor device.

The address coding apparatus of the semiconductor device of the present invention for achieving the above object is to decode the byte option signal and the first address, the number of address bits required according to the input / output configuration to output the first group of decoded signals A first address decoder; A second address decoder configured to decode a signal of a second address group and output a decoded signal of a second group; A driver for driving a second group of decoding signals to generate a block selection signal; And a plurality of control blocks for determining whether to operate the corresponding block according to the decoding signal and the block selection signal of the first group and outputting control signals to the cell block and the sense amplifier array.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4A and 4B are address tables for explaining the address coding apparatus of the semiconductor element of the present invention.

4A is an address table showing coding when 16 units of the smallest unit selectable from the addresses A12, A11, A10, and A9 are used when the IO unit of the DRAM unit is small. 4B is an address table showing coding when the number of minimum unit populations is cut in half when the IO configuration increases and the required address is reduced by one bit.

As shown in FIG. 4A, in the present invention, when selecting a control block that is the smallest unit group of a memory cell, the input address A11, A10, A9 is decoded to generate a block selection signal MSB <0: 7>, and the address A12. Are decoded separately to generate a decoded signal BX12B <0: 1>.

Accordingly, by combining the block selection signals MSB <0: 7> and the decoding signals BX12B <0: 1>, it is possible to select one of the 16 control blocks that actually operates.

As shown in FIG. 4B, in the present invention, in selecting a control block that is a minimum unit group of a memory cell, an input address A12 becomes a Don't care bit, and an input address A11, A10, Only A9 will be decoded.

In the present invention, the number of block selection signals MSB <0: 7> is eight by using die bonding information necessary for IO selection, and the number can be cut in half compared to the conventional art. In the prior art, only two block selection signals MSB are required in the present invention, whereas only two block selection signals MSB <0:15> are selected. There are two control blocks.

5 is a configuration diagram of an address coding apparatus of a semiconductor device according to the present invention.

The present invention includes a BX12 address decoder 100, an address decoder 200, a driver 300, a plurality of control blocks 400, a cell block, and a sense amplifier array 500.

The BX12 address decoder 100 decodes the input address BX12TI and the byte option signal X32 to output the decoded signal BX12B <0: 1>. The address decoder 200 decodes the input addresses BX11TI, BX10TI, and BX9TI to output the decoded signals MMS <0: 7>. Here, the number of addresses to be decoded is determined in accordance with the case where the byte option signal X32 has the maximum IO configuration and the minimum number of address bits required.

The driver 300 drives the decoding signals MMS <0: 7> to generate the block selection signals MSB <0: 7>. Each control block 400 receives the decoded signal BX12B <0: 1> and the block select signal MSB <0: 7> to determine whether to operate the corresponding block, and thus the cell block and the sense amplifier array 500. The control signal CON is output to.

FIG. 6 is a detailed block diagram illustrating each of the control blocks 400 of FIG. 5.

The control block 400 includes a block controller 410 and a control signal generator 420.

Here, the block controller 410 receives the active control signal ACS, the block selection signal MSB and the decoding signal BX12B, and outputs an operation signal OUT when the corresponding control block is selected. When the operation signal OUT applied from the block controller 410 is activated, the control signal generator 420 outputs a control signal CON required for driving the cell block and the sense amplifier array 500.

FIG. 7 is a detailed circuit diagram of the BX12 address decoder 100 of FIG. 5.

The BX12 address decoder 100 includes a plurality of inverters IV1 to IV7, and noah gates NOR1 and NOR2.

Here, the NOA gate NOR1 performs a NO operation on the input address BX12TI inverted by the inverter IV1 and the byte option signal X32 which is non-inverted by the inverters IV2 and IV3. The NOR gate NOR2 nominates the byte option signal X32 which is non-inverted by the input address BX12TI and the inverters IV2 and IV3. Inverters IV4 and IV5 non-invert the delay of the output of the NOR gate NOR1 and output the decoded signal BX12B <0>. Inverters IV6 and IV7 non-invert the delay of the output of NOR gate NOR2 and output the decoded signal BX12B <1>.

The BX12 address decoder 100 having such a configuration determines the level of the decoded signal BX12B <0> depending on whether the byte option signal X32 representing the IO configuration is high / low.

That is, when the unit of the IO configuration is small, the byte option signal X32 is input low. Accordingly, the decoding signal BX12B <0> is determined by the input address BX12TI as shown in Fig. 4A.

On the other hand, if the unit of the IO configuration is large, the byte option signal X32 is input high. Accordingly, the decoding signals BX12B <0: 1> are all low regardless of the value of the input address BX12TI, and the address A12 is treated as Don Care as shown in FIG. 4B.

FIG. 8 is a detailed circuit diagram of the block controller 400 of FIG. 6.

Each of the block controllers 400 includes PMOS transistors P1 to P3 and NMOS transistors N1 to N3 to implement a noah (or oa) circuit.

Here, the PMOS transistors P1 to P3 are connected in series between the power supply voltage terminal and the NMOS transistor N2. The PMOS transistor P1 receives an active control signal ACS through its gate terminal, the PMOS transistor P2 receives a block select signal MSB through its gate terminal, and the PMOS transistor P3 receives a decoding signal BX12B through its gate terminal.

NMOS transistors N1 to N3 are connected in parallel between the PMOS transistor P3 and the ground voltage terminal. The NMOS transistor N1 receives an active control signal ACS through its gate terminal, the NMOS transistor N2 receives a block select signal MSB through its gate terminal, and the NMOS transistor N3 receives a decoding signal BX12B through its gate terminal.

In addition, the driving signal OUT is output through the common drain terminal of the PMOS transistor P3 and the NMOS transistor N2.

That is, when the active control signal ACS, the block selection signal MSB and the decoding signal BX12B are low, the PMOS transistors P1 to P3 are turned on to output the drive signal OUT high, and the active control signal ACS, the block selection signal MSB and the decoding signal BX12B are When high, the NMOS transistors N1 to N3 are turned on and the drive signal OUT is output low.

According to the present invention having such a configuration, various IO configurations are possible in a single unit, and in a DRAM product in which the minimum number of address bits required corresponding to each configuration exists, the byte option signal X32 has a maximum IO configuration. The number of addresses to be decoded is determined in accordance with the minimum number of address bits required.

In addition, the number of address bits required increases when the IO configuration is minimal. In this case, each address bit is decoded by one bit and used to select a minimum unit group of memory cells. For example, in the embodiment of the present invention, the input address A12 is decoded to generate a decoded signal BX12B <0: 1>, which is separately decoded by the BX12 address decoder 100 and used to select a group of memory cells.

Accordingly, the present invention can reduce the number of wirings of the block select signal MSB <0: 7> and the decode signal BX12B <0: 1> in comparison with the conventional block select signal MSB <0:15>.

As described above, the present invention provides the following effects.

First, the number of addresses required to select the minimum unit group of the semiconductor memory cell varies depending on the IO configuration. By reducing the number of block selection signals by the decoding operation corresponding thereto, the wiring of the internal transmission signal can be reduced.

Second, the smallest IO configuration eliminates the need to decode the maximum number of addresses, thereby reducing the area of the decoding circuitry and thus reducing the overall chip area.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (7)

A first address decoder configured to output a first group of decoded signals by decoding a predetermined byte option signal and a first address according to an input / output configuration; A second address decoder configured to decode a signal of a second address group and output a decoded signal of a second group; A driving unit driving the second group of decoding signals to generate a block selection signal; And And a plurality of control blocks for determining whether to operate the corresponding block according to the decoding signal of the first group and the block selection signal and outputting control signals to the cell block and the sense amplifier array. Address coding apparatus. The address coding apparatus of claim 1, wherein one or two control blocks are selected by the byte option signal and one block selection signal. The method of claim 1, wherein the first address decoder is When the byte option signal is low, the decoding signal of the first group is output by the first address. When the byte option signal is high, all the decoding signals of the first group are low regardless of the first address. And the first address is controlled in a don care state. The method of claim 3, wherein the first address decoder is A first noah gate for novating the inverted first address and the non-inverted delayed byte option signal; A second NOR gate for performing a nil operation on the byte option signal that is non-inverted delayed with the first address; A first inverter unit for outputting a first decoding signal by non-inverting a delay of the output of the first NOR gate; And And a second inverter unit for outputting a second decoding signal by non-inverting a delay of the output of the second NOR gate. The method of claim 1, wherein each of the control blocks A block controller which receives an active control signal, the block selection signal and the decoding signal of the first group, and outputs an operation signal differently according to whether a corresponding control block is selected; And And a control signal generator for outputting the control signal for driving the cell block and the sense amplifier array according to whether the operation signal is activated. 6. The address coding apparatus of claim 5, wherein the block controller is a circuit for performing a no operation on the active control signal, the block selection signal, and the decoded signal of the first group. 6. The address coding apparatus of claim 5, wherein the block controller is a circuit for performing an operation on the active control signal, the block selection signal, and the decoding signal of the first group.

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