KR100669348B1 - Nor flash memory device and data transfer method thereof - Google Patents

Abstract

A NOR flash device and a data transmission method thereof is provided to suppress a difference between precharge voltages of adjacent data lines by performing a precharge process after equalizing the data lines. A NOR flash device includes a cell array(110), a sense amplifier(120), a data output unit(150), plural data lines(130), and a precharge unit(140). The cell array includes plural memory cells. The sense amplifier senses and amplifiers the data, which are stored on the memory cells. The data output unit receives the data from the sense amplifier and outputs the received data to the outside. The data lines couple the sense amplifier with the data output unit. The precharge unit precharges the data lines. The precharge unit sets first and second data lines at first and second voltages, respectively, and equalizes the first and second data lines during a data line precharge process.

Description

NOR flash device and its data transfer method {NOR FLASH MEMORY DEVICE AND DATA TRANSFER METHOD THEREOF}

1 is a circuit diagram illustrating a NOR flash memory device according to the present invention.

FIG. 2 is a timing diagram for describing an operation of the NOR flash memory device illustrated in FIG. 1.

* Explanation of symbols for main parts of drawings *

110: cell array 111, 112: memory cell

120: sense amplifier 122, 124: sense amplifier

126, 128: tri-state buffer 130: data line

140: precharge unit 141: precharge circuit

142: discharge circuit 143: equalization circuit

150: data output section 152, 154: tri-state buffer

156, 158: latch output section

The present invention relates to a semiconductor memory device, and more particularly to a NOR flash memory device and a data transfer method thereof.

Recent semiconductor memory devices are becoming highly integrated and large in capacity, whether volatile (e.g., DRAM or SRAM) or non-volatile (e.g., flash memories), and are designed to support high-speed systems.

The flash memory device has low power consumption and freely inputs and outputs information, which is suitable for mobile devices such as digital cameras, mobile phones, and PDAs. Flash memory devices are roughly divided into NAND and NOR types according to the cell array structure. NAND flash memory devices are data storage type memory devices, and are mainly used in USB storage devices and MP3 players. On the other hand, the NOR flash memory device is a code storage type memory device, and is widely used in mobile phone terminals requiring high-speed data processing because of its high processing speed.

Memory cells storing data in a NOR flash memory device include cell transistors. Each cell transistor has a control gate and a floating gate. The NOR flash memory device requires some time for storing information because the NOR flash memory device stores information using a tunneling phenomenon through an insulating film.

With the recent development of technology, as the time for storing information is getting shorter, the data transmission speed in the data input / output device, which has not been a problem in terms of speed, is rapidly increasing. Accordingly, even in the data input / output device of the NOR flash memory device which did not have a separate precharge means or method, it is necessary to provide a precharge method or means which is advantageous for high speed operation.

In the conventional NOR flash memory device, there are various methods for precharging data lines. These methods include precharging the data line to the supply voltage, precharging the data line to the ground voltage, and precharging to the intermediate voltage level between the supply voltage and the ground voltage.

Among these methods, the method of precharging to an intermediate voltage level makes the basic ready state intermediate in the state of not knowing the data to be transmitted through the data line after precharging, so that data to be transmitted through the data line is high ( In the case of the high level state and the low level state, there is an advantage that the rapid change is small due to the small width of the voltage transition, and thus, the technique is widely preferred to the other two precharge methods.

However, this intermediate voltage level precharge method is cumbersome in that a separate intermediate voltage generation circuit must be provided as compared to the other two methods mentioned above. In particular, when there are many lines that need to be precharged, a large capacity intermediate voltage generation circuit must be provided to precharge many data lines in a short time. Such a large capacity intermediate voltage generation circuit occupies a large amount of space on the semiconductor chip and can generate noise due to sudden power consumption during precharge operation.

In addition, the NOR flash memory device requires a high voltage higher than a power supply voltage during write and read operations, and has a noise-sensitive characteristic due to this feature and structure. Such noise may adversely affect a sense operation that may be performed simultaneously with the precharge operation and a data transmission performed after the precharge operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is a NOR flash memory device capable of precharging a data line to an intermediate level between a supply voltage and a ground voltage without a separate intermediate voltage generation circuit, and data transmission through the same. To provide a way.

The NOR flash memory device according to the present invention for achieving the above object includes a cell array, a sense amplifier, a data output unit, a plurality of data lines, and a precharge unit. The sense amplifier senses and amplifies data stored in the plurality of memory cells. The data output unit receives the data of the sense amplifier and outputs the data to the outside. A plurality of data lines connect the sense amplifier and the data output. The precharge unit precharges the plurality of data lines. During the data line precharge operation, the precharge unit sets different first and second data lines among the plurality of data lines to first and second voltages, respectively, and then sets the first and second data lines. Equalize.

The precharge unit may include: a precharge circuit configured to precharge the first data line to the first voltage; A discharge circuit for discharging the second data line to the second voltage; And an equalization circuit for equalizing the first and second data lines. The equalization circuit is connected between the first and second data lines and equalizes the first and second data lines to an intermediate voltage level of the first and second voltages. The precharge circuit is connected between a power supply terminal and the first data line and provides the first data line with the first voltage input through the power supply terminal in response to a precharge signal. The first voltage is a power supply voltage VCC. The discharge circuit is connected between a ground terminal and the second data line and provides the second data line with the second voltage input through the ground terminal in response to a discharge signal.

A data transfer method of a NOR flash memory device according to the present invention, the NOR flash memory device comprising: a cell array having a plurality of memory cells; A sense amplifier for sensing and amplifying data stored in the plurality of memory cells; A data output unit configured to receive data from the sense amplifier and output the data to the outside; A plurality of data lines configured to transmit data of the sense amplifier to the data output unit; And a precharge unit for precharging the plurality of data lines. And a data transfer method of the NOR flash memory device includes sensing and amplifying data stored in the plurality of memory cells; Precharging the first and second data lines adjacent to each other among the plurality of data lines to first and second voltages, and then equalizing the first and second data lines to the same voltage level; And transmitting the data sensed and amplified by the sense amplifier to the data output unit through the plurality of precharged data lines.

In an embodiment, in the data sensing and amplifying step, the output terminal of the sense amplifier is in a floating state Hi-Z.

In another embodiment, the precharge step includes precharging the first data line to the first voltage; Discharging the second data line to the second voltage; And

Equalizing the first and second data lines. The first voltage is a power supply voltage VCC and the second voltage is a ground voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

1 is a circuit diagram illustrating a NOR flash memory device according to an exemplary embodiment of the present invention. Referring to FIG. 1, the NOR flash memory device 100 according to the present invention includes a cell array 110, a sense amplifier 120, a data line unit 130, a precharge unit 140, and a data output unit ( 150).

The cell array 110 is composed of a plurality of memory cells. Only two memory cells 111 and 112 are shown in FIG. The memory cells 111 and 112 are connected to the word line WL and the bit lines BL0 and BL1. The memory cells 111 and 112 receive a positive voltage of about 1V to the bit lines BL0 and BL1 and a positive voltage of about 4.5V to the word lines during a read operation. The programmed cell is called an 'off cell' and stores data "0". The erased cell is called an "on cell" and stores data "1". Depending on whether the memory cells 111 and 112 are OFF cells or ON cells, the amount of current flowing to the memory cells 111 and 112 during a read operation varies.

The sense amplifier 120 includes sense amplifiers 122 and 124 and three-state buffers 126 and 128. The sense amplifiers 122 and 124 sense amplify data stored in the memory cells 111 and 112. The tri-state buffers 126 and 128 transfer the output data of the sense amplifiers 122 and 124 to the data lines 131 and 132 in response to the data output enable signal DOE. The tri-state buffers 126 and 128 maintain the floating state Hi-Z while precharging the data lines 131 and 132.

The data line unit 130 is composed of data lines 131 and 132. Referring to FIG. 1, the data lines 131 and 132 include resistors and capacitors, which model parasitic resistances and parasitic capacitors that are additionally present in the data lines 131 and 132. When the data lines 131 and 132 transfer data from the tri-state buffers 126 and 128, such parasitic resistances and incidental effects of the parasitic capacitors may cause problems such as a slow data transfer rate. .

The precharge unit 140 is connected to the data lines 131 and 132. Referring to FIG. 1, the precharge unit 140 includes a precharge circuit 141, a discharge circuit 142, and an equalization circuit 143. The precharge circuit 141 is connected between the power supply terminal and the data lines DL0 and 131. The precharge circuit 141 is configured of a PMOS transistor and precharges the data line DL0 to the power supply voltage VCC in response to the precharge signal PRE. The discharge circuit 142 is connected between the ground terminal and the data lines DL1 and 132. The discharge circuit 142 is configured of an NMOS transistor and discharges the data line DL1 to the ground voltage 0V in response to the discharge signal DIS. The equalizing circuit 143 is connected between the two data lines DL0 and DL1. The equalizing circuit 143 is composed of NMOS transistors and equalizes the two data lines DL0 and DL1 to the same voltage in response to the equalizing signal EQZ.

The data output unit 150 includes three-state buffers 152 and 154 and latch output units 156 and 158. The tri-state buffers 152 and 154 output data transferred through the data lines DL0 and DL1 in response to the data latch enable signal DLE. The latch output units 156 and 158 store data output from the tri-state buffers 152 and 154 and output the stored data to the outside.

As described above, the sense amplifiers 122 and 124 sense data, the tri-state buffers 126 and 128 transmit the sensed data to the data lines DL0 and DL1, and the data output unit 150 transmits the sensed data. Latch. Here, the data lines DL0 and DL1 are set by the precharge circuit 141 and the discharge circuit 142, and then charge-charge by the equalizing circuit 143. Precharged to an intermediate voltage level.

The data lines DL0 and DL1 precharged to the intermediate voltage level have different levels depending on sensed data from the sense amplifiers 122 and 124. When the memory cells 111 and 112 are ON cells, they are discharged to a ground voltage, and when the memory cells 111 and 112 are OFF cells, they are precharged to a power supply voltage. In this case, the voltage level of the data lines DL0 and DL1 is changed from the intermediate voltage VCC / 2 to the power supply voltage VCC or the ground voltage 0V. At this time, the voltages of the data lines DL0 and DL1 swing only by the intermediate voltage VCC / 2.

FIG. 2 is a timing diagram for describing an operation of the NOR flash memory device illustrated in FIG. 1. As illustrated in FIG. 2, the precharge operation of the data lines DL0 and DL1 of the NOR flash memory device 100 illustrated in FIG. 1 is generally performed in the standby period T1, the setting period T2, and the equalization period T3. ), It is divided into a transmission waiting section (T4), a data transmission section (T5), and a data output section (T6). Each operation section will be described in detail as follows.

The waiting section T1 is a section waiting for the next operation after the previous data transmission or before the first data transmission. Referring to FIG. 2, in the waiting period T1, the data lines DL0 and DL1 are in a 0V state.

The setting section T2 is a section for precharging or discharging the data lines DL0 and DL1. As described above in FIG. 1, when the low level precharge signal PRE is applied to the precharge circuit 141, the data line DL0 is precharged to the power supply voltage VCC. On the other hand, when the high level discharge signal DIS is applied to the discharge circuit 142, the data line DL1 is discharged to 0V.

The equalizing period T3 is a period for setting the data lines DL0 and DL1 to an intermediate voltage level by the charge recycling method. When the high level equalization signal EQZ is applied to the equalization circuit 143, the data lines DL0 and DL1 share a charge and are set to an intermediate voltage level without a separate reference voltage generation circuit.

The transmission waiting section T4 is a waiting section until the equalizing operation is stabilized, and is a section waiting for data transmission. Referring to FIG. 2, the data lines DL0 and DL1 are stabilized to the intermediate voltage level VCC / 2 during the transmission waiting period T4.

The data transmission section T5 is a section for transmitting data from the sense amplifier 120 to the data output unit 150. 2, a high level data output enable signal DOE is applied to the tri-state buffers 126 and 128 of the sense amplifier 120 during the data transmission period T5. At this time, if the memory cell is an ON cell, the voltage level of the data line decreases, and if the memory cell is an OFF cell, it rises.

The data output section T6 is a section for outputting data to the outside. 2, a high level data latch enable signal DLE is applied to the tri-state buffers 152 and 154 of the data output unit 150 during the data output period T6. In this case, the latch output units 156 and 158 store data output from the tri-state buffers 152 and 154 and output the stored data to the outside.

According to the NOR flash memory device 100 according to the present invention, in the precharge operation of the data lines DL0 and DL1, the level of the data lines DL0 and DL1 has a swing width equal to that of the intermediate voltage. Compared to the full swing, the swing width is smaller, and the precharge speed can be increased. In addition, the power consumption due to the small swing width is also reduced, thereby reducing the possibility of power supply noise. In the precharge operation of the data lines DL0 and DL1, a separate large capacity intermediate voltage generation circuit is not required. In addition, since the precharge circuit 141, the discharge circuit 142, and the equalization circuit 143 are distributed and connected to the data lines DL0 and DL1, there are significant advantages in terms of area and power supply noise.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, the NOR flash memory device may precharge the data line to an intermediate voltage level without a separate intermediate voltage generation circuit. Therefore, according to the present invention, since the intermediate voltage generation circuit is not required, a great advantage can be obtained in the area of the semiconductor memory chip, the power consumption can be reduced by the power consumed in the intermediate voltage generation circuit, and the entire semiconductor memory chip can be obtained. By distributing the precharge operation, the overall noise characteristics of the chip can be improved. The precharge operation is performed through the equalization operation between adjacent data lines, and the precharge voltage difference due to the process difference between adjacent data lines can be improved. There is an advantage to overcome.

Claims (13)

A cell array having a plurality of memory cells; A sense amplifier for sensing and amplifying data stored in the plurality of memory cells; A data output unit configured to receive data from the sense amplifier and output the data to the outside; A plurality of data lines connecting the sense amplifier and the data output unit; And A precharge unit configured to precharge the plurality of data lines, During the data line precharge operation, the precharge unit sets different first and second data lines among the plurality of data lines to first and second voltages, respectively, and then sets the first and second data lines. NOR flash memory device characterized by equalizing. The method of claim 1, And the first and second data lines are adjacent to each other. The method of claim 2, The precharge unit A precharge circuit for precharging the first data line to the first voltage; A discharge circuit for discharging the second data line to the second voltage; And A NOR flash memory device comprising an equalization circuit for equalizing the first and second data lines. The method of claim 3, wherein The equalizing circuit is connected between the first and second data lines, and equalizes the first and second data lines to an intermediate voltage level of the first and second voltages. . The method of claim 3, wherein The precharge circuit is connected between a power supply terminal and the first data line and provides the first data line with the first voltage input through the power supply terminal in response to a precharge signal. Memory device. The method of claim 5, The first voltage is a NOR flash memory device, characterized in that the power supply voltage (VCC). The method of claim 3, wherein The discharge circuit is connected between a ground terminal and the second data line, and the NOR flash provides the second data line with the second voltage input through the ground terminal in response to a discharge signal. Memory device. The method of claim 1, And the sense amplifying unit comprises a tri-state buffer configured to provide sensed amplified data to the data output unit in response to a data output enable signal. In the data transfer method of the NOR flash memory device: The NOR flash memory device A cell array having a plurality of memory cells; A sense amplifier for sensing and amplifying data stored in the plurality of memory cells; A data output unit configured to receive data from the sense amplifier and output the data to the outside; A plurality of data lines configured to transmit data of the sense amplifier to the data output unit; And A precharge unit configured to precharge the plurality of data lines, The data transfer method of the NOR flash memory device is Sensing and amplifying data stored in the plurality of memory cells; Precharging the first and second data lines adjacent to each other among the plurality of data lines to first and second voltages, and then equalizing the first and second data lines to the same voltage level; And And transmitting the data sensed and amplified by the sense amplifier to the data output unit through the plurality of precharged data lines. The method of claim 9, In the data sensing and amplifying step, the output terminal of the sense amplifier is in a floating state (Hi-Z). The method of claim 9, The precharge step, Precharging the first data line to the first voltage; Discharging the second data line to the second voltage; And Equalizing the first and second data lines. The method of claim 11, And wherein the first voltage is a power supply voltage (VCC). The method of claim 11, And the second voltage is a ground voltage.

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