KR100667077B1 - Thin film transistor and fabricating for the same - Google Patents

Abstract

A thin film transistor and a method for manufacturing the same are provided to reduce the edge effect, completely remove the kink effect, and achieve an excellent threshold voltage characteristic. A semiconductor layer is disposed on a substrate, wherein the semiconductor layer includes source and drain regions, a channel region positioned between the source and drain regions, an edge region connected to a portion of the channel region, and a body region(202B) connected to the edge region. A gate insulating layer is disposed on the channel region of the semiconductor layer. A gate electrode is disposed on the gate insulating layer. An interlayer insulating film is disposed on the gate electrode. A wire part(215SB) is disposed on the interlayer insulating film, and connects the source region and the body region. The wire part is capable of connecting the gate electrode and the body region.

Description

Thin film transistor and its manufacturing method {Thin film transistor and fabricating for the same}

1A is a cross-sectional view of a thin film transistor formed by the prior art, and FIG. 1B is a plan view of FIG. 1A.

2A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 2B is a plan view of FIG. 2A.

3A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 3B is a plan view of FIG. 3A.

4A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 4B is a plan view of FIG. 4A.

5A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 5B is a plan view of FIG. 5A.

6A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 6B is a plan view of FIG. 6A.

7A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 7B is a plan view of FIG. 7A.

8A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 8B is a plan view of FIG. 8A.

9 is a graph showing the characteristics of the thin film transistor formed by the embodiment of the present invention.

10A is a cross-sectional view of a manufacturing process of a thin film transistor according to another embodiment of the present invention, and FIG. 10B is a plan view of FIG. 10A.

11A is a cross-sectional view of a manufacturing process of a thin film transistor according to another embodiment of the present invention, and FIG. 11B is a plan view of FIG. 11A.

12 is a graph showing the characteristics of a thin film transistor formed by another embodiment of the present invention.

13A is a cross-sectional view of a manufacturing process of a thin film transistor according to still another embodiment of the present invention, and FIG. 13B is a plan view of FIG. 13A.

14A is a cross-sectional view of a manufacturing process of a thin film transistor according to still another embodiment of the present invention, and FIG. 14B is a plan view of FIG. 14A.

 <Description of the symbols for the main parts of the drawings>

202S: first source region 202D: first drain region

202C: first channel region 202E: edge region

202B: body region 203S: second source region

203D: Second drain region 203L: LDD region

215SB: Source-body wiring 215GB: Gate-body wiring

215SBG: Source-body-gate wiring

The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a thin film transistor and a method for manufacturing the same, which can reduce edge effects, completely eliminate the kink effect, and obtain excellent threshold voltage characteristics.

Recently, a liquid crystal display device, an organic electroluminescence device, or a plasma display plane, which solve the shortcomings of the conventional display device, which are heavy and large, such as a cathode ray tube. A flat panel display device, such as), has attracted attention.

At this time, since the liquid crystal display is not a light emitting device but a light receiving device, there is a limit in brightness, contrast, viewing angle, and large area, and although the PDP is a self-light emitting device, it is heavier than other flat panel display devices and consumes more weight. On the other hand, the organic electroluminescent device is excellent in viewing angle, contrast, etc., because it is a self-luminous device, and because it does not require a backlight, it is possible to be light and thin, and in terms of power consumption. It is advantageous.

In addition, since it is possible to drive a DC low voltage, a fast response speed, and all solid, it is resistant to external shock, wide use temperature range, and has a simple and inexpensive manufacturing method.

Flat Plane Displays, such as organic electroluminescent display devices or liquid crystal display devices, may be used as switching elements or driving elements, and may be thin film transistors. Transistor) is used.

1A is a cross-sectional view of a thin film transistor formed by the prior art, and FIG. 1B is a plan view of FIG. 1A.

1A and 1B, a buffer layer 101 is positioned on a substrate 100 such as glass or plastic, and a source / drain region 102a and a source / drain region doped with P-type impurities are disposed on the buffer layer 101. A first semiconductor layer 102 including a channel 102b located between the drain regions 102a, a source / drain region 103a doped with N-type impurities, and a channel located between the source / drain region 103a. A second semiconductor layer 103 including a region 103b and a lightly doped drain (LDD) region 103c positioned between the source / drain region 103a and the channel region 103b is located.

A gate insulating film 104 is disposed on the first semiconductor layer 102 and a second semiconductor layer 103, and the first semiconductor layer 102 and the second semiconductor layer 103 are disposed on the gate insulating film 104. Each of the gate electrodes 105 and 106 is positioned at a position corresponding to the channels 102b and 103b of the interlayer, and an interlayer insulating layer 107 is formed to protect the gate electrodes 105 and 106.

The source / drain electrodes filling and contacting the contact holes 108 exposing predetermined regions of the source / drain regions 102a and 103a of the first semiconductor layer 102 and the second semiconductor layer 103. 109 and 110 are disposed on the interlayer insulating film 107.

In this case, the thin film transistor including the first semiconductor layer 102 is a P-type thin film transistor and the thin film transistor including the second semiconductor layer 103 is an N-type thin film transistor. The P-type or N-type thin film transistor as described above may be used as a switching or driving element of a flat panel display device. In this case, the thin film transistor used as a driving element of the flat panel display device needs to remove elements that hinder the characteristics of the device such as edge effect, kink effect, and bipolar juction transistor (BJT), but the thin film transistors formed by the prior art are structurally This has the disadvantage that it is not easy to solve.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, and has an edge region and a body region doped with impurities of a type opposite to the source / drain region, and the body region and the gate electrode or / and It is an object of the present invention to provide a thin film transistor having a wiring portion in contact with a source region and a method of manufacturing the same.

The object of the present invention is a substrate; A semiconductor layer on the substrate, the semiconductor layer including a source region and a drain region, a channel region located between the source region and a drain region, an edge region connected to a predetermined region of the channel region, and a body region connected to the edge region; A gate insulating layer on the channel region of the semiconductor layer; A gate electrode on the gate insulating film; An interlayer insulating film on the gate electrode; And a thin film transistor disposed on the interlayer insulating film, the wiring portion connecting one or more of the source region and the gate electrode to the body region.

The object of the present invention is a substrate; A first channel region positioned on the substrate and positioned between a first source region and a first drain region, a first channel region located between the first source region and a first drain region, an edge region connected to a predetermined region of the first channel region, and the edge region A first semiconductor layer comprising a body region connected to the first semiconductor layer; A second channel region, a second channel region, a second source region, and a second drain region, the second source region and the second drain region; A first semiconductor layer including an LDD region located between a region and the second channel; A gate insulating film disposed on the first semiconductor layer and the second semiconductor layer; First and second gate electrodes positioned on the gate insulating layer and positioned at positions corresponding to the first channel region and the second channel region, respectively; An interlayer insulating layer on the first gate electrode and the second gate electrode; And a thin film transistor disposed on the interlayer insulating film, the wiring portion connecting one or more of the first source region and the first gate electrode to the body region.

The object of the present invention is to prepare a substrate; Forming a semiconductor layer in which source / drain regions, channel regions, edge regions, and body regions are defined on the substrate; Forming a gate insulating film on the substrate on which the semiconductor layer is formed; Forming a first pattern on the gate insulating layer to expose an edge region and a body region of the semiconductor layer; Performing a first impurity implantation process on the edge region and the body region of the semiconductor layer using the first pattern as a mask; Removing the first pattern and forming a gate electrode on the substrate on which the semiconductor layer is formed; Forming a second pattern on the substrate to cover at least the body region of the semiconductor layer and the gate electrode; Performing a second impurity implantation process on a source / drain region of the semiconductor layer using the second pattern as a mask; Forming an interlayer insulating film on the substrate on which the gate electrode is formed; Exposing a body region of the semiconductor layer and forming contact holes exposing at least one of a source region and a gate electrode of the semiconductor layer; And forming a conductive layer on the substrate and patterning the conductive layer to form a wiring portion connecting at least one of a body region of the semiconductor layer, a source region of the semiconductor layer, and a gate electrode. Is achieved.

The object of the present invention is to prepare a substrate; A first semiconductor layer in which a first source / drain region, a first channel region, an edge region, and a body region are defined and a second semiconductor layer in which a second source / drain region, a second channel, and an LDD region are defined are formed on the substrate. Forming; Forming a gate insulating film on the substrate on which the first semiconductor layer and the second semiconductor layer are formed; Exposing an edge region and a body region of the first semiconductor layer and forming a first pattern on the gate insulating layer to expose a second source / drain region of the second semiconductor layer; Performing a first impurity implantation process on the edge region and the body region of the first semiconductor layer and the second source / drain region of the second semiconductor layer using the first pattern as a mask; Removing the first pattern and forming a first gate electrode and a second gate electrode on the first semiconductor layer and the second semiconductor layer; Performing an LDD implantation process on the LDD region of the second semiconductor layer using the second gate electrode as a mask; Forming a second pattern on the substrate, the second pattern covering at least the body region of the first semiconductor layer, the first gate electrode, and the second semiconductor layer; Performing a second impurity implantation process on a first source / drain region of a first semiconductor layer using the second pattern as a mask; Forming an interlayer insulating film on the substrate on which the first gate electrode and the second gate electrode are formed; Exposing a body region of the first semiconductor layer and forming contact holes exposing at least one of a first source region and a first gate of the first semiconductor layer; And forming a conductive layer on the substrate and patterning the conductive layer to form a wiring portion connecting at least one of a body region of the first semiconductor layer, a first source region of the first semiconductor layer, and a first gate electrode. It is also achieved by a thin film transistor manufacturing method consisting of.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention. In the drawings, the length, thickness, etc. of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout the specification.

<Example 1>

2A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 2B is a plan view of FIG. 2A.

2A and 2B, a buffer layer 201 is formed on a substrate 200 such as glass or plastic. In this case, the buffer layer 201 serves to prevent crystallization of the semiconductor layer by preventing diffusion of moisture or impurities generated from the lower substrate or by controlling the rate of heat transfer during crystallization.

Subsequently, a first semiconductor layer 202 and a second semiconductor layer 203 are formed on the buffer layer 201. In this case, the first semiconductor layer 202 and the second semiconductor layer 203 may include a rapid thermal annealing (RTA) process, a solid phase crystallization (SPC) method, an excimer laser crystallization (ELA) method, and a metal induced crystallization (MIC) method. It may be formed of a polycrystalline silicon layer crystallized by a crystallization method such as, for example, MILC (Metal Induced Lateral Crystallization) or SLS (Sequential Lateral Solidification). In addition, the first semiconductor layer 202 and the second semiconductor layer 203 may be a silicon layer doped with a P type or N type when formed on a substrate.

In this case, as shown in FIG. 2B, the first semiconductor layer 202 includes a region A in which a body region is to be formed, and a region B in which a first source / drain region, a first channel region, and an edge region are to be formed. The second semiconductor layer 203 is formed to include the second source / drain region, the second channel region, and the region C on which the LDD region is to be formed. I will explain in detail accordingly.)

Subsequently, a gate insulating film 204 is formed on the substrate on which the first semiconductor layer 202 and the second semiconductor layer 203 are formed. In this case, the gate insulating film 204 may be formed using any one of an oxide film, a nitride film, and a multilayer thereof.

3A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 3B is a plan view of FIG. 3A.

3A and 3B, a photoresist is coated on a substrate on which the gate insulating layer 204 is formed, and an exposure process is performed to produce an edge region 202E and a body region 202B of the first semiconductor layer 202. ) And a first pattern 205 exposing the second source / drain regions 203S and 203D of the second semiconductor layer 203.

In this case, a portion of the first pattern 205 formed on the first semiconductor layer 202 should cover a region where the first channel region and the first source / drain region of the first semiconductor layer 202 are to be formed. The portion formed on the second semiconductor layer 203 should cover the region where the second channel region and the LDD region of the second semiconductor layer 203 are to be formed.

Subsequently, an edge region 202E and a body region 202B of the first semiconductor layer 202 and a second source / drain region of the second semiconductor layer 203 using the first pattern 205 as a mask. A high concentration of first impurity injection step 206 is performed at 203S and 203D. In this case, the impurity implanted by the first impurity implantation process 206 is an impurity of a different type from the impurity doped into the first semiconductor layer 202 and the second semiconductor layer 203. That is, when the impurity doped in the first semiconductor layer 202 and the second semiconductor layer 203 is P-type, the impurity implanted by the first impurity implantation process 206 is N-type and P-type. Use N type.

In this case, the edge region 202E of the first semiconductor layer 202 generally forms a silicon layer over the entire substrate when the first semiconductor layer 202 is formed, and forms a photoresist pattern on the silicon layer. After forming, the semiconductor layer is formed by etching the silicon layer using the photoresist pattern as a mask. When the silicon layer is etched, an edge portion of the semiconductor layer is formed on an etching solution or plasma used for etching. Not only are they damaged, but the characteristics of the semiconductor layer become uneven or worsen due to residual photoresist or the like. Accordingly, the thin film transistor including the semiconductor layer changes characteristics such as a threshold voltage or an S-factor, and a hump occurs in an IV curve representing the characteristics of the thin film transistor. Will cause problems. The above problem occurs because the damaged edge portion is used as a channel, and thus, as in the present invention, the edge portion (especially, the edge portion adjacent to the channel region) is doped with the channel region and the source / drain region and the edge region doped with other impurities. By changing to 202E, the current flows only into the channel region and can be solved.

4A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 4B is a plan view of FIG. 4A.

4A and 4B, the first pattern 205 of FIG. 3A is removed and formed on the gate insulating layer 204, but not on the first semiconductor layer 202 and the second semiconductor layer 203. The first gate electrode 207 and the second gate electrode 208 are formed at positions corresponding to the first gate electrode 207 and the second gate electrode 208.

In this case, the first gate electrode 207 is formed at a position corresponding to the first semiconductor layer 202, so that the first semiconductor layer 202 has a first channel region 202C and a first source / drain. Regions 202S and 202D are defined, and the second gate electrode 208 is formed at a position corresponding to the second semiconductor layer 203, so that the second channel layer 203C is formed in the second semiconductor layer 203. ) And second source / drain regions 203S and 203D, and a width of the second gate electrode 208 is formed on the second semiconductor layer 203 of a portion of the first pattern 205. The LDD region 203L is defined as smaller than the width of.

Subsequently, an LDD implantation process 209 is performed on the substrate 200 using the first gate electrode 207 and the second gate electrode 208 as masks.

In this case, the LDD implantation process 209 is implanted with the same impurities as the first impurity implantation 206 of FIG. 3A, but is implanted at a concentration lower than that of the first impurity implantation process 206. This means that the concentration of impurities implanted into the LDD region 203L of the second semiconductor layer 203 must be lower than the concentration of impurities implanted into the second source / drain regions 203S and 203D of the second semiconductor layer 203. Because.

5A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 5B is a plan view of FIG. 5A.

5A and 5B, a photoresist is applied on a substrate on which the gate electrodes 207 and 208 are formed, and then an exposure process is performed to at least the body region 202B of the first semiconductor layer 202. And a second pattern 210 completely covering the edge region 202E under the first gate electrode 207 and completely covering the second semiconductor layer 203. In this case, in FIG. 5B, the body region 202B, the first gate electrode 207 (the edge region 202E under the first gate electrode 207 is also covered) and the entire second semiconductor layer 203 are covered. Although the second pattern 210 is illustrated, forming the second pattern 210 covering the body region 202B, the edge region 202E, the first gate electrode 207 and the second semiconductor layer 202. desirable. That is, it is preferable to form the second pattern 210 which opens only the region defined as the first source / drain region among the regions of the first semiconductor layer 202. This is to prevent the edge effect of the edge region 202E occurring in the semiconductor layer below the edge of the first gate electrode 207.

Subsequently, a second impurity implantation process 211 is performed on the first source / drain regions 202S and 202D of the first semiconductor layer 202 using the second pattern 210 as a mask.

Accordingly, the edge region E and the body region 202B of the first semiconductor layer 202 may be formed by the first impurity implantation process 206, the LDD implantation process 209, and the second impurity implantation process 211. Impurities of the same type are implanted into the second source / drain regions 203S and 203D and the LDD region 203L of the second semiconductor layer 203. However, due to the different impurity implantation process, the concentration of impurity implanted is different. That is, the concentration of the impurities injected into the LDD region 203L is lower than that of the impurities injected into other regions.

6A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 6B is a plan view of FIG. 6A.

6A and 6B, the second pattern 210 is removed and an interlayer insulating film 212 is formed on a substrate on which the first gate electrode 207 and the second gate electrode 208 are formed.

7A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 7B is a plan view of FIG. 7A.

7A and 7B, the interlayer insulating film 212 and the gate insulating film 204 are etched to expose predetermined regions of the first source / drain regions 202S and 202D of the first semiconductor layer 202. Contact holes 213S and 213D, a contact hole 213B exposing a predetermined region of the body region 202B of the first semiconductor layer 202 and a second source / drain region of the second semiconductor layer 203. Contact holes 214S and 214D exposing predetermined regions of 203S and 203D are formed.

8A is a cross-sectional view of a manufacturing process of a thin film transistor according to an embodiment of the present invention, and FIG. 8B is a plan view of FIG. 8A.

8A and 8B, a conductive layer is formed on a substrate on which contact holes 213S, 213D, 213B, 214S, and 214D formed by etching the interlayer insulating film 212 and the gate insulating film 204 are formed. A first drain electrode 215D patterned to contact the first drain region 202D of the first semiconductor layer 202, a first source region 202S of the first semiconductor layer 202, and the first semiconductor Source-body wirings 215SB connecting the body region 202B of the layer 202 and second source / drain contacting the second source / drain regions 203S and 203D of the second semiconductor layer 203. Electrodes 216S and 216D are formed. In this case, although not referring to forming the first source electrode, if necessary, a first source electrode connected to the first source region 202S of the first semiconductor layer 202 may be formed.

As the size of the thin film transistor decreases as the flat panel display becomes higher, a hot carrier is generated in the drain region adjacent to the channel by a latent electric Feil (LEF) in the drain region at a low drain voltage, and the hot carriers Impingement ionization and propagation of carriers, i.e., electron-hole pairs, occur and avalanche multiplication in which the carriers continuously move into the channel region. The avalanche proliferation causes problems such as a sudden increase in drain current due to a kink effect, a change in threshold voltage, and a deterioration in a thin film transistor.

The above problem can be seen as a Bipolar Juction Transistor (BJT) effect, which is connected to the first channel region 202C through the edge region 202E of the first semiconductor layer 202 as in the present invention. This can be solved by connecting the body region 202B and the first source region 202S with the source-body wiring portion 215SB. In other words, electron-hole pairs generated in the first channel region 202C and the first drain region 202D by the LEF are defined by the edge region 202E, the body region 202B, and the source-body wiring portion 202SB. The BJT effect in the first drain region 202D can be completely eliminated by moving to the first source region 202S through the reference numeral.

That is, the source-body wiring part 202SB connecting the first channel region 202C and the first source region 202S as shown in FIG. 9, which is a graph showing the characteristics of the thin film transistor formed by the exemplary embodiment of the present invention. ), The drain current (I ₁ ) of the thin film transistor formed by the prior art has less kink effect even at a higher drain voltage (V _D ) than the drain current (I ₂ ) of the thin film transistor formed by the prior art, so that the breakdown due to the kink effect does not occur. Therefore, it can be seen that excellent drain current characteristics are shown. That is, when the first channel region 202C and the first source region 202S are connected to the source-body interconnection portion 202SB, the kink effect can be removed by removing the parasitic BJT.

In the graph of FIG. 9, when the gate voltage V _G of 0.5V is applied to the first gate electrode 207 and the drain voltage V _D applied to the drain electrode 215D is changed, the channel region is changed. The current flowing through 202C, that is, the drain current I _D was measured.

 <Example 2>

In the process of <Example 2>, the process of forming the interlayer insulating film of <Example 1>, that is, the manufacturing process described with reference to FIGS. 2A through 6B is formed in the same method and thus omitted. That is, the same method as in <Example 1> is performed until the process of forming the interlayer insulating film 212 on the substrate.

10A is a cross-sectional view of a manufacturing process of a thin film transistor according to another embodiment of the present invention, and FIG. 10B is a plan view of FIG. 10A.

10A and 10B, the interlayer insulating layer 212 is etched to form a contact hole 213G exposing a predetermined region of the first gate electrode 207, and the interlayer insulating layer 212 and the gate insulating layer are formed. Contact holes 213S and 213D exposing predetermined regions of the first source / drain regions 202S and 202D of the first semiconductor layer 202 and the first semiconductor layer 202. Contact holes 213B exposing a predetermined region of the body region 203B and contact holes 216S and 216D exposing a predetermined region of the second source / drain regions 203S and 203D of the second semiconductor layer 203. ).

11A is a cross-sectional view of a manufacturing process of a thin film transistor according to another embodiment of the present invention, and FIG. 11B is a plan view of FIG. 12A.

11A and 11B, a conductive layer is formed on a substrate on which the contact holes 213S, 213D, 213G, 213B, 214S, and 214D are formed, and then patterned to form a conductive layer of the first semiconductor layer 202. The first source / drain electrodes 215S and 215D contacting the first source / drain regions 202S and 202D, and the body region 202B of the first gate electrode 105 and the first semiconductor layer 202. Second source / drain electrodes 216S and 216D are formed to contact the gate-body wiring unit 215GB to be connected and the second source / drain regions 203S and 203D of the second semiconductor layer 203. In this case, although not referring to forming the first source electrode, if necessary, a first source electrode connected to the first source region 202S of the first semiconductor layer 202 may be formed.

As a conventional thin film transistor used in a flat panel display device has a smaller size, a threshold voltage is lowered. As a result, not only the saturation region of the drain current is reduced but also the drain current is reduced. This problem can be solved by forming a gate-body contact portion 215GB connecting the channel region and the gate electrode of the semiconductor layer.

The threshold voltage of the thin film transistor is dependent on the substrate bias. In general, the substrate bias is reverse bias for the source, so the threshold voltage is increased. By connecting the channel region 202C and the first gate electrode 207 as described above, the influence of the reverse bias is eliminated and the threshold voltage can be reduced as well as the slope of the sub-threshold voltage can be improved. have.

That is, as shown in FIG. 12, which is a graph illustrating characteristics of the thin film transistor formed according to another exemplary embodiment of the present invention, a pattern including a gate-body wiring portion 215 GB connecting the first channel region 202C and the gate electrode is formed. It can be seen that the drain current I _D (I ₃ ) of the thin film transistor of the present invention shows a high amount of current even at a low gate voltage (V _G ) compared to the drain current (I ₄ ) of the thin film transistor formed by the prior art. It also shows that a low sub-threshold voltage swing can be obtained. In addition, it is shown that the variation of the threshold voltage can reduce the dispersion of the current characteristics of the thin film transistor in the substrate.

In this case, the graph of FIG. 12 fixes the drain voltage V _D applied to the drain electrode to 5 V, and the drain current I _D value that changes as the gate voltage V _G applied to the gate electrode changes. It is a result of a measurement.

 Example 3

Of the process of <Example 3>, the process of forming the interlayer insulating film of <Example 1>, that is, the fabrication process described with reference to FIGS. 2A to 6B is formed in the same manner and thus omitted. That is, the same method as in <Example 1> is performed until the process of forming the interlayer insulating film 212 on the substrate.

13A is a cross-sectional view of a manufacturing process of a thin film transistor according to still another embodiment of the present invention, and FIG. 13B is a plan view of FIG. 13A.

13A and 13B, the interlayer insulating layer 212 is etched to form a contact hole 213G exposing a predetermined region of the first gate electrode 207, and the interlayer insulating layer 212 and the gate insulating layer are formed. Contact holes 213S and 213D exposing the first source / drain regions 202S and 202D of the first semiconductor layer 202 by etching the 204, and a body region of the first semiconductor layer 202. Forming contact holes 213B exposing a predetermined region of 202B and contact holes 214S and 214D exposing predetermined regions of the second source / drain regions 203S and 203D of the second semiconductor layer 203. do.

14A is a cross-sectional view of a manufacturing process of a thin film transistor according to still another embodiment of the present invention, and FIG. 14B is a plan view of FIG. 14A.

14A and 14B, a conductive layer is formed on a substrate on which the contact holes 213S, 213D, 213G, 213B, 214S, and 214D are formed, and then patterned to form a conductive layer of the first semiconductor layer 202. The first source electrode 215S that contacts the first source region 202S, the first source region 202S and the body region 202B of the first gate electrode 105 and the first semiconductor layer 202 are disposed. Forming second source / drain electrodes 216S and 216D in contact with the source-body-gate wiring portion 215SBG to be connected and the second source / drain regions 203S and 203D of the second semiconductor layer 203. . In this case, although not referring to forming the first source electrode, if necessary, a first source electrode connected to the first source region 202S of the first semiconductor layer 202 may be formed.

In this case, the source-body-gate interconnection unit 215SBG connects the channel region 202C and the first source region 202S described in Embodiment 1 to the source-body interconnection unit 202SB. In addition to removing the kink effect by removing the parasitic BJT, the channel region 202C and the first gate electrode 207 described in Embodiment 2 are connected to the gate-body wiring portion 215GB. In this way, the characteristics of <Example 1> and <Example 2> such as a high channel current amount and a low sub-threshold voltage swing value may be simultaneously achieved even at a low gate voltage.

The present invention has been shown and described with reference to the preferred embodiments as described above, but is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

Therefore, the thin film transistor of the present invention and the method of manufacturing the same reduce the edge effect, completely eliminate the kink effect, high channel current amount, low sub-threshold voltage swing even at low gate voltage, excellent threshold voltage characteristics and the dispersion of the current characteristics of the thin film transistor The present invention relates to a thin film transistor and a method for manufacturing the same, which can achieve an effect such as a decrease in the number of layers.

Claims (14)

Board; A semiconductor layer on the substrate, the semiconductor layer including a source region and a drain region, a channel region located between the source region and a drain region, an edge region connected to a predetermined region of the channel region, and a body region connected to the edge region; A gate insulating layer on the channel region of the semiconductor layer; A gate electrode on the gate insulating film; An interlayer insulating film on the gate electrode; And And a wiring part disposed on the interlayer insulating layer and connecting one or more of the source region and the gate electrode to the body region. The method of claim 1, And the source region and the drain region are semiconductor layers doped with impurities of the same type as the channel region, but doped at a higher concentration than the impurity concentration of the channel region. The method of claim 1, And the edge and body regions are doped with impurities of a type opposite to that of the channel region. Board; A first channel region positioned on the substrate and positioned between a first source region and a first drain region, a first channel region located between the first source region and a first drain region, an edge region connected to a predetermined region of the first channel region, and the edge region A first semiconductor layer comprising a body region connected to the first semiconductor layer; A second channel region, a second channel region, a second source region, and a second drain region, the second source region and the second drain region; A first semiconductor layer including an LDD region located between a region and the second channel; A gate insulating film disposed on the first semiconductor layer and the second semiconductor layer; First and second gate electrodes positioned on the gate insulating layer and positioned at positions corresponding to the first channel region and the second channel region, respectively; An interlayer insulating layer on the first gate electrode and the second gate electrode; And And a wiring part disposed on the interlayer insulating layer and connecting one or more of the first source region and the first gate electrode to the body region. The method of claim 4, wherein The first source region and the first drain region are doped with impurities of the same type as the first channel region and the second channel region but doped with a high concentration of impurities. The method of claim 4, wherein And the second source region and the second drain region are doped with impurities of a different type from the first source region and the second drain region. The method of claim 4, wherein The edge region and the body region may be doped with impurities of the same type as the second source region and the second drain region. Preparing a substrate; Forming a semiconductor layer in which source / drain regions, channel regions, edge regions, and body regions are defined on the substrate; Forming a gate insulating film on the substrate on which the semiconductor layer is formed; Forming a first pattern on the gate insulating layer to expose an edge region and a body region of the semiconductor layer; Performing a first impurity implantation process on the edge region and the body region of the semiconductor layer using the first pattern as a mask; Removing the first pattern and forming a gate electrode on the substrate on which the semiconductor layer is formed; Forming a second pattern on the substrate to cover at least the body region of the semiconductor layer and the gate electrode; Performing a second impurity implantation process on a source / drain region of the semiconductor layer using the second pattern as a mask; Forming an interlayer insulating film on the substrate on which the gate electrode is formed; Exposing a body region of the semiconductor layer and forming contact holes exposing at least one of a source region and a gate electrode of the semiconductor layer; And Forming a conductive layer on the substrate and patterning the conductive layer to form a wiring portion connecting at least one of a body region of the semiconductor layer, a source region of the semiconductor layer, and a gate electrode; Manufacturing method. The method of claim 8, The impurity implanted by the first impurity implantation process is an impurity of a type opposite to the impurity doped in the channel region. The method of claim 8, The impurity implanted by the second impurity implantation process is an impurity of a different type from the impurity implanted by the first impurity implantation well. Preparing a substrate; A first semiconductor layer in which a first source / drain region, a first channel region, an edge region, and a body region are defined and a second semiconductor layer in which a second source / drain region, a second channel, and an LDD region are defined are formed on the substrate. Forming; Forming a gate insulating film on the substrate on which the first semiconductor layer and the second semiconductor layer are formed; Forming a first pattern on the gate insulating layer to expose an edge region and a body region of the first semiconductor layer and expose a second source / drain region of the second semiconductor layer; Performing a first impurity implantation process on the edge region and the body region of the first semiconductor layer and the second source / drain region of the second semiconductor layer using the first pattern as a mask; Removing the first pattern and forming a first gate electrode and a second gate electrode on the first semiconductor layer and the second semiconductor layer; Performing an LDD implantation process on the LDD region of the second semiconductor layer using the second gate electrode as a mask; Forming a second pattern on the substrate, the second pattern covering at least the body region of the first semiconductor layer, the first gate electrode, and the second semiconductor layer; Performing a second impurity implantation process on a first source / drain region of a first semiconductor layer using the second pattern as a mask; Forming an interlayer insulating film on the substrate on which the first gate electrode and the second gate electrode are formed; Exposing a body region of the first semiconductor layer and forming contact holes exposing at least one of a first source region and a first gate of the first semiconductor layer; And Forming a conductive layer on the substrate and patterning the conductive layer to form a wiring portion connecting at least one of a body region of the first semiconductor layer, a first source region of the first semiconductor layer, and a first gate electrode; Thin film transistor manufacturing method comprising a. The method of claim 11, The impurity implanted by the LDD implantation process is an impurity of the same type as the impurity implanted by the first impurity implantation process but has a low concentration. The method of claim 11, The impurity implanted by the first impurity implantation process is an impurity of a type opposite to the impurity doped in the channel region. The method of claim 11, The impurity implanted by the second impurity implantation process is an impurity of a different type from the impurity implanted by the first impurity implantation well.

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