KR100667041B1 - Flip flop - Google Patents

Abstract

A flip-flop is provided to reduce power consumption by removing an unnecessary charging and discharging effect and a glitch effect of internal nodes. A first transistor includes a first electrode connected with a first power source, a control electrode for receiving an input signal, and a second electrode. A second transistor includes a first electrode connected with the second electrode of the first transistor, a control electrode for receiving a clock signal, and a second electrode connected with a first node. A third transistor includes a first electrode connected with the first node, a control electrode for receiving the input signal, and a second electrode connected with a second power source. A fourth transistor includes a first electrode connected with the first power source, a control electrode for receiving the clock signal, and a second electrode connected with a second node. A fifth transistor includes a first electrode connected with the second node, a control electrode connected with the first node, and a second electrode connected with a third node. A sixth transistor includes a first electrode connected with the third node, a control electrode for receiving the clock signal, and a second electrode connected with the second power source. A seventh transistor includes a first electrode connected with the first power source, a control electrode connected with the second node, and a second electrode connected with an output node. An eighth transistor includes a first electrode connected with the output node, a control electrode for receiving the clock signal, and a second electrode. A ninth transistor includes a first electrode connected with the second electrode of the eighth transistor, a control electrode connected with the second node, and a second electrode connected with the third node.

Description

Flip-flop {FLIP FLOP}

1 and 4 show a conventional flip-flop, respectively.

2 and 3 are signal timing diagrams of the flip-flop of FIG. 1, respectively.

5 is a signal timing diagram of the flip-flop of FIG. 4.

6 is a view showing a flip-flop according to an embodiment of the present invention.

7A to 7D are diagrams illustrating an operation of the flip-flop of FIG. 6 according to an input signal and a clock signal, respectively.

8 is a signal timing diagram of the flip-flop of FIG. 6.

9 is a signal timing diagram of the flip-flop of FIG. 6.

FIG. 10 is a table comparing the flip-flops according to the exemplary embodiment of the present invention shown in FIG. 6 with the conventional flip-flops shown in FIGS. 1 and 4.

The present invention relates to flip-flops, and more particularly, to a True Single Phase Clock (TSPC) D-flip flop.

Recently, a circuit that satisfies high-speed operation and low power characteristics is required, and a dynamic logic gate or a clocked logic gate having a clock signal input has been used as such a circuit. In the dynamic CMOS circuit technology, the D flip-flop using the TSPC method has only one type of clock signal, and there is no clock signal skew in addition to the clock signal delay, and the flip-flop structure is simple.

The structure of a conventional flip-flop is briefly described with reference to the accompanying drawings.

1 is a diagram illustrating a conventional flip-flop, and FIGS. 2 and 3 are signal timing diagrams at respective nodes CLK1, D1, A10, B10, QB10, and Q10 of the flip-flop of FIG. 1, respectively. 4 is a view illustrating another conventional flip-flop, and FIG. 5 is a signal timing diagram at each node CLK2, D2, A20, B20, C20, QB20, and Q20 of the flip-flop of FIG. 4.

1 shows a representative structure of a conventional flip-flop, and FIG. 4 shows a structure of a conventional flip-flop in which glitches are removed using a TSPC latch structure.

First, in the flip-flop of FIG. 1, as illustrated in FIG. 2, a glitch phenomenon occurs in which the output node QB10 is discharged and charged in a specific period P1. The causes of such glitches are as follows.

When the clock signal CLK1 transitions from the low level to the high level when the input signal D1 is at the low level, the node B10 is discharged and the transistor MP14 is turned on, thereby determining the output node QB10 at the high level. . However, at this time, it takes some time for the charge of the node B10 to be discharged through the discharge path composed of the transistors MN12 and MN13 immediately after the clock signal CLK1 transitions to the high level. As a result, as shown in FIG. 2, a case where the node B10 and the clock signal CLK1 overlap in a high level occurs instantaneously. At this time, the transistors MN14 and MN15 are turned on so that the output node QB10 is instantaneously. Glitches occur after being discharged and then recharged. This glitch not only causes unnecessary power consumption of the flip-flop itself, but also causes abnormal state of logic blocks connected to the flip-flop.

Also, as shown in FIG. 3, it can be seen that the output node QB10 has an incorrect value during some periods P2 and P3. This is because the flip-flop is sensitive to the clock signal CLK1 slope.

When the clock signal CLK1 transitions from the low level to the high level while the input signal D1 is at the low level, the output node QB10 is determined to be at the high level. Then, when the clock signal CLK1 transitions from the high level to the low level, the time at which the node B10 is determined to be at the high level by the transistor MP13 is very fast while the slope of the clock signal CLK1 is gentle. ) Is turned on to some extent. Therefore, a section in which the transistors MN14 and MN15 are turned on occurs, and the output node QB10 discharges momentarily. And the value of this wrong output node (QB10) will continue to maintain the value until the next charge and the problem of passing the wrong value to the logic block of the next stage.

In addition, in the flip-flop structure of FIG. 1, it can be seen that the transition path from the low level to the high level and the transition path from the high level to the low level of the output node QB10 are structurally different. In other words, when the output node QB10 transitions from the high level to the low level, the node B10 has a desired level before the rising time of the clock signal CLK1. However, when transitioning from the low level to the high level, the level of the node B10 is determined only when the clock signal CLK1 rises, and then does not affect the output. Therefore, the transition from the low level to the high level has a relatively longer propagation delay time than the transition from the high level to the low level. In addition, the delay time becomes longer because the charging operation of the output node QB10 is not immediately performed at the moment when the transistor MP14 is turned on by the glitch phenomenon but after being discharged for a while. Therefore, the delay time from the low level to the high level and the delay time from the high level to the low level of the output node QB10 are asymmetric, which limits the operation speed of the flip-flop.

Meanwhile, FIG. 4 illustrates a flip-flop in which glitches are removed by using a TSPC latch structure. In order to solve the above-mentioned problems, the flip-flop stabilizes a malfunctioning node by changing a circuit structure.

This structure improves the glitches by using the discharge suppression scheme and makes the propagation delay time symmetrical, which makes it more suitable for higher speed operation than the typical flip flop. However, the structure shows good characteristics in terms of speed, but poor in terms of power consumption.

As shown in FIG. 5, the nodes A20 and B20 are precharged to a high level when the clock signal CLK2 is at a low level and the input signal D2 is at a high level. At this time, when the clock signal CLK2 transitions to the high level, as the transistor MN25 is turned on and the node A20 is discharged, the transistor MN22 is turned off and the node B20 must maintain the high level. do. However, some time is required for the node A20 to discharge, and at this moment, the node B20 is momentarily discharged through the path formed by the transistors MN22 and MN25. The value is maintained until the clock signal CLK2 transitions to the low level (P4).

In addition, when the input signal D2 is in the high level section, the node A20 is charged and discharged due to the level transition of the clock signal CLK2 (P5). This is an operation originating from the structure in which the charging of the node A20 is independent of the input terminal, and is an unnecessary operation not seen in the existing structure. Unnecessary charging and discharging of the internal node causes power consumption to increase.

Accordingly, the present invention has been made in view of the above problems, and provides a flip-flop that minimizes power consumption by removing unnecessary charge / discharge phenomena and glitches of an internal node.

In addition, it provides a flip-flop that speeds up the operation speed by symmetrically inducing a low to high level delay time and a high to low level delay time of the output node.

According to a feature of the present invention to achieve the above-described problem, the flip-flop,

A first transistor having a first electrode connected to a first power source, a control electrode receiving an input signal, and a second electrode; A second transistor having a first electrode connected to the second electrode of the first transistor, a control electrode receiving a clock signal, and a second electrode connected to a first node; A third transistor having a first electrode connected to the first node, a control electrode receiving the input signal, and a second electrode connected to a second power source; A fourth transistor having a first electrode connected to the first power source, a control electrode receiving the clock signal, and a second electrode connected to a second node; A fifth transistor having a first electrode connected to the second node, a control electrode connected to the first node, and a second electrode connected to a third node; A sixth transistor having a first electrode connected to the third node, a control electrode receiving the clock signal, and a second electrode connected to the second power source; A seventh transistor having a first electrode connected to the first power source, a control electrode connected to the second node, and a second electrode connected to an output node; An eighth transistor having a first electrode connected to the output node, a control electrode receiving the clock signal, and a second electrode; And a ninth transistor having a first electrode connected to the second electrode of the eighth transistor, a control electrode connected to the second node, and a second electrode connected to the third node.

According to another feature of the invention, the flip-flop,

And having a first node, precharging the first node to a high level voltage in response to a first level of an input signal and a second level of a clock signal, wherein the first node is precharged in response to a third level of the input signal. A first stage for discharging the high level voltage; And a second node and a third node, and precharges the second node to a high level voltage in response to the second level of the clock signal, and drives the third node in response to the fourth level of the clock signal. A second discharge path forming a first discharge path for discharging, and forming a second discharge path for discharging the high level voltage of the second node through the first discharge path in response to the high level voltage of the first node; stage; And an output node, charging the output node to a high level voltage in response to a low level voltage of the second node, and the fourth level and the second level of the clock signal when the first discharge path is formed. And a third stage forming a third discharge path for discharging the charging voltage of the output node through the first discharge path in response to the high level voltage of the node.

According to another feature of the invention, the flip-flop,

A first clock type CMOS connected between the first power supply and the second power supply, the first clock type CMOS inverting the input signal and outputting the inverted signal to the first node when the clock signal changes from the first level to the second level; A first transistor connected between the first power supply and the second node and turned on in response to the first level of the clock signal; A second transistor connected between the second node and the third node and operating in response to a voltage of the first node; A third transistor connected between the third node and the second power supply and turned on in response to the second level of the clock signal; A second clock type CMOS connected between the first power supply and the third node and inverting and outputting an output signal of the second node when the clock signal is changed from the second level to the first level; Include.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

Now, a flip-flop according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

6 is a circuit diagram of a flip-flop according to an embodiment of the present invention.

As shown in FIG. 6, the flip-flop according to the exemplary embodiment of the present invention includes a first stage 100, a second stage 200, and a third stage 300. In this case, the first and third stages 100 and 300 have different types of clocked CMOS (CMOS) structures. The first stage 100 includes two P-channel transistors MP31 and MP32 and one N-channel transistor MN31, and the second stage 200 includes one P-channel transistor MP33 and two N. The channel transistors MN32 and MN35 are included, and the third stage 300 includes one P-channel transistor MP34 and two N-channel transistors MN33 and MN34.

In FIG. 6, these transistors MP31-MP34 and MN31-MN35 are illustrated as metal oxide silicon (MOS) transistors having a source and a drain as two electrodes and a gate as a control electrode.

In detail, the first electrode of the transistor MP31 is connected to a power supply VDD supplying a high level voltage, and the control electrode of the transistor MP31 receives the input signal D3.

In the transistor MP32, a first electrode is connected to the second electrode of the transistor MP31, receives a clock signal CLK3 through a control electrode, and a second electrode is connected to the first node A30.

The transistor MN31 has a first electrode connected to the first node A30, receives an input signal D3 through a control electrode, and a second electrode connected to a power supply supplying a low level voltage. In FIG. 6, a power supply supplying a low level voltage is illustrated as a ground terminal supplying a ground voltage.

The transistor MP33 is connected to a power source to which a first electrode supplies a high level voltage, receives a clock signal CLK3 through a control electrode, and a second electrode is connected to a second node B30.

In the transistor MN32, a first electrode is connected to the second node B30, a control electrode is connected to the first node A30, and a second electrode is connected to the third node C30.

The transistor MN35 is connected to a power source having a first electrode connected to the third node C30, receiving a clock signal CLK3 through a control electrode, and a second electrode supplying a low level voltage.

The transistor MP34 is connected to a power source to which a first electrode supplies a high level voltage, a control electrode is connected to a second node B30, and a second electrode is connected to an output node QB30.

The transistor MN33 has a first electrode connected to the output node QB30 and receives a clock signal CLK3 through the control electrode.

In the transistor MN34, a first electrode is connected to the second electrode of the transistor MN33, a control electrode is connected to the second node B30, and a second electrode is connected to the third node C30.

In this case, the inverter 400 is connected to the output node QB30 to invert and output the signal of the output node QB30 so that the flip-flop of FIG. 6 may operate as a D flip-flop.

Next, the operation of the flip-flop of FIG. 6 will be described with reference to FIGS. 7A to 7D.

7A to 7D are diagrams illustrating the operation of the flip-flop of FIG. 6 according to the input signal D3 and the clock signal CLK3, respectively. 7A and 7B illustrate an operation of flip-flop when the clock signal CLK3 is at the low level or the high level CLK3 when the input signal D3 is at the low level. 7C and 7D show the flip-flop operation when the clock signal CLK3 is at the low level or the high level CLK3 when the input signal D3 is at the high level.

As shown in FIG. 7A, first, when the input signal D3 is low level and the clock signal CLK3 is low level, the transistors MP31, MP32, and MP33 are turned on and the transistors MN31, MN35, and MN33 are turned on. Is off. Then, the high level voltage of the power supply VDD is precharged to the first node A30 through the transistors MP31 and MP32, and the transistor MN32 is responsive to the voltage of the first node A30 precharged to the high level voltage. ) Is turned on. Then, the second node B30 and the third node C30 are precharged to the high level voltage of the power supply VDD through the transistors MP33 and MN32, and in response to the high level voltage of the second node B30. (MP34) is turned off. Since the transistors MP34, MN33, and MN35 are turned off, the charge / discharge path is not formed at the output node QB30, so the output node QB30 maintains the previous value (Hold).

Next, as shown in FIG. 7B, when the clock signal CLK3 transitions to the high level while the input signal D3 maintains the low level, the transistors MP32 and MP33 are turned off and the transistors MN35 and MN33 are turned off. ) Is turned on. Then, a discharge path ① is formed in which the voltage of the third node C30 is discharged by the turned-on transistor MN35, and the voltage of the first node A30 is transferred by the turned-off transistors MP32 and MN31. Maintain the voltage (high level voltage). A discharge path ② is formed through which the precharge voltage of the second node B30 is discharged through the turned-on transistor MN32 and the first discharge path ①. At this time, since the transistor MP34 is turned on and the transistor MN34 is turned off, the output node QB30 is determined to be at a high level by charging the output node QB30. The output signal Q3 of the inverter 400 is determined at the low level.

Meanwhile, as shown in FIG. 7C, when the input signal D3 is at the high level and the clock signal CLK3 is at the low level, the transistors MP32, MN31, and MP33 are turned on and the transistors MP31, MN35, and MN33 are turned on. Is turned off. Then, the voltage of the first node A30 is discharged through the transistor MN31. The transistor MN32 is turned off in response to the low level voltage of the first node A30, and the high level voltage of the power supply VDD is precharged to the second node B30 through the turned on transistor MP33. At this time, the transistor MP34 is turned off in response to the high level voltage of the second node B30. Since the charge / discharge path is not formed at the output node QB30 by the turned-off transistors MP34 and MN33, the output node QB30 maintains the previous value (Hold).

Next, when the clock signal CLK3 transitions to the high level while the input signal D3 maintains the high level as shown in FIG. 7D, the transistors MN33 and MN35 are turned on and the transistors MP32 and MP33 are turned on. Is off. Then, the voltage of the first node A30 is maintained at the previous voltage (low level voltage) by the turned off transistor MP32. The voltage of the second node B30 is maintained at the previous voltage (high level voltage) by the turned-off transistors MP33 and MN32. Then, a path (3) through which the turned-on transistors MN33, MN34, MN35 discharges the voltage of the output node QB30 is formed. The charge of the output node QB30 is discharged through this discharge path ③, so that the output node QB30 is determined to be at a low level. The output signal Q30 of the inverter 400 is determined to be at a high level.

As described above, each stage of the flip-flop according to the embodiment of the present invention performs the following functions.

That is, the first stage 100 precharges the first node A30 in response to the low level of the input signal D3 and the low level of the clock signal CLK3, and in response to the high level of the clock signal CLK3. The first node A30 is discharged. The second stage 200 charges the second node B30 in response to the clock signal CLK3 and the high level voltage of the first node A30, or the second node B30 and the third node C30. ) Is discharged. The third stage 300 charges the output node QB30 in response to the low level voltage of the second node B30, or in response to the clock signal CLK3 and the high level voltage of the second node B30. The output node QB30 is discharged.

8 and 9 are signal timing diagrams of a flip-flop according to an embodiment of the present invention, respectively, and FIG. 8 shows a result of experimenting with a clock signal CLK3 having a frequency of 2 GHz and an inclination of 0.01 nsec. 9 shows the results of experiments with a clock signal CLK3 having a frequency of 100 MHz and a slope of 0.8 nsec.

According to FIG. 8, it can be seen that unnecessary discharge of the second node B30 is suppressed. That is, when the clock signal CLK3 transitions from the low level to the high level when the input signal D3 is at the high level, it can be seen that the second node B30 maintains the high level in a stable manner (P11). Since the discharge of the first node A30 is performed only by the transistor MN31 having a control electrode connected to the input terminal, the first node A30 may be quickly discharged regardless of the clock signal CLK3. Therefore, since the transistor MN32 can be turned off before the moment when the transistor MN35 is turned on, the discharge of the second node B30 can be suppressed.

In addition, it can be seen that the phenomenon in which the first node A30 is unnecessarily charged and discharged by the clock signal CLK3 when the input signal D3 is at a high level is suppressed (P12). This is because the transistors MP31 and MP32 that charge the first node A30 are configured to comply with the input signal D3 and the clock signal CLK3. As a result, the transistor MP31 affected by the input signal D3 is input signal. When D3 is at a high level, the charging path is turned off to prevent unnecessary charging and discharging of the first node A30.

In addition, it can be seen that an incorrect discharge phenomenon of the output node QB30, which occurs when the glitch phenomenon and the slope of the clock signal CLK3 are gentle due to the instantaneous discharge phenomenon of the output node QB30 at an undesired instant, is suppressed. (P13). This is because the third node C30 plays a role of preventing such an erroneous discharge. A constant charge is precharged to the third node C30 to prevent the output node QB30 from being discharged unnecessarily, and only after the charge of the third node C30 is discharged, the charge of the output node QB30 is discharged. To help. Therefore, sensitivity to the glitch phenomenon and the slope of the clock signal CLK3 may be alleviated.

Sensitivity to the slope of the clock signal CLK3 is relaxed, as shown in FIG. 9.

According to FIG. 9, even when the clock signal CLK3 inclines having a slope of 0.8 nsec are operated without malfunction, it is shown (P14).

Next, FIG. 10 is a table illustrating comparison between the conventional flip-flop shown in FIGS. 1 and 4 and the flip-flop according to the embodiment of the present invention shown in FIG. 6. Experiments were performed under the same conditions using 0.18 um CMOS process variables. The result is a comparison of the number of transistors, propagation delay time, and power consumption, respectively.

According to FIG. 10, although the number of transistors constituting the flip-flop is similar, the output node QB30 may transition from the low level to the high level compared to the flip-flop having the conventional structure. It can be seen that the delay time and the delay time when the output node QB30 transitions from the high level to the low level are small. In addition, it can be seen that the propagation delay time is closer to symmetry, and the power consumption is also the smallest.

The scope of the present invention is not limited to the above-described embodiment, but various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims are also within the scope of the present invention.

By the above-described configuration, unnecessary charge / discharge phenomena and glitches of the internal nodes can be eliminated. That is, the charge path transistor of the first node is configured to depend on the input signal level, the discharge path transistor is composed of one transistor that depends only on the input signal level, and the low path power is shared by sharing the discharge path transistor of the second node and the output node. It can enable consumption.

In addition, the symmetrical propagation delay time and the operation speed is greatly improved to implement a high-speed prescaler, it can be applied to a variety of applications requiring high-speed operation.

Claims (14)

A first transistor having a first electrode connected to a first power source, a control electrode receiving an input signal, and a second electrode; A second transistor having a first electrode connected to the second electrode of the first transistor, a control electrode receiving a clock signal, and a second electrode connected to a first node; A third transistor having a first electrode connected to the first node, a control electrode receiving the input signal, and a second electrode connected to a second power source; A fourth transistor having a first electrode connected to the first power source, a control electrode receiving the clock signal, and a second electrode connected to a second node; A fifth transistor having a first electrode connected to the second node, a control electrode connected to the first node, and a second electrode connected to a third node; A sixth transistor having a first electrode connected to the third node, a control electrode receiving the clock signal, and a second electrode connected to the second power source; A seventh transistor having a first electrode connected to the first power source, a control electrode connected to the second node, and a second electrode connected to an output node; An eighth transistor having a first electrode connected to the output node, a control electrode receiving the clock signal, and a second electrode; And A ninth transistor having a first electrode connected to the second electrode of the eighth transistor, a control electrode connected to the second node, and a second electrode connected to the third node Flip-flop comprising a. The method of claim 1, The first transistor, the second transistor, the fourth transistor, and the seventh transistor are of a first channel type, And the third transistor, the fifth transistor, the sixth transistor, the eighth transistor, and the ninth transistor are of a second channel type. The method of claim 2, And the first channel type is a P channel, and the second channel type is an N channel. The method according to any one of claims 1 to 3, And the first power supply supplies a higher voltage than the second power supply. The method according to any one of claims 1 to 3, And a inverter coupled to the output node. And having a first node, precharging the first node to a high level voltage in response to a first level of an input signal and a second level of a clock signal, wherein the first node is precharged in response to a third level of the input signal. A first stage for discharging the high level voltage; And a second node and a third node, and precharges the second node to a high level voltage in response to the second level of the clock signal, and drives the third node in response to the fourth level of the clock signal. A second discharge path forming a first discharge path for discharging, and forming a second discharge path for discharging the high level voltage of the second node through the first discharge path in response to the high level voltage of the first node; stage; And Has an output node, charges the output node to a high level voltage in response to a low level voltage of the second node, and the fourth level and the second node of the clock signal when the first discharge path is formed A third stage forming a third discharge path for discharging the charging voltage of the output node through the first discharge path in response to the high level voltage of? Flip-flop comprising a. The method of claim 6, And the first level and the second level are low levels, and the third level and the fourth level are high levels. The method according to claim 6 or 7, The first stage, A path for discharging the first node in response to the third level of the input signal and the first and second transistors connected in series between the first power supplying the high level voltage and the first node; A third transistor to form, And the first transistor is turned on in response to the first level of the input signal and the second transistor is turned on in response to the second level. The method according to claim 6 or 7, The second stage, A fourth transistor that forms a path for precharging the second node in response to the second level of the clock signal, and a fifth transistor that forms the second discharge path in response to the high level voltage of the first node And a sixth transistor forming the first discharge path in response to the fourth level of the clock signal. The method according to claim 6 or 7, The third stage, A seventh transistor forming a path for charging the output node in response to the low level voltage of the second node, and the fourth level of the clock signal and the high level voltage of the second node, respectively; A flip-flop comprising eighth and ninth transistors forming a third discharge path. The method according to claim 6 or 7, And a inverter coupled to the output node. A first clock type CMOS connected between the first power supply and the second power supply, the first clock type CMOS inverting the input signal and outputting the inverted signal to the first node when the clock signal changes from the first level to the second level; A first transistor connected between the first power supply and the second node and turned on in response to the first level of the clock signal; A second transistor connected between the second node and the third node and operating in response to a voltage of the first node; A third transistor connected between the third node and the second power supply and turned on in response to the second level of the clock signal; A second clock type CMOS connected between the first power supply and the third node and inverting an output signal of the second node when the clock signal is changed from the second level to the first level; Flip-flop comprising a. The method of claim 12, And the first level is a voltage level lower than the second level. The method according to claim 12 or 13, And a inverter coupled to the output node.

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