KR100666565B1 - Organic Electroluminescence Display Device and Fabrication Method of the Same - Google Patents

Abstract

The present invention relates to an organic light emitting display device and a method for manufacturing the same, wherein a lower step by a thin film transistor is formed by applying an inorganic planarization film through a high temperature heat treatment process after coating a solution mixed with a polymer and a solvent on a substrate. Improve the step coverage of the first electrode to improve the adhesion and opening ratio of the first electrode, and prevent the rise of surface resistance of the first electrode and the deterioration of the inorganic planarization film when the first electrode is the anode electrode. In addition, pixel shrinkage is prevented by preventing degradation of the organic light emitting layer due to out-gassing phenomenon such as H ₂ 0 and 0 ₂ from the inorganic planarization layer after deposition of the organic layer. And life of the organic light emitting layer can be improved.

Organic light emitting display device, inorganic planarization film, passivation film, pixel definition film

Description

Organic electroluminescent display device and method of manufacturing the same {Organic Electroluminescence Display Device and Fabrication Method of the Same}

1 is a cross-sectional view for explaining a conventional organic light emitting display device and a manufacturing method thereof.

2 is a cross-sectional view for explaining an organic light emitting display device and a method of manufacturing the same according to an embodiment of the present invention.

3 is a cross-sectional photograph of an inorganic planarization film formed on the thin film transistor of the substrate as an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

     300 substrate 310 semiconductor layer

     330: gate electrode 341: contact hole

     345: source / drain electrodes 355: via holes

     360: planarization film 370: first electrode

     375: Pixel defining layer 380: Organic layer

     390: second electrode

      d1: total thickness of the passivation film and the inorganic planarization film

      d2: Total thickness of the source / drain electrode, passivation film, and inorganic planarization film

The present invention relates to an organic light emitting display device and a method of manufacturing the same, and more particularly, to a structure of an inorganic flattening film capable of simultaneously performing a passivation function and a planarization function of a thin film transistor formed on a substrate in an organic light emitting display device; The present invention relates to an organic light emitting display device including an inorganic planarization film formed through a high temperature heat treatment process after coating on a substrate through a coating method using a solution, and a method of manufacturing the same.

In general, among flat panel display devices, an organic electroluminescence display device is self-luminous and has a wide viewing angle, fast response speed, thin thickness, low manufacturing cost, high contrast, and the like. It is attracting attention as a next-generation flat panel display device in the future.

In general, an organic light emitting display device includes an organic light emitting layer between an anode electrode and a cathode electrode so that holes supplied from the anode electrode and electrons received from the cathode electrode combine in the organic light emitting layer to form an exciton, which is a hole-electron pair, again. The excitons emit light by energy generated when the excitons return to the ground state.

In general, an organic light emitting display device is divided into a passive matrix method and an active matrix method according to a method of driving N × M pixels arranged in a matrix form. The anode electrode and the cathode electrode are composed of a simple matrix type device, which is easy to manufacture, but is limited to low resolution and small display applications due to problems such as resolution, an increase in driving voltage, and a decrease in the life of a material. On the other hand, in the active matrix method, the display area is equipped with a thin film transistor for each pixel to supply a stable current regardless of the number of pixels of the organic light emitting display device, thereby showing stable luminance and low power consumption, thereby applying high resolution and large display. It has the advantage of being advantageous.

In addition, the organic light emitting display device is divided into a bottom emission type and a top emission type according to a direction in which light emitted from the organic light emitting layer is emitted. In the bottom emission type, light is emitted to the formed substrate, and a reflective electrode is disposed on the organic emission layer. The transparent electrode is formed below the organic light emitting layer. Here, when the organic light emitting display device adopts an active matrix method, the portion where the thin film transistor is formed may not transmit light, thereby reducing the area where light can be emitted. On the other hand, in the front emission type, since a transparent electrode is formed on the organic light emitting layer and a reflective electrode is formed on the organic light emitting layer, light is emitted in a direction opposite to the substrate side, so that the light transmitting area is widened, so that the luminance can be improved. Can be.

1 is a cross-sectional view illustrating a conventional active organic light emitting display device and a method of manufacturing the same.

Referring to FIG. 1, in a conventional active organic light emitting display device, a semiconductor layer 110 including source / drain regions 110c and 110a and a channel region 110b is formed on a substrate 100. A gate insulating layer 120 is formed on the semiconductor layer 110, and a gate electrode 130 is formed on the gate insulating layer 120 to correspond to the channel region 110b. An interlayer insulating layer 140 is formed on the gate electrode 130 over the entire substrate, and a source / drain region of the semiconductor layer 110 is formed through the contact hole 141 formed in the interlayer insulating layer 140. (110c, 110a) and the source / drain electrodes 141 are connected to form a thin film transistor.

A passivation film 150 is formed over the entire surface of the source / drain electrode 145, and a planarization film 160 may be further included to planarize the substrate. A via hole 155 is formed in the passivation layer 150 and the planarization layer 160 to expose any one of the source / drain electrodes 145, and the source / drain electrode 145 is formed through the via hole 155. The first electrode 170 is formed to be in contact with each other.

Subsequently, a pixel definition layer 175 having an opening 178 is formed over the entire substrate including the first electrode 170, and includes at least an organic light emitting layer on the first electrode exposed in the opening 178. An organic film layer 180 is formed.

Subsequently, a second electrode 190 is formed over the entire organic layer 180.

In this case, the passivation layer 150 is typically formed to protect the thin film transistor from contamination of the upper portion, and an inorganic insulating layer such as silicon nitride layer (SiNx), silicon oxide layer (SiO ₂ ), or a double layer thereof (SiO ₂ / SiNx). To form.

The passivation film 150 is formed by a chemical vapor deposition (CVD) method, such as plasma-enhanced chemical vapor deposit (PECVD), low-pressure chemical vapor deposition (LPCVD), and atmospheric pressurization chemical vapor deposition (APCVD). The film is formed using a deposition apparatus, and in this case, since the film is uniformly deposited along the lower step, the planarization property is poor, which is caused by the topologies of the lower patterns of the passivation film 150, in particular, the contact hole 141. Have a goal. For this reason, in the case of the top emission type structure, the planarization layer 160 should generally be further formed on the passivation layer 150 to compensate for the planarization characteristic.

In addition, since the planarization layer 160 uses an organic insulating layer such as polyimide (PI), polyamide (PA), acrylic resin, benzocyclobutene (BCB), or phenol resin, The organic light emitting layer is easily deteriorated by the outgassing phenomenon such as H ₂ 0, 0 ₂ from the planarization film due to the deterioration of the planarization film into the organic layer after the deposition of the organic layer in the subsequent process and the deposition of the organic layer in the subsequent process. It has a problem of shortening the pixel shrinkage phenomenon and life of the organic light emitting layer.

The technical problem to be achieved by the present invention is to solve the above problems of the prior art, due to the passivation film having only the passivation function of the thin film transistor because the planarization characteristics are poor to be laminated on the upper portion of the passivation An organic light emitting display device including an inorganic planarization film capable of performing a passivation function of a thin film transistor instead of the organic planarization film, and a manufacturing method thereof are provided.

The present invention to achieve the above object,

Board,

A thin film transistor formed on the substrate,

A passivation film further formed on the thin film transistor,

An inorganic planarization film formed on the passivation film,

A first electrode formed on the inorganic planarization film,

A pixel definition layer formed over the first electrode and having an opening;

An organic layer including at least an organic light emitting layer on the first electrode, and

A second electrode formed on the organic layer;

The inorganic planarization film simultaneously performs the passivation function of the thin film transistor and the planarization function of the substrate through lower level offset, and is formed by applying a solution by a coating method and then performing a high temperature heat treatment process. to provide.

In addition, the present invention

Providing a substrate;

Forming a thin film transistor on the substrate;

Further forming a passivation film on the thin film transistor;

Forming an inorganic planarization film on the passivation film;

Forming a first electrode on the inorganic planarization film;

Forming a pixel definition layer having an opening on the first electrode;

Forming an organic layer including at least an organic light emitting layer on the first electrode; And

Forming a second electrode on the organic layer;

The inorganic planarization film is also achieved by a method of manufacturing an organic light emitting display device, characterized in that the solution is uniformly coated on the thin film transistor by a coating method and then formed through a high temperature heat treatment process.

Hereinafter, the present invention will be described in more detail.

2 is a cross-sectional view of a unit pixel of an organic light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the organic light emitting display device of the present invention may include a buffer layer 305 on the substrate 300. The buffer layer 305 is formed on the substrate 300 to protect the thin film transistor formed in a subsequent process from impurities flowing out of the substrate. The buffer layer 305 is not necessarily stacked, but may be formed of a silicon oxide film, a silicon nitride film, or a double layer in which the buffer layer 305 is stacked.

Subsequently, the semiconductor layer 310 including the source / drain regions 310c and 310a and the channel region 310b is patterned on the buffer layer 305. The semiconductor layer 310 may be formed of amorphous silicon or polycrystalline silicon, but is preferably formed of polycrystalline silicon.

Subsequently, a gate insulating layer 320 is formed over the entire substrate including the semiconductor layer 310. The gate insulating layer 320 may be formed of a silicon oxide layer, a silicon nitride layer, or a double layer thereof.

Subsequently, a gate electrode 330 corresponding to a predetermined region of the semiconductor layer 310 is formed on the gate insulating layer 320. The gate electrode 330 is formed of a polysilicon film formed of amorphous silicon or polycrystalline silicon. Subsequently, an impurity is implanted into the semiconductor layer 310 using a mask, thereby forming source / drain regions 310c and 310a in the semiconductor layer, and simultaneously between the source / drain regions 310c and 310a. The intervening channel region 310b is defined.

Subsequently, an interlayer insulating layer 340 is formed over the entire substrate including the gate electrode 330. The interlayer insulating film 340 may be formed of a silicon oxide film, a silicon nitride film, or a double layer thereof.

Subsequently, contact holes 341 are formed in the interlayer insulating layer 340 to expose the source / drain regions 310c and 310a, respectively. The source / drain electrodes 345 are formed by stacking and patterning a metal film on the source / drain regions 310c and 310a and the interlayer insulating layer 340 exposed in the contact holes 341.

As described above, the semiconductor layer 310, the gate 330, and the source / drain electrodes 345 constitute a thin film transistor.

Subsequently, an inorganic planarization layer 360 is formed on the substrate on which the source / drain electrodes 345 are formed. The inorganic planarization film 360 is formed of an inorganic film. Preferably, the inorganic planarization film 360 is formed of a silicon oxide film (SiO ₂ ). At this time, the silicon nitride film (SiNx) cannot be laminated in a liquid phase by mixing materials.

When the inorganic planarization film 360 is formed too thin, less than 1 μm, the planarization function of the inorganic planarization film is decreased, and when the inorganic planarization film 360 is formed too thick, more than 2 μm, cracks may occur due to stress during the heat treatment process. ) Is generated, it is preferable to form a thickness of 1㎛ to 2㎛.

The inorganic planarization layer 360 simultaneously performs a passivation function of the thin film transistor and a planarization function of the substrate, and improves step coverage of the first electrode by canceling a lower step to improve adhesion of the first electrode. It improves the aperture ratio, prevents the increase of the surface resistance of the first electrode and the deterioration of the inorganic planarization film when the first electrode is an anode electrode, and also when the conventional organic planarization film is used after deposition of the organic film layer in a subsequent process, By preventing the deterioration of the organic light emitting layer due to the outgassing phenomenon such as H ₂ O, 0 ₂ from the inorganic planarization film into the film layer it is possible to prevent the pixel shrinkage phenomenon and to improve the life of the organic light emitting layer.

Here, a passivation film 350 may be further formed below the inorganic planarization film 360. The passivation film 350 is formed of a silicon nitride film (SiNx).

Subsequently, a via hole 355 is formed in the inorganic planarization layer 360 to expose any one of the source / drain electrodes 345.

Subsequently, a first electrode 370 is formed to contact the source / drain electrode 345 through the via hole 355.

In the case of the anode, the first electrode 370 may be a transparent electrode made of ITO or IZO having a high work function or a transparent electrode including a reflective film made of a metal having high reflectivity such as aluminum or an aluminum alloy in a lower layer. have. When the first electrode is a cathode electrode, a conductive metal having a low work function is a material selected from the group consisting of Mg, Ca, Al, Ag, and alloys thereof, or a reflective electrode having a thick thickness, or having a thin thickness. It may be a reflective electrode.

Subsequently, a pixel definition layer 375 having an opening 378 is formed over the entire substrate including the first electrode 370. The pixel defining layer 375 may use an organic or inorganic type, and the organic type is one selected from the group consisting of polyimide (PI), polyamide (PA), acrylic resin, benzocyclobutene (BCB) or phenol resin. And SiO ₂ is used as the inorganic system.

Subsequently, an organic layer 380 including at least an organic light emitting layer is formed on the first electrode exposed in the opening 378. The organic layer 380 may include at least one of a hole injection layer, a hole transport layer, a hole suppression layer, an electron transport layer, and an electron injection layer in addition to the organic light emitting layer.

Subsequently, a second electrode 390 is formed over the entire organic layer 380. When the first electrode 370 is a transparent electrode that is an anode or a transparent electrode that includes a reflective film, the second electrode 390 is a conductive metal having a low work function and made of Mg, Ca, Al, Ag, and an alloy thereof. One material selected from the group is formed as a reflective electrode, and when the first electrode 370 is a cathode, it is formed as a transparent electrode such as ITO or IZO.

On the other hand, if the first electrode 370 is a cathode electrode, the second electrode 390 becomes an anode electrode, the layer structure is inversely the structure described above.

Hereinafter, a method of manufacturing the organic light emitting display device according to the present invention will be described.

2, the manufacturing method provides a substrate 300. The substrate 300 is a transparent insulating substrate such as glass, plastic, or quartz.

Subsequently, a buffer layer 305 is formed on the substrate 300. The buffer layer It is formed by performing a method such as plasma chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

Subsequently, the semiconductor layer 310 including the source / drain regions 310c and 310a and the channel region 310b is patterned on the substrate 300.

The semiconductor layer 310 is formed by depositing amorphous silicon using a chemical vapor deposition (CVD) method, crystallizing a polysilicon film using a crystallization method, and then patterning the amorphous silicon. The CVD method may use a chemical vapor deposition method such as PECVD, LPCVD. In this case, when the amorphous silicon is performed by PECVD, a process of lowering hydrogen concentration by performing dehydrogenation by heat treatment after deposition of a silicon film is performed.

In addition, the crystallization method of the amorphous silicon film may be RTA (Rapid Thermal Annealing) process, SPC (Solid Phase Crystallization), ELA (Excimer Laser Crystallization), MIC (Metal Induced Crystallization), SLS (Sequential Lateral Solidification) or MILC Any one or more of the methods (Metal Induced Lateral Crystallization) may be used.

Subsequently, the gate insulating layer 320 is formed over the entire semiconductor layer 310. The gate insulating layer 320 is stacked by performing a method such as PECVD or LPCVD.

Subsequently, a gate electrode 330 is formed on the gate insulating layer 320 to correspond to the channel region 310b. When the gate electrode 330 is formed of a polysilicon layer, the gate electrode 330 is formed in the same manner as in the method of forming the semiconductor layer 310 using amorphous silicon or polycrystalline silicon.

Subsequently, an impurity is implanted into the semiconductor layer 310 using a mask, thereby forming source / drain regions 310c and 310a in the semiconductor layer, and simultaneously between the source / drain regions 310c and 310a. The intervening channel region 310b is defined.

The impurity is formed by selecting from p ⁺ type such as boron fluoride (BF ₂ ⁺ ), boron ion (B ⁺ ) or n ⁺ type such as arsenic (AS ⁺ ) or phosphorus (P ⁺ ).

Subsequently, an interlayer insulating film 340 is formed over the entire substrate including the gate electrode 330. The interlayer insulating layer 340 is stacked by performing a method such as PECVD or LPCVD.

Subsequently, contact holes 341 are formed in the interlayer insulating layer 340 to expose the source / drain regions 310c and 310a, respectively. The source / drain electrodes 345 are formed by stacking and patterning a metal film on the source / drain regions 310c and 310a and the interlayer insulating layer 340 exposed in the contact holes 341.

Subsequently, an inorganic planarization layer 360 is formed on the substrate on which the source / drain electrodes 345 are formed. More preferably, the planarization 360 is formed of a silicon oxide film SiO ₂ .

The inorganic planarization film 360 is formed through a high temperature heat treatment process after applying the solution through a coating method.

The solution for forming the inorganic planarization film 360 is made by mixing each polymer with a solvent in a different composition ratio, methyl siloxane to the solvent propylene glycol monomethyl ether acetate (PGMEA) (Metyl siloxane) is formed of a solution of 10wt% to 20wt% or a solution of hydrosilsilsesquioxane (HSQ; Hydrogen silsesquioxane) in a solvent (PGMEA) of 5wt% to 35wt%.

In order to form the inorganic planarization layer 360, the solution is uniformly coated on the substrate by a spin coating method.

The solution applied on the substrate is subjected to spin speed of the coating equipment at 100 rpm to 1300 rpm for 1 second to 30 seconds to form a uniform film having a thickness of 1 μm to 2 μm.

When the spin speed is less than 1 second at 100 rpm or less, the thickness of the planarization film is too thick to be 2 μm or more, and when the thickness is less than 30 seconds to 1300 rpm or more, the thickness of the planarization film is too thin to be 1 μm or less. It is desirable to hold seconds to 30 seconds.

The solution coated on the substrate is subjected to a heat treatment process of keeping time 1/2 hour to 1 hour at a high temperature of 200 ° C to 300 ° C.

Since the film uniformly coated by the solution starts to harden at 200 ° C. or more and exceeds 300 ° C., the film exceeds the glass transition temperature (Tg) of the substrate, so that the heat treatment temperature is preferably maintained at 200 ° C. to 300 ° C.

If the heat treatment holding time is less than 1/2 hour, the film is not properly formed, and even if only 1/2 hour or more, the film is sufficiently formed. Therefore, it is preferable to perform 1/2 hour to 1 hour.

The solution removes H ₂ O contained in the film through a high temperature heat treatment (Bake) to form an inorganic planarization film 360 which is finally formed of a silicon oxide film (SiO ₂ ).

In the inorganic planarization film 360 formed by the manufacturing method, the lower step is offset by the applied solution.

Hereinafter, a reaction mechanism in which the inorganic planarization film 360 is formed of SiO ₂ will be described.

Table 1 describes the physical / chemical changes to aid in understanding the SiO ₂ formation mechanism.

Abbreviation Name Scheme A Hydrolysis ≡Si-OE + H ₂ 0-> ≡Si-OH B Condensation    ≡Si-OH + HO-Si ≡-> ≡Si-O-Si C Condensation    ≡Si-OEt + HO-Si ≡-> ≡Si-O-Si D Decomposition    ≡Si-OEt-> ≡Si-OH E Evaporation F Dehydration G Viscous Sintering

Table 2 below shows the SiO ₂ formation reaction mechanism.

With reference to Table 2, the reaction mechanism is described by dividing into steps I to V.

Step I-A solution containing 10 wt% to 20 wt% of methyl siloxane in a solvent (PGMEA) or a solution containing 5 wt% to 35 wt% of hydroxysilsesquioxane (HSQ) in a solvent (PGMEA) Prepare.

In this process, [Si (Oet) _a (OH) _b O _c ] _n , a solvent (PGMEA), and H ₂ O are prepared.

At this time, c = 1/2 (4-a-b). (a, b, c, n are integers)

Step II-The material of I is applied to the substrate by spin coating.

This process involves A, B, E reactions to produce [Si (OEt) _a '(OH) _b ' O _c '] _n ', with solvent (PGMEA) and H ₂ 0 present. At this time, a '<a, b'<b, c '> c and n'> n are satisfied.

(a ', b', c ', n' are integers)

Step III-Bake the material produced in step II.

This process involves the reaction of B, C, E below 250 ° C to produce [Si (Oet) _a "(OH) _b " O _c "] _n ". At this time, alcohols (Alcohols) and water (H ₂ O) of the formed material satisfying a "<a ', b"<b', c "> c ', n"-> ∞ are hydrogen bonded (Hydrogen Bonded). Has

(a ", b", c ", n" are integers)

Step IV- The material produced in step III produces [Si (OH) _x O _y ] _∞ below 425 ° C.

At this time, head towards x-> 0, y-> 2 and track H ₂ O.

Step V- The material produced in IV is accompanied with the B, F, G reaction below 900 ℃ to form a silicon oxide film (SiO ₂ ) as the final product of the reaction.

In the reaction mechanism, the silicon oxide film (SiO ₂ ) was formed at a high temperature of 900 ° C. or lower, but in the present invention, since the glass transition temperature (Tg) of the substrate is 250 ° C. to 300 ° C., the silicon oxide film ( It is preferable to form SiO ₂ ).

In the embodiment of the present invention by the reaction mechanism was measured the contact angle (Contact Angle) of the material produced at 200 ℃ to 300 ℃ showed a contact angle of 30 °, such as the silicon oxide film (SiO ₂ ) produced below 900 ℃ Through this, it could be confirmed that the material of the present invention is the same material as the silicon oxide film (SiO ₂ ).

In addition, a passivation film 350 made of a silicon nitride film may be further formed under the inorganic planarization film 360 formed of the silicon oxide film. The passivation film can be formed by PECVD or LPCVD.

Subsequently, a via hole 355 is formed in the inorganic planarization layer 360 to expose any one of the source / drain electrodes 345. The first electrode 370 is stacked and patterned on the inorganic planarization layer 360 on which the via hole 355 is formed. As a result, the first electrode 370 is formed on the bottom of the via hole 355 to be in contact with the exposed source / drain electrode 345 and extend on the inorganic planarization layer 360.

The first electrode 370 is formed by a method such as sputtering or ion plating. Preferably, the first electrode 370 is formed by a conventional method of sputtering. The first electrode 370 is patterned through a wet etching process that is selectively removed using a pattern of a photoresist (PR) layer formed in a photolithography process after deposition .

Subsequently, a pixel defining layer 375 is formed of an insulating material to define a pixel region on the first electrode 370 and to insulate the organic light emitting layer, and then, the photoresist PR is used as a mask, and the opening is formed through dry etching. To form.

The organic layer 380 is laminated by vacuum deposition, spin coating, inkjet printing, laser thermal transfer (LITI), or the like. Preferably, the lamination is performed by spin coating. In addition, the patterning of the organic layer 380 may be implemented using laser thermal transfer, vacuum deposition using a shadow mask, or the like.

The organic light emitting layer may be a low molecular material or a high molecular material. The low molecular weight material is formed of one selected from the group consisting of aluminy chironium complex (Alq3), anthracene (Anthracene), cyclo pentadiene (Cyclo pentadiene), BeBq2, Almq, ZnPBO, Balq, DPVBi, BSA-2 and 2PSP. . Preferably, the organic light emitting layer is formed of an aluminy chinolium composite (Alq3).

The polymer material is poly (p-phenylenevinylene) (PPV; poly (p-phenylenevinylene)) and its derivatives, polythiophene (PT) and its derivatives and polyphenylene (PPP; polyphenylene) and its derivatives It is preferable to form one selected from the group consisting of.

Subsequently, a second electrode 390 is formed on the organic layer 380. The second electrode 390 is formed by a vacuum deposition method.

Hereinafter, one experimental example of the present invention is presented. However, the following experimental examples are provided only for better understanding of the present invention, and the present invention is not limited to the following experimental examples.

Experimental Example

A test substrate was manufactured based on the top-emitting organic light emitting display device.

Provided is an insulating glass substrate formed with a thin film transistor, a passivation film is formed on the thin film transistor, the content of methyl siloxane (Metyl siloxane) (manufactured by Honeywell) to the propylene glycol monomethyl ether acetate (PGMEA) as a solvent on the passivation The 15 wt% solution was spin-coated for 10 seconds at 300 rpm using a spin coating method to deposit a uniform film having a thickness of 2.29 µm to 2.39 µm. Subsequently, the deposited film was subjected to a heat treatment process having a holding time of 1 hour at a high temperature of 250 ° C. to form an inorganic planarization film made of a silicon oxide film (SiO ₂ ).

3 is a cross-sectional photograph of an inorganic planarization film formed on the thin film transistor of the substrate according to the experimental example of the present invention.

The d1 represents the sum of the passivation film 350 and the inorganic planarization film 360.

D2 represents the sum of thicknesses of the source / drain electrodes 345, the passivation layer 350, and the inorganic planarization layer 360.

The d2 includes a source / drain electrode having a thickness of 0.49 µm, but the thickness difference with d1 is 0.1 µm, and it does not show a significant difference within an error range of ± 0.05 µm.

The passivation film 350 formed of the silicon nitride film SiNx is poor in the planarization property of canceling the lower step through the experimental example, and the inorganic planarization film 360 formed of the silicon oxide film SiO ₂ has the planarization of canceling the lower step. It was confirmed that the characteristics are excellent.

Accordingly, when the planarization film is deposited during the manufacturing process of the organic light emitting display device, the solution is applied by a coating method and then formed into an inorganic planarization film through a high temperature heat treatment process, thereby canceling the lower step so that the adhesion and opening ratio of the first electrode are offset. In the subsequent process, the organic light emitting layer may be prevented from deterioration of the organic light emitting layer by the outgassing such as H ₂ 0, 0 _2, etc. from the planarization layer after the deposition of the organic layer in the organic layer, and the life of the organic light emitting layer may be improved. .

As described above, according to the present invention, by forming the inorganic planarization film, the lower level difference is canceled by the method of manufacturing the inorganic planarization film to improve the step coverage of the first electrode, thereby improving the adhesion and opening ratio of the first electrode, and In the case where the electrode is an anode, an organic light emitting layer is prevented from increasing the surface resistance of the first electrode and deterioration of the inorganic planarization layer and outgassing from the inorganic planarization layer such as H ₂ O, 0 ₂ into the organic layer after deposition of the organic layer. It is possible to prevent the pixel shrinkage phenomenon and to improve the lifespan of the organic light emitting layer by preventing deterioration of the organic light emitting layer.

In addition, by forming an inorganic planarization film having a passivation function, the passivation film lamination process can be omitted, thereby improving productivity through shortening of air.

Claims (30)

delete delete delete delete delete delete delete delete delete delete delete Providing a substrate; Forming a thin film transistor on the substrate; Forming an inorganic planarization layer on the thin film transistor; Forming a first electrode on the inorganic planarization film; Forming a pixel definition layer having an opening on the first electrode; Forming an organic layer including at least an organic light emitting layer on the first electrode, and Forming a second electrode on the organic layer; The inorganic planarization film is a method of manufacturing an organic light emitting display device, characterized in that the solution is applied by a coating method and then formed through a high temperature heat treatment process. delete delete The method of claim 12, The silicon-based material is a method of manufacturing an organic light emitting display device, characterized in that the silicon oxide film (SiO ₂ ). The method of claim 12, The inorganic planarization film is a method for manufacturing an organic light emitting display device, characterized in that the insulating film layer having a passivation function of the thin film transistor. The method of claim 12, The inorganic planarization layer is formed by using a solution in which methyl siloxane and a solvent (PGMEA) are mixed or a solution in which hydrogen silsesquioxane and a solvent (PGMEA) are mixed. Manufacturing method of display element. The method of claim 12, The solution may be a solution having a methylsiloxane content of 10 wt% to 20 wt% with respect to a solvent (PGMEA) or a solution having a content of 5 wt% to 35 wt% of hydroxysilsesquioxane (HSQ) with respect to a solvent (PGMEA). A method of manufacturing an organic light emitting display device. The method of claim 12, The coating method of manufacturing an organic light emitting display device, characterized in that the spin speed is performed for 1 second to 30 seconds at 100rpm to 1300rpm. The method of claim 12, The thickness of the inorganic planarization film is a manufacturing method of the organic light emitting display device, characterized in that 1㎛ 2㎛. The method of claim 12, The heat treatment temperature of the inorganic planarization film is a manufacturing method of an organic light emitting display device, characterized in that performed at 200 ℃ to 300 ℃. The method of claim 12, A method of manufacturing an organic light emitting display device, wherein the holding time of the heat treatment process of the inorganic planarization film is performed within a range of 1/2 hour to 1 hour. The method of claim 12, The inorganic planarization film is a method of manufacturing an organic light emitting display device, characterized in that to form a silicon oxide film (SiO ₂ ) by removing the H ₂ O contained in the film through a heat treatment process. The method of claim 12, The inorganic planarization film is a manufacturing method of an organic light emitting display device comprising further forming a passivation film on the bottom. The method of claim 12, The passivation film is a method of manufacturing an organic light emitting display device, characterized in that formed with an inorganic material. The method of claim 25, The inorganic material is a method of manufacturing an organic light emitting display device, characterized in that the silicon nitride film. The method of claim 12, The first electrode is an anode, and the second electrode is a cathode. The method of claim 12, The first electrode is a cathode, and the second electrode is an anode. The method of claim 12, The pixel definition layer is a polyimide, a method of manufacturing an organic light emitting display device, characterized in that it is made of any one of an organic material of silicon resin and silicon oxide film. The method of claim 12, The opening of the pixel definition layer is formed by dry etching.

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