KR100653358B1 - A parallel multiplier in the finite field - Google Patents

Abstract

A parallel multiplier for a finite field is provided to usefully apply to implementation of hardware in encryption-related application fields by having the same space/time complexity as the most efficient Reyhani-Masoleh and Hansan multiplier. An AB multiplier(100) multiplies input 'A' and 'B' by a formula-1. An 'x' function part(110) operates the input 'A' and 'B' by a formula-2. An S1 function part(120) performs right cyclic shift according to a formula-3 by using a result value of the 'x' function part. A BTX1 multiplier(130) maps/adds the result value of the AB multiplier and the S1 function part to each cipher of the final output by a formular-4.

Description

A parallel multiplier in the finite field

1 is a block diagram showing the configuration of a finite field parallel multiplication apparatus according to the present invention.

FIG. 2 is a block diagram illustrating a more detailed configuration of the x function unit of FIG. 1.

3 is a block diagram illustrating a more detailed configuration of the subgroup of FIG. 2.

4 is a block diagram illustrating a more detailed configuration of the BTX1 calculator of FIG. 1.

FIG. 5 illustrates a more detailed configuration of the sub-BTX1 calculator of FIG. 4.

6 is a block diagram illustrating the concept of a parallel multiplication apparatus according to the present invention.

FIG. 7 shows a detailed block diagram of a parallel multiplier using AOP, corresponding to an embodiment of the present invention.

8 illustrates a block for a y _{j , i} operation as a gate.

Figure 9 illustrates one embodiment of a parallel multiplication operator of finite field GF (2 ⁷ ) with Gaussian normal basis of type IV.

The present invention relates to a multiplication device, and more particularly, to a parallel multiplying device of a finite field.

Finite bodies are applied in cryptography and coding theory, and they are actively used in related applications such as elliptic curve cryptography (ECC), XTR, and ElGamal type cryptography. In particular, the finite field GF (2 ^m ) is a number system including 2 ^m elements, and since each element of the finite field can be represented by n bits, it is widely used for applications such as error correction codes and hardware implementations of cryptographic systems. These basically include finite field operations, which determine the efficiency of the cryptographic system. Therefore, the speedup of the operation defined in the finite field is very important and has been the subject of much research.

The operation of finite field depends on the expression method, and there are representative polynomial basis, regular basis, etc., and nonconvention basis is used. In particular, in the case of using a normal basis, the square operation is used for hardware implementation because it has many advantages such as cyclic shift. Among them, the finite field having the type I optimal normal basis generated by the contract AOP (All one polynomial) shows the highest efficiency. There is a need for a finite field multiplication apparatus excellent in space and time complexity.

Aspect of the present invention is the type I based on the partial body and the type of finite field GF (2 ^m) having a Gaussian period of (m, k) of the finite field GF (2 ^m) having the optimal normal basis, oval In cryptographic system applications, such as curve ciphers, the prime m is mainly used, so only the case of m is an odd number, and the finite field GF (2 ^mk ) uses the parallel multiplication operator Reyhani-Masoleh and Hasan's Type I operator. It is to provide a finite field multiplication apparatus that performs multiplication at GF (2 ^m ).

In accordance with the present invention for achieving the above technical problem, the finite-body parallel multiplication apparatus has a Gaussian normal basis whose finite field GF (2 ^m ) is of type k, where GF (n + 1) ^* = <2> and n = AB multiplication unit for multiplying A, B by Equation 1 with A _i * B _i for inputs A, B (A, B are vectors) satisfying the condition of mk; An x function unit computed by Equation 2 on inputs A and B; An S1 function unit performing a right cyclic shift according to Equation 3 by inputting a result value of the x function unit; And a BTX1 calculation unit for mapping the result value of the AB multiplication unit and the result value of the S1 function unit to each position of the final output by mapping (4).

[Equation 1]

A * B = A _i * B _i

[Equation 2]

[Equation 3]

S1 =

[Equation 4]

[Equation 5]

The AB multiplication unit performs an AND operation on the input A and the input B, and preferably consists of as many AND gates as the number of m in the finite field GF (2 ^m ). The x function portion is made up of u = (m-1) / 2 groups, the group is made up of m subgroups, and the subgroups are logical products of Aj and B _{(( i0 + j))} . 1AND gate; A second AND gate for performing an AND operation on A _{(( i0 + j))} and Bj; And an XOR gate that exclusively combines the outputs of the first and second AND gates. Where ((a + b)) is ((a + b)) = (a + b) mod m

함수에 의해 m 개의 출력으로 오른쪽 순환이동 매핑함이 바람직하다.The S1 function unit comprises an S1 function mapping group corresponding to the number of subgroups (u) of the x function unit, the S1 function mapping group consists of k unit mapping units, and the unit mapping unit is a subgroup of the x function unit By using m bits of data output from

It is preferable to map the right shift to m outputs by a function.

The BTX1 operator comprises m sub-BTX1 operators, and the sub-BTX1 operator performs an exclusive logical sum operation on an input value determined by Equation 4 with respect to a result value of the AB multiplication unit and a result value of the unit mapping unit of the S1 function unit. XOR gate is preferably composed of a binary tree.

In accordance with the present invention for achieving the above technical problem, the finite-body parallel multiplication apparatus has a Gaussian normal basis whose finite field GF (2 ^m ) is of type k, where GF (n + 1) ^* = <2> and n = AB multiplication unit for multiplying A, B by Equation 1 with A _i * B _i for inputs A, B (A, B are vectors) satisfying the condition of mk; A y function unit computed by Equation 6 on inputs A and B; An S2 function unit performing a right cyclic shift according to Equation 7 by inputting a result value of the y function unit; And a BTX2 calculation unit configured to add the result of the AB multiplication unit and the result of the S2 function unit by adding Equation 4 to each position of the final output.

[Equation 6]

here,

[Equation 7]

S2 =

[Equation 8]

here,

The AB multiplication unit performs an AND operation on the input A and the input B, and preferably consists of as many AND gates as the number of m in the finite field GF (2 ^m ). The y function portion is composed of m groups, the group is composed of u = (m-1) / 2 subgroups, and the subgroups are formed by performing an exclusive logic operation on Aj and A _{(( i0 + j))} . 1XOR gate; (Where ((a + b)) is ((a + b)) = (a + b) mod m.) A second XOR gate that performs an exclusive logic operation on Bj and B _{(( i0 + j))} ; And an AND gate for performing an AND operation on the outputs of the first and second XOR gates.

함수에 의해 m 개의 출력으로 오른쪽 순환이동 매핑함이 바람직하다.The S2 function unit is composed of S2 function mapping groups corresponding to the number of subgroups (u) of the y function unit, the S2 function mapping group is composed of k unit mapping units, and the unit mapping unit is a subgroup of the y function unit By using m bits of data output from

It is preferable to map the right shift to m outputs by a function.

The BTX2 operator comprises m sub-BTX2 operators, and the sub-BTX2 operator performs an exclusive logical sum operation on an input value determined by Equation 8 with respect to a result value of the AB multiplier and a result value of the unit mapping unit of the S2 function unit. XOR gate is preferably composed of a binary tree.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the parallel multiplication apparatus of the finite body according to the present invention.

이 GF(2) 위에서 GF(2^m)의 기저 (Basis)일 때 N을 정규기저라 하고, β를 정규기저 생성자라 한다. 따라서 A∈GF(2^m)에 대하여

로 표현되며 좌표로

와 같이 나타낸다. 또한 벡터 (행렬)표현으로 다음과 나타내며 T는 행렬의 치환 (Transpose)을 나타낸다. First, the basic mathematical background for the present invention will be described. For a positive integer m there is a normal basis of GF (2 ^m ) above finite field GF (2). That is β∈GF (2 ^m )

When GF (2) is the basis of GF ( ^2m ), N is called normal basis, and β is called normal basis generator. Thus for A∈GF (2 ^m )

Expressed in coordinates

It is represented as Also, the vector (matrix) representation is as follows and T represents the transpose of the matrix.

이고, 이는 오른쪽 순환이동 (Right cyclic shift, RCS)로 수행이 된다. For any element A∈GF (2 ^m ), A ² is represented by coordinates

This is performed by right cyclic shift (RCS).

, kth root of unity를 τ이고,

이라고 하면 β는 유한체 GF(2^m)의 정규기저 생성자이다. 즉

은 유한체 GF(2) 위에서 GF(2^m)의 정규기저로, 이 때 β를 유한체 GF(2) 위에서 타입 (m,k) 인 가우스 주기 (Gauss period of type (m,k))라 한다. 본 발명에서는 유한체 GF(2^m)이 타입(m,k)인 가우스 주기를 가지는 경우 유한체 GF(2^m)를 타입 k라고 한다. 또한 모든 계수가 1인 다항식인

을 All one polynomial(AOP)라 한다. 이 때 k=1인 경우 타입 I 최적 정규기저라고 하며, k=2 인 경우 타입 II 최적 정규기저라고 한다. 또한 n=mk인 경우 유한체 GF(2^m)은 GF(2ⁿ)의 부분체이다. m, k is a positive number and p = mk + 1 ≠ 2 is a prime, the order of 2 in the finite field GF (p) ^* is e and GCD (mk / e, m) = 1. A primitive nth root of unity at finite field GF (2 ⁿ ), n = mk

, kth root of unity is τ,

Is the normal basis constructor of the finite field GF (2 ^m ). In other words

Is the normal basis of GF (2 ^m ) above finite field GF (2), where β is the Gaussian period of type (m, k) above finite field GF (2). do. In the present invention, when the finite field GF ( ^2m ) has a Gaussian period of type (m, k), the finite field GF ( ^2m ) is referred to as type k. Also, a polynomial with all coefficients equal to 1

Is called All one polynomial (AOP). In this case, k = 1 is called type I optimal normal basis, and k = 2 is called type II optimal normal basis. In addition, when n = mk, the finite field GF ( ^2m ) is a part of GF ( ²ⁿ ).

Theorem 1. (Type I Optimal Normal Basis)

가 유한체 GF(2) 위에서 기약다항식인 경우 AOP의 근은 최적 정규기저의 생성자이다.The necessary conditions for GF (2 ⁿ ) to have an optimal normal basis of type I on the finite field GF (2) are (n + 1) prime and GF (n + 1) ^* = <2>. Or nth AOP

If is a contract polynomial on the finite field GF (2), the root of the AOP is the constructor of the optimal normal basis.

Theorem 2. (Optimum Normal Basis for Type II)

는 유한체 GF(2)위에서 GF(2^m)의 최적 정규기저 생성자이다. 여기서

는 (2m+1)의 원시근이다.The necessary and sufficient condition for GF (2 ⁿ ) to have an optimal normal basis of type II on finite field GF (2) is that (2m + 1) is prime and GF (2m + 1) ^* = <2> or 2m + 1 Mod3 mod 4 and GF (2m + 1) ^* = <-1,2>

Is the optimal normal basis constructor of GF (2 ^m ) on finite field GF (2). here

Is the root of (2m + 1).

즉

이 (n+1)의 원시근이면, 정리 1에 의해

는 유한체 GF(2ⁿ)의 타입 I 최적 정규기저 생성자이다. 또한, e=mk, τ=2^m이므로, (m,k)는 가우스 주기이며,

는 유한체 GF(2)위에서 GF(2^m)의 정규기저 생성자이다. 따라서 임의의 원소 A∈GF(2^m)는 In the present invention, the case where m is odd, n = mk, (n + 1) is prime and GF (n + 1) ^* = <2> is considered.

In other words

If this is the (n + 1) primitive root, theorem 1

Is the type I optimal normal basis constructor of the finite field GF (2 ⁿ ). Further, since e = mk and τ = 2 ^m , (m, k) is a Gaussian period,

Is the normal basis constructor of GF (2 ^m ) on finite field GF (2). So any element A∈GF (2 ^m )

와 같이 표현된다. 유한체 GF(2^m)는 GF(2ⁿ)의 부분체이므로, A∈GF(2ⁿ) 이고,

It is expressed as Finite field GF (2 ^m ) is a subdivision of GF (2 ⁿ ), so A∈GF (2 ⁿ ),

to be. Arbitrary elements

이면

Back side

[Equation 1]

to be.

The same properties as in Equation 1 are satisfied.

(2) Type I calculator using Reyhani-Masoleh and Hasan's AOP

If any two elements in the finite field GF (2 ^m ) are C = AB for A and B, then the product of C is expressed as

[Equation 2]

을 구성하며 수학식 2에서 곱의 행렬 M을 다음과 같이 다시 표현한다.Using base N

The matrix M of the product in Equation 2 is expressed as follows.

Using the square operation as a circular shift operation, the product C = AB = (c ₀ , c ₁ , ..., c _m-1 ) is expressed as

Therefore, for each i, it can be seen that the number of 1s in the matrix M _i is the same, and the number of 1s in M _o is called the complexity of the normal basis B and denoted by C _N. Gao et al. Also proved that C _N ≥2m-1. If C _N = 2m-1, the normal basis N is called an optimal normal basis (ONB).

① Multiplier using AOP of Reyhani-Masoleh and Hasan

)을 다음과 같이 분리하였다.Reyhani-Masoleh and Hasan are the matrix of finite products M = (

) Were separated as follows.

이면 U의 모든 원소는

로 표현되므로 다음과 같은 정리를 제시하였다.if

If all elements of U are

The following theorem is presented.

이면 C=AB는 다음과 같다.Theorem 3.

Then C = AB is

이다.

는 XOR 연산자이고, ·는 AND 연산자이며 모든 색인은 모듈러 m값이다.Where a _j , b _j are the coordinates of A, B

to be.

Is the XOR operator, · is the AND operator, and all indexes are modular m values.

에 의해 생성되고, AOP의 근을

라 하자. 이 때

는 유한체 GF(2ⁿ)의 타입 I 최적 정규기저를 생성하며, 정리 3을 정리 4와 같이 적용할 수 있다. 여기서 <<i+j>>는 i+j mod n을 의미한다.Finite Field GF (2 ⁿ ) is a Polynomial AOP

Generated by the root of the AOP

Let's do it. At this time

Produces a type I optimal normal basis of finite field GF (2 ⁿ ), and theorem 3 can be applied as theorem 4. Here, << i + j >> means i + j mod n.

는 이 정규기저의 생성자이라고 하자. 임의의 원소 이면 는 다음과 같다. Theorem 4. Finite Field Type I Having Optimal Normal Basis

Let is the constructor of this regular basis. If it is an arbitrary element, then

A multiplier that reduces the AND operation of Reyhani-Masoleh and Hasan

In 2003, Reyhani-Masoleh and Hasan proposed a parallel multiplication algorithm that reduces the AND operation based on the product of theorem 5.

이면 C=AB는 다음과 같다.5. The Random Element

Then C = AB is

이고 모든 색인은 모듈러 m 값이다.

And all indexes are modular m values.

(3) Structure of Parallel Multiplier According to the Present Invention

일 때 2002년과 2003년에 각각 제안된 Reyhani-Masoleh과 Hasan의 기본 타입 I 연산기를 활용하여 새로운 병렬 곱셈 연산 C=AB를 수행하는 연산기를 구성한다. 본 발명에서 이용할

는 다음과 같이 정의한다.In the present invention, a case in which the finite field GF ( ^2m ) has a Gaussian normal basis of type k, and GF (n + 1) ^* = <2> and n = mk is considered. The present invention proposed a new parallel computing for finite field multiplication by using the arithmetic unit of the type I parallel multiplication operator Reyhani-Masoleh and Hasan in GF (2 ⁿ⁾ perform the multiplication in the finite field GF (2 ^m). Random elements

Is constructed using the Reyhani-Masoleh and Hasan basic Type I operators proposed in 2002 and 2003 respectively. Use in the present invention

Is defined as:

이라 하자. 이 때

에 대해

인 경우 다음과 같이

를 정의 한다.Definition 1. n = mk, (n + 1) is prime, GF (n + 1) ^* = <2> and k _i is

Let's say At this time

About

If is

Define.

① Parallel multiplier in finite field GF (2 ^m ) according to the present invention using Reyhani-Masoleh and Hasan multiplier

이므로 n개의 계산이 필요하다. 그러나 본 발명에서는

는 m개만 계산한다. 또한

은 식 (1)에 의해

임을 이용하여 연산한다. The present invention constitutes a parallel multiplier by considering the elements A and B of the finite field GF ( ^2m ) as elements of the enlarged body GF ( ²ⁿ ) having an optimal normal basis of type I. In the 2002 Reyhani-Masoleh and Hasan calculator

N calculations are required. However, in the present invention

Counts only m. Also

By the equation (1)

Calculate using

에 대하여 B_i 통과한 후 S_i에서의 연산은

을 만족하는 k_i에 따라 오른쪽 순환이동(RCS)에 의하여 수행된다. 한편

이므로 m개의 좌표가 k번 반복하여 표현되며

이므로 0부터 m-1까지의 좌표만 고려한다. 따라서

에 대해 Bi,

경우

로부터 S_i의 출력값은 앞에 정의한

에 의한 RCS에 의하여 주어진다. In the multiplier of Reyhani-Masoleh and Hasan

After passing through B _i , the operation in S _i

Is performed by right circular shift (RCS) according to k _i satisfying. Meanwhile

M coordinates are repeated k times.

Therefore, only coordinates from 0 to m-1 are considered. therefore

About Bi,

Occation

The output of S _i from

Given by RCS.

에 대해 본 발명에서 제안하는 C=AB는 다음과 같다.Arbitrary elements

C = AB proposed by the present invention is as follows.

1 is a block diagram showing the configuration of a parallel multiplication apparatus of a finite body according to the present invention. The parallel multiplication apparatus includes an AB multiplication unit 100, an x function unit 110, an S1 function unit 120, and a BTX1 operation unit. 130 is made.

The AB multiplication unit 100 has a Gaussian normal basis of finite field GF (2 ^m ) of type k, and inputs A and B (s) satisfying the condition that GF (n + 1) ^* = <2> and n = mk ( A and B are multiplied by Equation 1 by A _i * B _i .

A * B = A _i * B _i

The AB multiplication unit 100 performs an AND operation on the input A and the input B, and preferably consists of AND gates corresponding to the number of m in the finite field GF (2 ^m ).

The x function 110 is calculated by Equation 2 with respect to inputs A and B.

FIG. 2 is a block diagram showing a more detailed configuration of the x function unit 110, where u = (m-1) / 2 groups, and the group consists of m subgroups.

3 is a block diagram illustrating a more detailed configuration of the subgroup, in which the subgroup is the first AND gate 300 and A _{(( i0 + j) for} performing an AND operation on Aj and B _{(( i0 + j)) . )} And a second AND gate 320 that performs an AND operation on Bj and an XOR gate 340 that exclusively sums the outputs of the first AND gate 300 and the second AND gate 320. Where ((a + b)) is ((a + b)) = (a + b) mod m

The S1 function unit 120 performs a right cyclic shift according to Equation 3 by inputting the result value of the x function unit 110.

S1 =

S1 =

함수에 의해 The S1 function unit 130 is composed of an S1 function mapping group corresponding to the number of subgroups (u) of the x function unit. The S1 function mapping group includes k unit mapping units. The unit mapping unit receives m-bit data output from the subgroup of the x function unit as an equation (5).

By function

Maps right shift with m outputs.

The BTX1 calculator 130 maps the result value of the AB multiplier 100 and the result value of the S1 function unit 120 to each digit of the final output by using Equation 4 below.

4 is a block diagram illustrating a more detailed configuration of the BTX1 calculator 130, and the BTX1 calculator comprises m sub-BTX1 calculators 400, 410, and 420. Referring to FIG.

FIG. 5 illustrates a more detailed configuration of the sub-BTX1 calculation unit 400. The result value of the AB multiplication unit 100 and the result value of the unit mapping unit of the S1 function unit 120 are expressed by Equation 4 below. An XOR gate that performs an exclusive logic operation on the input value determined by the binary tree is configured.

6 is a block diagram illustrating the concept of a parallel multiplication apparatus according to the present invention.

FIG. 7 shows a detailed block diagram of a parallel multiplier using AOP, corresponding to an embodiment of the present invention.

② Parallel multiplier in finite field GF (2 ^m ) according to the present invention using Reyhani-Masoleh and Hasan multiplier

가 이 정규기저의 생성자라고 하고, 임의의 원소

이면 C=AB는 다음과 같다.The present invention constructs a new parallel multiplication operator that performs multiplication on the finite field GF (2 ^m ) by using the AND reduction algorithm proposed by Reyhani-Masoleh and Hasan in 2003. That is, finite field GF (2 ⁿ ) has an optimal normal basis of type I

Is the constructor of this regular basis,

Then C = AB is

를 계산해야 한다. 그러나 본 발명에서는 수학식 1에 의하여

만 계산하면 된다. 따라서 m개의 AND연산이 주어진다. 또한,

를 계산하기 위해 수학식 1이 성립하므로, 다음이 성립한다.In conventional multipliers

Must be calculated. In the present invention, however,

You only need to calculate. Thus m AND operations are given. Also,

Equation 1 holds to calculate, so the following holds.

과Also

and

일 때 다음과 같다.

When

인 경우

라 하면

이며 다음과 같다.if,

If

If

And is as follows.

인 경우 다음이 성립한다.

If, the following holds true.

는 ,

인 경우만 계산하며,

의 계산은 할 필요가 없음을 알 수 있다. 유한체 GF(2^m)은 GF(2ⁿ)의 부분체이므로 부분체의 성질에 의하여 GF(2ⁿ)에서 m개의 좌표를 수행한다. 따라서 타입 k인 유한체 GF(2^m)에서 n=mk, GF(n+1)^*=<2> 라 하고, 임의의 원소

이면 C=AB는 다음과 같다.therefore

Is,

Only counts if

It can be seen that there is no need to calculate. Finite field GF (2 ^m) performs m-coordinate in the GF (2 ^n), by the nature of the body portion is the part of the body GF (2 ^n). Therefore, in the finite field GF (2 ^m ) of type k, n = mk, GF (n + 1) ^* = <2>

Then C = AB is

로 바꾸어 다시 구성하면 도 8과 같다. 또한

값이 BTX의 j번째 좌표의 입력값이 되도록 조정한다.The parallel multiplier proposed by the present invention inputs A _j , _i such that the output of B _i is y _{j, i} .

It is as shown in FIG. Also

Adjust the value to be the input value of the jth coordinate of BTX.

The parallel multiplier in the finite field GF (2 ^m ) according to the present invention using the multiplier of Reyhani-Masoleh and Hasan described above comprises an AB multiplication unit, a y function unit, an S2 function unit, and a BTX2 operation unit.

The AB multiplication unit has a Gaussian normal basis of finite field GF (2 ^m ) of type k, and inputs A, B (A, B) satisfying the condition that GF (n + 1) ^* = <2> and n = mk Vector), A and B are multiplied by Equation 1 by A _i * B _i .

The AB multiplication unit performs an AND operation on the input A and the input B, and is composed of as many AND gates as the number of m in the finite field GF (2 ^m ).

The y function unit is calculated by Equation 6 with respect to inputs A and B.

here,

The y function portion consists of m groups, and the group consists of u = (m-1) / 2 subgroups. The subgroup includes a first XOR gate for performing an exclusive logic operation on Aj and A _{(( i0 + j))} , a second XOR gate for performing an exclusive logic operation on Bj and B _{(( i0 + j))} , and the first XOR gate and a first operation. And an AND gate for performing an AND operation on the output of the 2XOR gate. Where ((a + b)) is ((a + b)) = (a + b) mod m

The S2 function unit performs a right cyclic shift according to Equation 7 by inputting a result value of the y function unit.

S2 =

S2 =

함수에 의해 m 개의 출력으로 오른쪽 순환이동 매핑한다.The S2 function unit includes an S2 function mapping group corresponding to the number of subgroups (u) of the y function unit, and the S2 function mapping group includes k unit mapping units. The unit mapping unit receives m bits of data output from the subgroup of the y function unit as shown in Equation 5

The right-circular mapping maps to m outputs by function.

[Equation 5]

The BTX2 calculation unit maps the result value of the AB multiplication unit and the result value of the S2 function unit to each position of the final output by adding (4).

here,

The BTX2 operator comprises m sub-BTX2 operators, and the sub-BTX2 operator performs an exclusive logical sum operation on an input value determined by Equation 8 with respect to a result value of the AB multiplier and a result value of the unit mapping unit of the S2 function unit. An XOR gate is composed of a binary tree.

Figure 9 illustrates one embodiment of a parallel multiplication operator of finite field GF (2 ⁷ ) with Gaussian normal basis of type IV.

The present invention can be embodied as code that can be read by a computer (including all devices having an information processing function) in a computer-readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording devices include ROM, RAM, CD-ROM, magnetic tape, floppy disks, optical data storage devices, and the like.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, when the present invention is applied to the cryptographically applied finite chain type k = 2, 4, 6, it has the same space and time complexity as the most efficient multiplier of Reyhani-Masoleh and Hasan. Therefore, it can be usefully applied to hardware implementation of cryptography related fields.

The performance evaluation of the parallel multiplication apparatus according to the present invention is as follows.

① performance

end. If type k = 4

m is odd, p = 4m + 1 is prime, GF (p) ^* = <2> and for u = (m-1) / 2 in Z ^* _p

또는

중 하나가 성립함을 확인하였다. 따라서 타입 IV의 경우는 2m 개의 XOR gate수를 줄일 수 있다. 예를 들어 타입 IV인 권장 타원곡선인 m=163인 경우,

일 때

로 같다. m=409인 경우,

일 때

로 같다.Let's say. for m less than 2000

or

One of them was confirmed to be true. Therefore, in the case of Type IV, the number of 2m XOR gates can be reduced. For example, if m = 163, the recommended elliptic curve of type IV,

when

Is the same as if m = 409

when

Is the same as

I. If type k = 6

가 같은 쌍으로 4개 나타난다. 즉 m=103 인 경우, i=2*103-1.2*103+1 일 때,

이고, i=14,103-14 일 대 14, i=2*103+14.2*103-14 일 때 15, i=15,103-15 일 때 14 이다. 만약 m이 홀수, p=6m+1은 소수, GF(p)^*=<2>라 하면 이를 이용하여

에 대해

일 때

의 같은 쌍이 4개 존재한다. 따라서 타입 VI의 경우는 XOR gate를 8m 개를 감소시킬 수 있다는 것을 알 수 있다.For i for m less than or equal to type k = 6

Appears as four in the same pair. That is, when m = 103, when i = 2 * 103-1.2 * 103 + 1,

I = 14,103-14 days versus 14, i = 2 * 103 + 14.2 * 103-14 and 15 when i = 15,103-15. If m is odd, p = 6m + 1 is prime, GF (p) ^* = <2>

About

when

There are 4 identical pairs of. Therefore, in the case of Type VI, it can be seen that the XOR gate can be reduced by 8m.

All. If type k = 10

의 같은 쌍이 16개 나타난다. 먼저 i₀에 대하여 수학식 4의 에 대한

가 같을 때를

로 표현하면 m=337 인 경우는 다음과 같다.For i for m below 1000 that satisfies type k = 10

16 identical pairs of are shown. First, for i ₀ ,

When is the same

In the case of m = 337,

{6, m-6, 2 * m + 6, 278}, {7, 7, m + 7, 116}, {7, m-7, 2 * m + 7, 0}, {51, m + 51 , 2 * m + 51, 51}, {51, 2 * m-51, 5 * m-51, 272}, {52, m + 52, 2 * m + 51, 109}, {57, m-57 , 5 * m-57, 285}, {58, m-58, 5 * m-58, 0}, {58, 2 * m-58, 4 * m-58, 58}, {59, 2 * m -59, 4 * m-59, 65}, {65, 65, 5 * m-65, 59}, {65, 2 * m + 65, 3 * m + 65, 116}, {109, m + 109 , 4 * m-109, 52}, {109, 2 * m + 109, 5 * m-109, 330}, {116, 116, 2 * m-116, 65}, {116, 2 * m + 116 , 4 * m-116, 7}.

에 대해

일 때

가 같은 쌍이 k=10 이면 16개, k=12 이면 25개 존재한다. 따라서 타입 X의 경우 32m개, XII의 경우 50개의 XOR gate 수를 줄일 수 있다.If m is odd, p = 10m + 1 or 12m + 1 is prime, GF (p) ^* = <2>

About

when

There are 16 pairs of equal pairs if k = 10 and 25 if k = 12. Therefore, the number of 32m gates in type X and 50 gates in XII can be reduced.

On the other hand, the present invention is the maximum complexity when the parallel multiplier in the finite field GF (2 ^m ) using a multiplier of Reyhani-Masoleh and Hasan is as follows. Where T _A is AND delay and T _X is XOR Delay.

a) m ² AND gate.

b) (k + 1) m (m-1) / 2 XOR gate.

c)

In addition, the complexity of the present invention in the finite field GF (2 ^m ) having an optimal normal basis of type II is as follows.

a)

b)

The complexity of the present invention in finite field GF (2 ^m ) with an optimal normal basis of type IV is as follows.

a)

b)

The complexity of the present invention in a finite field with optimal normal basis of type VI is as follows.

a) m ² AND gate, m (7m-23) / 2 XOR gate.

b)

In the present invention, the maximum complexity of the parallel multiplier in the finite field GF (2 ^m ) using the multiplier of Reyhani-Masoleh and Hasan proposed in 2003 is as follows. Where T _A is AND delay and T _X is XOR Delay.

a) m (m + 1) / 2 AND gate.

b) (k + 2) m (m-1) / 2 XOR gate.

c)

In addition, the complexity of the present invention in finite field GF (2 ^m ) with an optimal normal basis of type II is as follows.

a) m (m + 1) AND gate.

b) 2 m (m-1) XOR gate.

c)

The complexity of the present invention in a finite field with an optimal normal basis of type IV is as follows.

a) m (m + 1) / 2 AND gate.

b) m (3m-5) XOR gate.

c)

The complexity of the present invention in finite field GF (2 ^m ) with an optimal normal basis of type VI is as follows.

a) m ² AND gate.

b) 4 m (m-3) XOR gate.

c)

가 각각 일치하므로, 최대 복잡도에서 32m, 50m개의 XOR gate를 빼며 그에 따른 의 T_X값도 줄어들 것이다.In a finite field with a Gaussian period of type (m, 10) or (m, 12), operators of 16, 25 pairs

Are matched, so the 32m and 50m XOR gates will be subtracted from the maximum complexity and the resulting T _X value will be reduced.

② Example

의 값을

와 같이 표현하면 다음과 같다.When m = 7 and k = 4, since n = 29 and p = 29, GF (29) ^* = <2>. K _i for each i

Value of

When expressed as follows.

{1, 5, 5}, {7-1, 12, 6}, {7 + 1, 16, 2}, {2 * 7-1, 27, 0}, {2, 22, 1}, {7 -2, 2, 4}, {7 + 2, 24, 3}, {2 * 7-2, 3, 5}, {3, 10, 3}, {7-3, 21, 3}, {7 +3, 23, 2}, {2 * 7-3, 9, 5}.

에서

이 동일한 값이므로 S₃, S₄는 삭제하여도 된다. therefore,

in

Since these values are the same, S ₃ and S ₄ may be deleted.

Claims (10)

For inputs A and B (A and B are vectors) that have a Gaussian normal basis of type k with finite field GF (2 ^m ) and satisfy the condition that GF (n + 1) ^* = <2> and n = mk , An AB multiplication unit for multiplying A and B by Equation 1 by A _i * B _i ; [Equation 1] A * B = A _i * B _i An x function unit computed by Equation 2 on inputs A and B; [Equation 2]

An S1 function unit performing a right cyclic shift according to Equation 3 by inputting a result value of the x function unit; [Equation 3] S1 =

The result value of the AB multiplication unit and the result value of the S1 function unit are represented by Equation 4 in each position of the final output. [Equation 4]

A finite field parallel multiplication computing device comprising: a BTX1 calculation unit for mapping and adding. The method of claim 1, wherein the AB multiplication unit A logical multiplication operation of input A and input B, wherein the finite field parallel multiplication unit is characterized in that the number of AND gates corresponding to m in the finite field GF (2 ^m ). The method of claim 1, wherein the x function unit u = (m-1) / 2 groups, The group consists of m subgroups, The subgroup A first AND gate for ANDing Aj and B _{((i0 + j))} ; (Where ((a + b)) is ((a + b)) = (a + b) mod m.) A second AND gate for performing an AND operation on A _{((i0 + j))} and Bj; And And an XOR gate configured to exclusively sum the outputs of the first and second AND gates. The method of claim 3, wherein the S1 function unit It consists of S1 function mapping group corresponding to the number of subgroups (u) of x function part, The S1 function mapping group is composed of k unit mapping units, The unit mapping unit receives m-bit data output from the subgroup of the x function unit as an equation (5).

By function [Equation 5]

A finite field parallel multiplication device characterized by mapping right circular to m outputs. The method of claim 4, wherein the BTX1 calculation unit m sub-BTX1 calculation unit, The sub BTX1 calculation unit A parallel multiplication operation of a finite field comprising an XOR gate which performs an exclusive logical sum operation on the result value of the AB multiplication unit and the input value determined by Equation 4 with respect to the result value of the unit mapping unit of the S1 function unit. Device. For inputs A and B (A and B are vectors) that have a Gaussian normal basis of type k with finite field GF (2 ^m ) and satisfy the condition that GF (n + 1) ^* = <2> and n = mk , An AB multiplication unit for multiplying A and B by Equation 1 by A _i * B _i ; [Equation 1] A * B = A _i * B _i A y function unit computed by Equation 6 on inputs A and B; [Equation 6]

here,

An S2 function unit performing a right cyclic shift according to Equation 7 by inputting a result value of the y function unit; [Equation 7] S2 =

The result of the AB multiplication unit and the result of the S2 function unit are represented by Equation 4 in each position of the final output. [Equation 8]

here,

A finite field parallel multiplication computing device comprising: a BTX2 computing unit for mapping and adding. The method of claim 6, wherein the AB multiplication unit A logical multiplication operation of input A and input B, wherein the finite field parallel multiplication unit is characterized in that the number of AND gates corresponding to m in the finite field GF (2 ^m ). The method of claim 6, wherein the y function unit m groups, The group consists of u = (m-1) / 2 subgroups, The subgroup A first XOR gate for performing an exclusive logic operation on Aj and A _{((i0 + j))} ; (Where ((a + b)) is ((a + b)) = (a + b) mod m.) A second XOR gate for performing an exclusive logic operation on Bj and B _{((i0 + j))} ; And And an AND gate for performing logical AND operation on the outputs of the first XOR gate and the second XOR gate. The method of claim 8, wherein the S2 function unit y S2 function mapping group corresponding to the number of subgroups (u) of the function part, The S2 function mapping group is composed of k unit mapping units, The unit mapping unit receives m bits of data output from the subgroup of the y function unit as shown in Equation 5

By function [Equation 5]

A finite field parallel multiplication device characterized by mapping right circular to m outputs. 10. The method of claim 9, wherein the BTX2 calculation unit m sub-BTX2 calculation unit, The sub BTX2 calculation unit A parallel multiplication operation of a finite field comprising an XOR gate that exclusively ORs an input value determined by Equation 8 with respect to a result of the AB multiplication unit and a result of the unit mapping unit of the S2 function unit. Device.

Images